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24#include <linux/printk.h>
25#include <linux/slab.h>
26#include <linux/uaccess.h>
27#include "kfd_priv.h"
28#include "kfd_mqd_manager.h"
29#include "v9_structs.h"
30#include "gc/gc_9_0_offset.h"
31#include "gc/gc_9_0_sh_mask.h"
32#include "sdma0/sdma0_4_0_sh_mask.h"
33#include "amdgpu_amdkfd.h"
34
35static inline struct v9_mqd *get_mqd(void *mqd)
36{
37 return (struct v9_mqd *)mqd;
38}
39
40static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
41{
42 return (struct v9_sdma_mqd *)mqd;
43}
44
45static void update_cu_mask(struct mqd_manager *mm, void *mqd,
46 struct queue_properties *q)
47{
48 struct v9_mqd *m;
49 uint32_t se_mask[4] = {0};
50
51 if (q->cu_mask_count == 0)
52 return;
53
54 mqd_symmetrically_map_cu_mask(mm,
55 q->cu_mask, q->cu_mask_count, se_mask);
56
57 m = get_mqd(mqd);
58 m->compute_static_thread_mgmt_se0 = se_mask[0];
59 m->compute_static_thread_mgmt_se1 = se_mask[1];
60 m->compute_static_thread_mgmt_se2 = se_mask[2];
61 m->compute_static_thread_mgmt_se3 = se_mask[3];
62
63 pr_debug("update cu mask to %#x %#x %#x %#x\n",
64 m->compute_static_thread_mgmt_se0,
65 m->compute_static_thread_mgmt_se1,
66 m->compute_static_thread_mgmt_se2,
67 m->compute_static_thread_mgmt_se3);
68}
69
70static void set_priority(struct v9_mqd *m, struct queue_properties *q)
71{
72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
73 m->cp_hqd_queue_priority = q->priority;
74}
75
76static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
77 struct queue_properties *q)
78{
79 int retval;
80 struct kfd_mem_obj *mqd_mem_obj = NULL;
81
82
83
84
85
86 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
87 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
88 if (!mqd_mem_obj)
89 return NULL;
90 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
91 ALIGN(q->ctl_stack_size, PAGE_SIZE) +
92 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
93 &(mqd_mem_obj->gtt_mem),
94 &(mqd_mem_obj->gpu_addr),
95 (void *)&(mqd_mem_obj->cpu_ptr), true);
96 } else {
97 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd),
98 &mqd_mem_obj);
99 }
100
101 if (retval) {
102 kfree(mqd_mem_obj);
103 return NULL;
104 }
105
106 return mqd_mem_obj;
107
108}
109
110static void init_mqd(struct mqd_manager *mm, void **mqd,
111 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
112 struct queue_properties *q)
113{
114 uint64_t addr;
115 struct v9_mqd *m;
116
117 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
118 addr = mqd_mem_obj->gpu_addr;
119
120 memset(m, 0, sizeof(struct v9_mqd));
121
122 m->header = 0xC0310800;
123 m->compute_pipelinestat_enable = 1;
124 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
125 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
126 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
127 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
128
129 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
130 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
131
132 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
133
134 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
135 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
136
137 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
138 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
139 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
140
141 if (q->format == KFD_QUEUE_FORMAT_AQL) {
142 m->cp_hqd_aql_control =
143 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
144 }
145
146 if (q->tba_addr) {
147 m->compute_pgm_rsrc2 |=
148 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
149 }
150
151 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
152 m->cp_hqd_persistent_state |=
153 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
154 m->cp_hqd_ctx_save_base_addr_lo =
155 lower_32_bits(q->ctx_save_restore_area_address);
156 m->cp_hqd_ctx_save_base_addr_hi =
157 upper_32_bits(q->ctx_save_restore_area_address);
158 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
159 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
160 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
161 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
162 }
163
164 *mqd = m;
165 if (gart_addr)
166 *gart_addr = addr;
167 mm->update_mqd(mm, m, q);
168}
169
170static int load_mqd(struct mqd_manager *mm, void *mqd,
171 uint32_t pipe_id, uint32_t queue_id,
172 struct queue_properties *p, struct mm_struct *mms)
173{
174
175 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
176
177 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
178 (uint32_t __user *)p->write_ptr,
179 wptr_shift, 0, mms);
180}
181
182static void update_mqd(struct mqd_manager *mm, void *mqd,
183 struct queue_properties *q)
184{
185 struct v9_mqd *m;
186
187 m = get_mqd(mqd);
188
189 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
190 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
191 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
192
193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
194 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
195
196 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
197 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
198 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
199 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
200
201 m->cp_hqd_pq_doorbell_control =
202 q->doorbell_off <<
203 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
204 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
205 m->cp_hqd_pq_doorbell_control);
206
207 m->cp_hqd_ib_control =
208 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
209 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT;
210
211
212
213
214
215
216
217
218 m->cp_hqd_eop_control = min(0xA,
219 order_base_2(q->eop_ring_buffer_size / 4) - 1);
220 m->cp_hqd_eop_base_addr_lo =
221 lower_32_bits(q->eop_ring_buffer_address >> 8);
222 m->cp_hqd_eop_base_addr_hi =
223 upper_32_bits(q->eop_ring_buffer_address >> 8);
224
225 m->cp_hqd_iq_timer = 0;
226
227 m->cp_hqd_vmid = q->vmid;
228
229 if (q->format == KFD_QUEUE_FORMAT_AQL) {
230 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
231 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
232 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT |
233 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT;
234 m->cp_hqd_pq_doorbell_control |= 1 <<
235 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
236 }
237 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
238 m->cp_hqd_ctx_save_control = 0;
239
240 update_cu_mask(mm, mqd, q);
241 set_priority(m, q);
242
243 q->is_active = QUEUE_IS_ACTIVE(*q);
244}
245
246
247static int destroy_mqd(struct mqd_manager *mm, void *mqd,
248 enum kfd_preempt_type type,
249 unsigned int timeout, uint32_t pipe_id,
250 uint32_t queue_id)
251{
252 return mm->dev->kfd2kgd->hqd_destroy
253 (mm->dev->kgd, mqd, type, timeout,
254 pipe_id, queue_id);
255}
256
257static void free_mqd(struct mqd_manager *mm, void *mqd,
258 struct kfd_mem_obj *mqd_mem_obj)
259{
260 struct kfd_dev *kfd = mm->dev;
261
262 if (mqd_mem_obj->gtt_mem) {
263 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem);
264 kfree(mqd_mem_obj);
265 } else {
266 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
267 }
268}
269
270static bool is_occupied(struct mqd_manager *mm, void *mqd,
271 uint64_t queue_address, uint32_t pipe_id,
272 uint32_t queue_id)
273{
274 return mm->dev->kfd2kgd->hqd_is_occupied(
275 mm->dev->kgd, queue_address,
276 pipe_id, queue_id);
277}
278
279static int get_wave_state(struct mqd_manager *mm, void *mqd,
280 void __user *ctl_stack,
281 u32 *ctl_stack_used_size,
282 u32 *save_area_used_size)
283{
284 struct v9_mqd *m;
285
286
287 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
288
289 m = get_mqd(mqd);
290
291 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
292 m->cp_hqd_cntl_stack_offset;
293 *save_area_used_size = m->cp_hqd_wg_state_offset;
294
295 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
296 return -EFAULT;
297
298 return 0;
299}
300
301static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
302 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
303 struct queue_properties *q)
304{
305 struct v9_mqd *m;
306
307 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
308
309 m = get_mqd(*mqd);
310
311 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
312 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
313}
314
315static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
316 struct queue_properties *q)
317{
318 struct v9_mqd *m;
319
320 update_mqd(mm, mqd, q);
321
322
323 m = get_mqd(mqd);
324 m->cp_hqd_vmid = q->vmid;
325}
326
327static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
328 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
329 struct queue_properties *q)
330{
331 struct v9_sdma_mqd *m;
332
333 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr;
334
335 memset(m, 0, sizeof(struct v9_sdma_mqd));
336
337 *mqd = m;
338 if (gart_addr)
339 *gart_addr = mqd_mem_obj->gpu_addr;
340
341 mm->update_mqd(mm, m, q);
342}
343
344static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
345 uint32_t pipe_id, uint32_t queue_id,
346 struct queue_properties *p, struct mm_struct *mms)
347{
348 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
349 (uint32_t __user *)p->write_ptr,
350 mms);
351}
352
353#define SDMA_RLC_DUMMY_DEFAULT 0xf
354
355static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
356 struct queue_properties *q)
357{
358 struct v9_sdma_mqd *m;
359
360 m = get_sdma_mqd(mqd);
361 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
362 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
363 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
364 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
365 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
366
367 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
368 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
369 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
370 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
371 m->sdmax_rlcx_doorbell_offset =
372 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
373
374 m->sdma_engine_id = q->sdma_engine_id;
375 m->sdma_queue_id = q->sdma_queue_id;
376 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
377
378 q->is_active = QUEUE_IS_ACTIVE(*q);
379}
380
381
382
383
384
385static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
386 enum kfd_preempt_type type,
387 unsigned int timeout, uint32_t pipe_id,
388 uint32_t queue_id)
389{
390 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
391}
392
393static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
394 uint64_t queue_address, uint32_t pipe_id,
395 uint32_t queue_id)
396{
397 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
398}
399
400#if defined(CONFIG_DEBUG_FS)
401
402static int debugfs_show_mqd(struct seq_file *m, void *data)
403{
404 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
405 data, sizeof(struct v9_mqd), false);
406 return 0;
407}
408
409static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
410{
411 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
412 data, sizeof(struct v9_sdma_mqd), false);
413 return 0;
414}
415
416#endif
417
418struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
419 struct kfd_dev *dev)
420{
421 struct mqd_manager *mqd;
422
423 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
424 return NULL;
425
426 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
427 if (!mqd)
428 return NULL;
429
430 mqd->dev = dev;
431
432 switch (type) {
433 case KFD_MQD_TYPE_CP:
434 case KFD_MQD_TYPE_COMPUTE:
435 mqd->allocate_mqd = allocate_mqd;
436 mqd->init_mqd = init_mqd;
437 mqd->free_mqd = free_mqd;
438 mqd->load_mqd = load_mqd;
439 mqd->update_mqd = update_mqd;
440 mqd->destroy_mqd = destroy_mqd;
441 mqd->is_occupied = is_occupied;
442 mqd->get_wave_state = get_wave_state;
443 mqd->mqd_size = sizeof(struct v9_mqd);
444#if defined(CONFIG_DEBUG_FS)
445 mqd->debugfs_show_mqd = debugfs_show_mqd;
446#endif
447 break;
448 case KFD_MQD_TYPE_HIQ:
449 mqd->allocate_mqd = allocate_hiq_mqd;
450 mqd->init_mqd = init_mqd_hiq;
451 mqd->free_mqd = free_mqd_hiq_sdma;
452 mqd->load_mqd = load_mqd;
453 mqd->update_mqd = update_mqd_hiq;
454 mqd->destroy_mqd = destroy_mqd;
455 mqd->is_occupied = is_occupied;
456 mqd->mqd_size = sizeof(struct v9_mqd);
457#if defined(CONFIG_DEBUG_FS)
458 mqd->debugfs_show_mqd = debugfs_show_mqd;
459#endif
460 break;
461 case KFD_MQD_TYPE_DIQ:
462 mqd->allocate_mqd = allocate_hiq_mqd;
463 mqd->init_mqd = init_mqd_hiq;
464 mqd->free_mqd = free_mqd;
465 mqd->load_mqd = load_mqd;
466 mqd->update_mqd = update_mqd_hiq;
467 mqd->destroy_mqd = destroy_mqd;
468 mqd->is_occupied = is_occupied;
469 mqd->mqd_size = sizeof(struct v9_mqd);
470#if defined(CONFIG_DEBUG_FS)
471 mqd->debugfs_show_mqd = debugfs_show_mqd;
472#endif
473 break;
474 case KFD_MQD_TYPE_SDMA:
475 mqd->allocate_mqd = allocate_sdma_mqd;
476 mqd->init_mqd = init_mqd_sdma;
477 mqd->free_mqd = free_mqd_hiq_sdma;
478 mqd->load_mqd = load_mqd_sdma;
479 mqd->update_mqd = update_mqd_sdma;
480 mqd->destroy_mqd = destroy_mqd_sdma;
481 mqd->is_occupied = is_occupied_sdma;
482 mqd->mqd_size = sizeof(struct v9_sdma_mqd);
483#if defined(CONFIG_DEBUG_FS)
484 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
485#endif
486 break;
487 default:
488 kfree(mqd);
489 return NULL;
490 }
491
492 return mqd;
493}
494
