LXR linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <drm/drm_crtc.h>
  27#include <drm/drm_vblank.h>
  28
  29#include "amdgpu.h"
  30#include "amdgpu_dm.h"
  31#include "dc.h"
  32
  33enum amdgpu_dm_pipe_crc_source {
  34        AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
  35        AMDGPU_DM_PIPE_CRC_SOURCE_AUTO,
  36        AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
  37        AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
  38};
  39
  40static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
  41{
  42        if (!source || !strcmp(source, "none"))
  43                return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
  44        if (!strcmp(source, "auto"))
  45                return AMDGPU_DM_PIPE_CRC_SOURCE_AUTO;
  46
  47        return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
  48}
  49
  50int
  51amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
  52                                 size_t *values_cnt)
  53{
  54        enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
  55
  56        if (source < 0) {
  57                DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
  58                                 src_name, crtc->index);
  59                return -EINVAL;
  60        }
  61
  62        *values_cnt = 3;
  63        return 0;
  64}
  65
  66int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
  67{
  68        struct amdgpu_device *adev = crtc->dev->dev_private;
  69        struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
  70        struct dc_stream_state *stream_state = crtc_state->stream;
  71        bool enable;
  72
  73        enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
  74
  75        if (source < 0) {
  76                DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
  77                                 src_name, crtc->index);
  78                return -EINVAL;
  79        }
  80
  81        if (!stream_state) {
  82                DRM_ERROR("No stream state for CRTC%d\n", crtc->index);
  83                return -EINVAL;
  84        }
  85
  86        enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
  87
  88        mutex_lock(&adev->dm.dc_lock);
  89        if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
  90                                     enable, enable)) {
  91                mutex_unlock(&adev->dm.dc_lock);
  92                return -EINVAL;
  93        }
  94
  95        /* When enabling CRC, we should also disable dithering. */
  96        dc_stream_set_dither_option(stream_state,
  97                                    enable ? DITHER_OPTION_TRUN8
  98                                           : DITHER_OPTION_DEFAULT);
  99
 100        mutex_unlock(&adev->dm.dc_lock);
 101
 102        /*
 103         * Reading the CRC requires the vblank interrupt handler to be
 104         * enabled. Keep a reference until CRC capture stops.
 105         */
 106        if (!crtc_state->crc_enabled && enable)
 107                drm_crtc_vblank_get(crtc);
 108        else if (crtc_state->crc_enabled && !enable)
 109                drm_crtc_vblank_put(crtc);
 110
 111        crtc_state->crc_enabled = enable;
 112
 113        /* Reset crc_skipped on dm state */
 114        crtc_state->crc_skip_count = 0;
 115        return 0;
 116}
 117
 118/**
 119 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
 120 * @crtc: DRM CRTC object.
 121 *
 122 * This function should be called at the end of a vblank, when the fb has been
 123 * fully processed through the pipe.
 124 */
 125void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
 126{
 127        struct dm_crtc_state *crtc_state;
 128        struct dc_stream_state *stream_state;
 129        uint32_t crcs[3];
 130
 131        if (crtc == NULL)
 132                return;
 133
 134        crtc_state = to_dm_crtc_state(crtc->state);
 135        stream_state = crtc_state->stream;
 136
 137        /* Early return if CRC capture is not enabled. */
 138        if (!crtc_state->crc_enabled)
 139                return;
 140
 141        /*
 142         * Since flipping and crc enablement happen asynchronously, we - more
 143         * often than not - will be returning an 'uncooked' crc on first frame.
 144         * Probably because hw isn't ready yet. For added security, skip the
 145         * first two CRC values.
 146         */
 147        if (crtc_state->crc_skip_count < 2) {
 148                crtc_state->crc_skip_count += 1;
 149                return;
 150        }
 151
 152        if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
 153                               &crcs[0], &crcs[1], &crcs[2]))
 154                return;
 155
 156        drm_crtc_add_crc_entry(crtc, true,
 157                               drm_crtc_accurate_vblank_count(crtc), crcs);
 158}
 159