1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31#include "logger_types.h"
32#include "gpio_types.h"
33#include "link_service_types.h"
34#include "grph_object_ctrl_defs.h"
35#include <inc/hw/opp.h>
36
37#include "inc/hw_sequencer.h"
38#include "inc/compressor.h"
39#include "inc/hw/dmcu.h"
40#include "dml/display_mode_lib.h"
41
42#define DC_VER "3.2.35"
43
44#define MAX_SURFACES 3
45#define MAX_PLANES 6
46#define MAX_STREAMS 6
47#define MAX_SINKS_PER_LINK 4
48
49
50
51
52struct dc_versions {
53 const char *dc_ver;
54 struct dmcu_version dmcu_version;
55};
56
57enum dc_plane_type {
58 DC_PLANE_TYPE_INVALID,
59 DC_PLANE_TYPE_DCE_RGB,
60 DC_PLANE_TYPE_DCE_UNDERLAY,
61 DC_PLANE_TYPE_DCN_UNIVERSAL,
62};
63
64struct dc_plane_cap {
65 enum dc_plane_type type;
66 uint32_t blends_with_above : 1;
67 uint32_t blends_with_below : 1;
68 uint32_t per_pixel_alpha : 1;
69 struct {
70 uint32_t argb8888 : 1;
71 uint32_t nv12 : 1;
72 uint32_t fp16 : 1;
73 uint32_t p010 : 1;
74 uint32_t ayuv : 1;
75 } pixel_format_support;
76
77
78
79 struct {
80 uint32_t argb8888;
81 uint32_t nv12;
82 uint32_t fp16;
83 } max_upscale_factor;
84
85
86
87 struct {
88 uint32_t argb8888;
89 uint32_t nv12;
90 uint32_t fp16;
91 } max_downscale_factor;
92};
93
94struct dc_caps {
95 uint32_t max_streams;
96 uint32_t max_links;
97 uint32_t max_audios;
98 uint32_t max_slave_planes;
99 uint32_t max_planes;
100 uint32_t max_downscale_ratio;
101 uint32_t i2c_speed_in_khz;
102 uint32_t dmdata_alloc_size;
103 unsigned int max_cursor_size;
104 unsigned int max_video_width;
105 int linear_pitch_alignment;
106 bool dcc_const_color;
107 bool dynamic_audio;
108 bool is_apu;
109 bool dual_link_dvi;
110 bool post_blend_color_processing;
111 bool force_dp_tps4_for_cp2520;
112 bool disable_dp_clk_share;
113 bool psp_setup_panel_mode;
114#ifdef CONFIG_DRM_AMD_DC_DCN2_0
115 bool hw_3d_lut;
116#endif
117 struct dc_plane_cap planes[MAX_PLANES];
118};
119
120#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
121struct dc_bug_wa {
122 bool no_connect_phy_config;
123 bool dedcn20_305_wa;
124};
125#endif
126
127struct dc_dcc_surface_param {
128 struct dc_size surface_size;
129 enum surface_pixel_format format;
130 enum swizzle_mode_values swizzle_mode;
131 enum dc_scan_direction scan;
132};
133
134struct dc_dcc_setting {
135 unsigned int max_compressed_blk_size;
136 unsigned int max_uncompressed_blk_size;
137 bool independent_64b_blks;
138};
139
140struct dc_surface_dcc_cap {
141 union {
142 struct {
143 struct dc_dcc_setting rgb;
144 } grph;
145
146 struct {
147 struct dc_dcc_setting luma;
148 struct dc_dcc_setting chroma;
149 } video;
150 };
151
152 bool capable;
153 bool const_color_support;
154};
155
156struct dc_static_screen_events {
157 bool force_trigger;
158 bool cursor_update;
159 bool surface_update;
160 bool overlay_update;
161};
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190enum surface_update_type {
191 UPDATE_TYPE_FAST,
192 UPDATE_TYPE_MED,
193 UPDATE_TYPE_FULL,
194};
195
196
197struct dc;
198struct dc_plane_state;
199struct dc_state;
200
201
202struct dc_cap_funcs {
203 bool (*get_dcc_compression_cap)(const struct dc *dc,
204 const struct dc_dcc_surface_param *input,
205 struct dc_surface_dcc_cap *output);
206};
207
208struct link_training_settings;
209
210
211
212struct dc_config {
213 bool gpu_vm_support;
214 bool disable_disp_pll_sharing;
215 bool fbc_support;
216 bool optimize_edp_link_rate;
217 bool disable_fractional_pwm;
218 bool allow_seamless_boot_optimization;
219 bool power_down_display_on_boot;
220 bool edp_not_connected;
221 bool forced_clocks;
222
223};
224
225enum visual_confirm {
226 VISUAL_CONFIRM_DISABLE = 0,
227 VISUAL_CONFIRM_SURFACE = 1,
228 VISUAL_CONFIRM_HDR = 2,
229};
230
231enum dcc_option {
232 DCC_ENABLE = 0,
233 DCC_DISABLE = 1,
234 DCC_HALF_REQ_DISALBE = 2,
235};
236
237enum pipe_split_policy {
238 MPC_SPLIT_DYNAMIC = 0,
239 MPC_SPLIT_AVOID = 1,
240 MPC_SPLIT_AVOID_MULT_DISP = 2,
241};
242
243enum wm_report_mode {
244 WM_REPORT_DEFAULT = 0,
245 WM_REPORT_OVERRIDE = 1,
246};
247
248
249
250
251
252struct dc_clocks {
253 int dispclk_khz;
254 int max_supported_dppclk_khz;
255 int dppclk_khz;
256 int dcfclk_khz;
257 int socclk_khz;
258 int dcfclk_deep_sleep_khz;
259 int fclk_khz;
260 int phyclk_khz;
261 int dramclk_khz;
262 bool p_state_change_support;
263};
264
265struct dc_bw_validation_profile {
266 bool enable;
267
268 unsigned long long total_ticks;
269 unsigned long long voltage_level_ticks;
270 unsigned long long watermark_ticks;
271 unsigned long long rq_dlg_ticks;
272
273 unsigned long long total_count;
274 unsigned long long skip_fast_count;
275 unsigned long long skip_pass_count;
276 unsigned long long skip_fail_count;
277};
278
279#define BW_VAL_TRACE_SETUP() \
280 unsigned long long end_tick = 0; \
281 unsigned long long voltage_level_tick = 0; \
282 unsigned long long watermark_tick = 0; \
283 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
284 dm_get_timestamp(dc->ctx) : 0
285
286#define BW_VAL_TRACE_COUNT() \
287 if (dc->debug.bw_val_profile.enable) \
288 dc->debug.bw_val_profile.total_count++
289
290#define BW_VAL_TRACE_SKIP(status) \
291 if (dc->debug.bw_val_profile.enable) { \
292 if (!voltage_level_tick) \
293 voltage_level_tick = dm_get_timestamp(dc->ctx); \
294 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
295 }
296
297#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
298 if (dc->debug.bw_val_profile.enable) \
299 voltage_level_tick = dm_get_timestamp(dc->ctx)
300
301#define BW_VAL_TRACE_END_WATERMARKS() \
302 if (dc->debug.bw_val_profile.enable) \
303 watermark_tick = dm_get_timestamp(dc->ctx)
304
305#define BW_VAL_TRACE_FINISH() \
306 if (dc->debug.bw_val_profile.enable) { \
307 end_tick = dm_get_timestamp(dc->ctx); \
308 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
309 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
310 if (watermark_tick) { \
311 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
312 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
313 } \
314 }
315
316struct dc_debug_options {
317 enum visual_confirm visual_confirm;
318 bool sanity_checks;
319 bool max_disp_clk;
320 bool surface_trace;
321 bool timing_trace;
322 bool clock_trace;
323 bool validation_trace;
324 bool bandwidth_calcs_trace;
325 int max_downscale_src_width;
326
327
328 bool disable_stutter;
329 bool use_max_lb;
330 enum dcc_option disable_dcc;
331 enum pipe_split_policy pipe_split_policy;
332 bool force_single_disp_pipe_split;
333 bool voltage_align_fclk;
334
335 bool disable_dfs_bypass;
336 bool disable_dpp_power_gate;
337 bool disable_hubp_power_gate;
338#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
339 bool disable_dsc_power_gate;
340#endif
341 bool disable_pplib_wm_range;
342 enum wm_report_mode pplib_wm_report_mode;
343 unsigned int min_disp_clk_khz;
344 int sr_exit_time_dpm0_ns;
345 int sr_enter_plus_exit_time_dpm0_ns;
346 int sr_exit_time_ns;
347 int sr_enter_plus_exit_time_ns;
348 int urgent_latency_ns;
349 uint32_t underflow_assert_delay_us;
350 int percent_of_ideal_drambw;
351 int dram_clock_change_latency_ns;
352 bool optimized_watermark;
353 int always_scale;
354 bool disable_pplib_clock_request;
355 bool disable_clock_gate;
356 bool disable_dmcu;
357 bool disable_psr;
358 bool force_abm_enable;
359 bool disable_stereo_support;
360 bool vsr_support;
361 bool performance_trace;
362 bool az_endpoint_mute_only;
363 bool always_use_regamma;
364 bool p010_mpo_support;
365 bool recovery_enabled;
366 bool avoid_vbios_exec_table;
367 bool scl_reset_length10;
368 bool hdmi20_disable;
369 bool skip_detection_link_training;
370 unsigned int force_odm_combine;
371 unsigned int force_fclk_khz;
372 bool disable_tri_buf;
373 struct dc_bw_validation_profile bw_val_profile;
374#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
375 bool disable_fec;
376#endif
377
378
379
380 unsigned int force_min_dcfclk_mhz;
381};
382
383struct dc_debug_data {
384 uint32_t ltFailCount;
385 uint32_t i2cErrorCount;
386 uint32_t auxErrorCount;
387};
388
389#ifdef CONFIG_DRM_AMD_DC_DCN2_0
390struct dc_phy_addr_space_config {
391 struct {
392 uint64_t start_addr;
393 uint64_t end_addr;
394 uint64_t fb_top;
395 uint64_t fb_offset;
396 uint64_t fb_base;
397 uint64_t agp_top;
398 uint64_t agp_bot;
399 uint64_t agp_base;
400 } system_aperture;
401
402 struct {
403 uint64_t page_table_start_addr;
404 uint64_t page_table_end_addr;
405 uint64_t page_table_base_addr;
406 } gart_config;
407
408 bool valid;
409};
410
411struct dc_virtual_addr_space_config {
412 uint64_t page_table_base_addr;
413 uint64_t page_table_start_addr;
414 uint64_t page_table_end_addr;
415 uint32_t page_table_block_size_in_bytes;
416 uint8_t page_table_depth;
417};
418#endif
419
420struct dc_bounding_box_overrides {
421 int sr_exit_time_ns;
422 int sr_enter_plus_exit_time_ns;
423 int urgent_latency_ns;
424 int percent_of_ideal_drambw;
425 int dram_clock_change_latency_ns;
426
427
428
429
430 int min_dcfclk_mhz;
431};
432
433struct dc_state;
434struct resource_pool;
435struct dce_hwseq;
436struct gpu_info_soc_bounding_box_v1_0;
437struct dc {
438 struct dc_versions versions;
439 struct dc_caps caps;
440 struct dc_cap_funcs cap_funcs;
441 struct dc_config config;
442 struct dc_debug_options debug;
443 struct dc_bounding_box_overrides bb_overrides;
444#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
445 struct dc_bug_wa work_arounds;
446#endif
447 struct dc_context *ctx;
448#ifdef CONFIG_DRM_AMD_DC_DCN2_0
449 struct dc_phy_addr_space_config vm_pa_config;
450#endif
451
452 uint8_t link_count;
453 struct dc_link *links[MAX_PIPES * 2];
454
455 struct dc_state *current_state;
456 struct resource_pool *res_pool;
457
458 struct clk_mgr *clk_mgr;
459
460
461 struct dm_pp_clock_levels sclk_lvls;
462
463
464 struct bw_calcs_dceip *bw_dceip;
465 struct bw_calcs_vbios *bw_vbios;
466#ifdef CONFIG_DRM_AMD_DC_DCN1_0
467 struct dcn_soc_bounding_box *dcn_soc;
468 struct dcn_ip_params *dcn_ip;
469 struct display_mode_lib dml;
470#endif
471
472
473 struct hw_sequencer_funcs hwss;
474 struct dce_hwseq *hwseq;
475
476
477 bool optimized_required;
478
479
480 bool optimize_seamless_boot;
481
482
483 struct compressor *fbc_compressor;
484
485 struct dc_debug_data debug_data;
486
487 const char *build_id;
488#ifdef CONFIG_DRM_AMD_DC_DCN2_0
489 struct vm_helper *vm_helper;
490 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
491#endif
492};
493
494enum frame_buffer_mode {
495 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
496 FRAME_BUFFER_MODE_ZFB_ONLY,
497 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
498} ;
499
500struct dchub_init_data {
501 int64_t zfb_phys_addr_base;
502 int64_t zfb_mc_base_addr;
503 uint64_t zfb_size_in_byte;
504 enum frame_buffer_mode fb_mode;
505 bool dchub_initialzied;
506 bool dchub_info_valid;
507};
508
509struct dc_init_data {
510 struct hw_asic_id asic_id;
511 void *driver;
512 struct cgs_device *cgs_device;
513 struct dc_bounding_box_overrides bb_overrides;
514
515 int num_virtual_links;
516
517
518
519
520 struct dc_bios *vbios_override;
521 enum dce_environment dce_environment;
522
523 struct dc_config flags;
524 uint32_t log_mask;
525#ifdef CONFIG_DRM_AMD_DC_DCN2_0
526
527
528
529
530 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
531#endif
532};
533
534struct dc_callback_init {
535 uint8_t reserved;
536};
537
538struct dc *dc_create(const struct dc_init_data *init_params);
539int dc_get_vmid_use_vector(struct dc *dc);
540#ifdef CONFIG_DRM_AMD_DC_DCN2_0
541void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
542
543int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
544#endif
545void dc_init_callbacks(struct dc *dc,
546 const struct dc_callback_init *init_params);
547void dc_destroy(struct dc **dc);
548
549
550
551
552
553enum {
554 TRANSFER_FUNC_POINTS = 1025
555};
556
557struct dc_hdr_static_metadata {
558
559 unsigned int chromaticity_green_x;
560 unsigned int chromaticity_green_y;
561 unsigned int chromaticity_blue_x;
562 unsigned int chromaticity_blue_y;
563 unsigned int chromaticity_red_x;
564 unsigned int chromaticity_red_y;
565 unsigned int chromaticity_white_point_x;
566 unsigned int chromaticity_white_point_y;
567
568 uint32_t min_luminance;
569 uint32_t max_luminance;
570 uint32_t maximum_content_light_level;
571 uint32_t maximum_frame_average_light_level;
572};
573
574enum dc_transfer_func_type {
575 TF_TYPE_PREDEFINED,
576 TF_TYPE_DISTRIBUTED_POINTS,
577 TF_TYPE_BYPASS,
578 TF_TYPE_HWPWL
579};
580
581struct dc_transfer_func_distributed_points {
582 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
583 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
584 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
585
586 uint16_t end_exponent;
587 uint16_t x_point_at_y1_red;
588 uint16_t x_point_at_y1_green;
589 uint16_t x_point_at_y1_blue;
590};
591
592enum dc_transfer_func_predefined {
593 TRANSFER_FUNCTION_SRGB,
594 TRANSFER_FUNCTION_BT709,
595 TRANSFER_FUNCTION_PQ,
596 TRANSFER_FUNCTION_LINEAR,
597 TRANSFER_FUNCTION_UNITY,
598 TRANSFER_FUNCTION_HLG,
599 TRANSFER_FUNCTION_HLG12,
600 TRANSFER_FUNCTION_GAMMA22
601};
602
603struct dc_transfer_func {
604 struct kref refcount;
605 enum dc_transfer_func_type type;
606 enum dc_transfer_func_predefined tf;
607
608 uint32_t sdr_ref_white_level;
609 struct dc_context *ctx;
610 union {
611 struct pwl_params pwl;
612 struct dc_transfer_func_distributed_points tf_pts;
613 };
614};
615
616#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
617
618
619struct dc_3dlut {
620 struct kref refcount;
621 struct tetrahedral_params lut_3d;
622 uint32_t hdr_multiplier;
623 bool initialized;
624 struct dc_context *ctx;
625};
626#endif
627
628
629
630
631
632struct dc_plane_status {
633 struct dc_plane_address requested_address;
634 struct dc_plane_address current_address;
635 bool is_flip_pending;
636 bool is_right_eye;
637};
638
639union surface_update_flags {
640
641 struct {
642 uint32_t addr_update:1;
643
644 uint32_t dcc_change:1;
645 uint32_t color_space_change:1;
646 uint32_t horizontal_mirror_change:1;
647 uint32_t per_pixel_alpha_change:1;
648 uint32_t global_alpha_change:1;
649 uint32_t sdr_white_level:1;
650 uint32_t rotation_change:1;
651 uint32_t swizzle_change:1;
652 uint32_t scaling_change:1;
653 uint32_t position_change:1;
654 uint32_t in_transfer_func_change:1;
655 uint32_t input_csc_change:1;
656 uint32_t coeff_reduction_change:1;
657 uint32_t output_tf_change:1;
658 uint32_t pixel_format_change:1;
659 uint32_t plane_size_change:1;
660
661
662 uint32_t new_plane:1;
663 uint32_t bpp_change:1;
664 uint32_t gamma_change:1;
665 uint32_t bandwidth_change:1;
666 uint32_t clock_change:1;
667 uint32_t stereo_format_change:1;
668 uint32_t full_update:1;
669 } bits;
670
671 uint32_t raw;
672};
673
674struct dc_plane_state {
675 struct dc_plane_address address;
676 struct dc_plane_flip_time time;
677#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
678 bool triplebuffer_flips;
679#endif
680 struct scaling_taps scaling_quality;
681 struct rect src_rect;
682 struct rect dst_rect;
683 struct rect clip_rect;
684
685 union plane_size plane_size;
686 union dc_tiling_info tiling_info;
687
688 struct dc_plane_dcc_param dcc;
689
690 struct dc_gamma *gamma_correction;
691 struct dc_transfer_func *in_transfer_func;
692 struct dc_bias_and_scale *bias_and_scale;
693 struct dc_csc_transform input_csc_color_matrix;
694 struct fixed31_32 coeff_reduction_factor;
695 uint32_t sdr_white_level;
696
697
698 struct dc_hdr_static_metadata hdr_static_ctx;
699
700 enum dc_color_space color_space;
701
702#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
703 struct dc_3dlut *lut3d_func;
704 struct dc_transfer_func *in_shaper_func;
705 struct dc_transfer_func *blend_tf;
706#endif
707
708 enum surface_pixel_format format;
709 enum dc_rotation_angle rotation;
710 enum plane_stereo_format stereo_format;
711
712 bool is_tiling_rotated;
713 bool per_pixel_alpha;
714 bool global_alpha;
715 int global_alpha_value;
716 bool visible;
717 bool flip_immediate;
718 bool horizontal_mirror;
719
720 union surface_update_flags update_flags;
721
722 struct dc_plane_status status;
723 struct dc_context *ctx;
724
725
726 bool force_full_update;
727
728
729 enum dc_irq_source irq_source;
730 struct kref refcount;
731};
732
733struct dc_plane_info {
734 union plane_size plane_size;
735 union dc_tiling_info tiling_info;
736 struct dc_plane_dcc_param dcc;
737 enum surface_pixel_format format;
738 enum dc_rotation_angle rotation;
739 enum plane_stereo_format stereo_format;
740 enum dc_color_space color_space;
741 unsigned int sdr_white_level;
742 bool horizontal_mirror;
743 bool visible;
744 bool per_pixel_alpha;
745 bool global_alpha;
746 int global_alpha_value;
747 bool input_csc_enabled;
748};
749
750struct dc_scaling_info {
751 struct rect src_rect;
752 struct rect dst_rect;
753 struct rect clip_rect;
754 struct scaling_taps scaling_quality;
755};
756
757struct dc_surface_update {
758 struct dc_plane_state *surface;
759
760
761 const struct dc_flip_addrs *flip_addr;
762 const struct dc_plane_info *plane_info;
763 const struct dc_scaling_info *scaling_info;
764
765
766
767
768 const struct dc_gamma *gamma;
769 const struct dc_transfer_func *in_transfer_func;
770
771 const struct dc_csc_transform *input_csc_color_matrix;
772 const struct fixed31_32 *coeff_reduction_factor;
773#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
774 const struct dc_transfer_func *func_shaper;
775 const struct dc_3dlut *lut3d_func;
776 const struct dc_transfer_func *blend_tf;
777#endif
778};
779
780
781
782
783struct dc_plane_state *dc_create_plane_state(struct dc *dc);
784const struct dc_plane_status *dc_plane_get_status(
785 const struct dc_plane_state *plane_state);
786
787void dc_plane_state_retain(struct dc_plane_state *plane_state);
788void dc_plane_state_release(struct dc_plane_state *plane_state);
789
790void dc_gamma_retain(struct dc_gamma *dc_gamma);
791void dc_gamma_release(struct dc_gamma **dc_gamma);
792struct dc_gamma *dc_create_gamma(void);
793
794void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
795void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
796struct dc_transfer_func *dc_create_transfer_func(void);
797
798#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
799struct dc_3dlut *dc_create_3dlut_func(void);
800void dc_3dlut_func_release(struct dc_3dlut *lut);
801void dc_3dlut_func_retain(struct dc_3dlut *lut);
802#endif
803
804
805
806
807
808struct dc_flip_addrs {
809 struct dc_plane_address address;
810 unsigned int flip_timestamp_in_us;
811 bool flip_immediate;
812
813};
814
815bool dc_post_update_surfaces_to_stream(
816 struct dc *dc);
817
818#include "dc_stream.h"
819
820
821
822
823struct dc_validation_set {
824 struct dc_stream_state *stream;
825 struct dc_plane_state *plane_states[MAX_SURFACES];
826 uint8_t plane_count;
827};
828
829bool dc_validate_seamless_boot_timing(const struct dc *dc,
830 const struct dc_sink *sink,
831 struct dc_crtc_timing *crtc_timing);
832
833enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
834
835void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
836
837
838
839
840
841enum dc_status dc_validate_global_state(
842 struct dc *dc,
843 struct dc_state *new_ctx,
844 bool fast_validate);
845
846
847void dc_resource_state_construct(
848 const struct dc *dc,
849 struct dc_state *dst_ctx);
850
851void dc_resource_state_copy_construct(
852 const struct dc_state *src_ctx,
853 struct dc_state *dst_ctx);
854
855void dc_resource_state_copy_construct_current(
856 const struct dc *dc,
857 struct dc_state *dst_ctx);
858
859void dc_resource_state_destruct(struct dc_state *context);
860
861
862
863
864
865
866
867
868
869
870bool dc_commit_state(struct dc *dc, struct dc_state *context);
871
872
873struct dc_state *dc_create_state(struct dc *dc);
874struct dc_state *dc_copy_state(struct dc_state *src_ctx);
875void dc_retain_state(struct dc_state *context);
876void dc_release_state(struct dc_state *context);
877
878
879
880
881
882struct dpcd_caps {
883 union dpcd_rev dpcd_rev;
884 union max_lane_count max_ln_count;
885 union max_down_spread max_down_spread;
886 union dprx_feature dprx_feature;
887
888
889 uint8_t edp_supported_link_rates_count;
890 enum dc_link_rate edp_supported_link_rates[8];
891
892
893 enum display_dongle_type dongle_type;
894
895 bool is_branch_dev;
896
897 union sink_count sink_count;
898
899
900 struct dc_dongle_caps dongle_caps;
901
902 uint32_t sink_dev_id;
903 int8_t sink_dev_id_str[6];
904 int8_t sink_hw_revision;
905 int8_t sink_fw_revision[2];
906
907 uint32_t branch_dev_id;
908 int8_t branch_dev_name[6];
909 int8_t branch_hw_revision;
910 int8_t branch_fw_revision[2];
911
912 bool allow_invalid_MSA_timing_param;
913 bool panel_mode_edp;
914 bool dpcd_display_control_capable;
915 bool ext_receiver_cap_field_present;
916#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
917 union dpcd_fec_capability fec_cap;
918 struct dpcd_dsc_capabilities dsc_caps;
919#endif
920};
921
922#include "dc_link.h"
923
924
925
926
927
928struct dc_container_id {
929
930 unsigned char guid[16];
931
932 unsigned int portId[2];
933
934 unsigned short manufacturerName;
935
936 unsigned short productCode;
937};
938
939
940#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
941struct dc_sink_dsc_caps {
942
943
944 bool is_virtual_dpcd_dsc;
945 struct dsc_dec_dpcd_caps dsc_dec_caps;
946};
947#endif
948
949
950
951
952struct dc_sink {
953 enum signal_type sink_signal;
954 struct dc_edid dc_edid;
955 struct dc_edid_caps edid_caps;
956 struct dc_container_id *dc_container_id;
957 uint32_t dongle_max_pix_clk;
958 void *priv;
959 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
960 bool converter_disable_audio;
961
962#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
963 struct dc_sink_dsc_caps sink_dsc_caps;
964#endif
965
966
967 struct dc_link *link;
968 struct dc_context *ctx;
969
970 uint32_t sink_id;
971
972
973
974
975
976 struct kref refcount;
977};
978
979void dc_sink_retain(struct dc_sink *sink);
980void dc_sink_release(struct dc_sink *sink);
981
982struct dc_sink_init_data {
983 enum signal_type sink_signal;
984 struct dc_link *link;
985 uint32_t dongle_max_pix_clk;
986 bool converter_disable_audio;
987};
988
989struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
990
991
992struct dc_cursor {
993 struct dc_plane_address address;
994 struct dc_cursor_attributes attributes;
995};
996
997
998
999
1000
1001enum dc_irq_source dc_interrupt_to_irq_source(
1002 struct dc *dc,
1003 uint32_t src_id,
1004 uint32_t ext_id);
1005bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1006void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1007enum dc_irq_source dc_get_hpd_irq_source_at_index(
1008 struct dc *dc, uint32_t link_index);
1009
1010
1011
1012
1013
1014void dc_set_power_state(
1015 struct dc *dc,
1016 enum dc_acpi_cm_power_state power_state);
1017void dc_resume(struct dc *dc);
1018unsigned int dc_get_current_backlight_pwm(struct dc *dc);
1019unsigned int dc_get_target_backlight_pwm(struct dc *dc);
1020
1021bool dc_is_dmcu_initialized(struct dc *dc);
1022
1023#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
1024
1025
1026
1027#include "dc_dsc.h"
1028#endif
1029#endif
1030