LXR linux/drivers/gpu/drm/amd/display/dc/dc_dp

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef DC_DP_TYPES_H
  27#define DC_DP_TYPES_H
  28
  29#include "os_types.h"
  30
  31enum dc_lane_count {
  32        LANE_COUNT_UNKNOWN = 0,
  33        LANE_COUNT_ONE = 1,
  34        LANE_COUNT_TWO = 2,
  35        LANE_COUNT_FOUR = 4,
  36        LANE_COUNT_EIGHT = 8,
  37        LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
  38};
  39
  40/* This is actually a reference clock (27MHz) multiplier
  41 * 162MBps bandwidth for 1.62GHz like rate,
  42 * 270MBps for 2.70GHz,
  43 * 324MBps for 3.24Ghz,
  44 * 540MBps for 5.40GHz
  45 * 810MBps for 8.10GHz
  46 */
  47enum dc_link_rate {
  48        LINK_RATE_UNKNOWN = 0,
  49        LINK_RATE_LOW = 0x06,           // Rate_1 (RBR) - 1.62 Gbps/Lane
  50        LINK_RATE_RATE_2 = 0x08,        // Rate_2               - 2.16 Gbps/Lane
  51        LINK_RATE_RATE_3 = 0x09,        // Rate_3               - 2.43 Gbps/Lane
  52        LINK_RATE_HIGH = 0x0A,          // Rate_4 (HBR) - 2.70 Gbps/Lane
  53        LINK_RATE_RBR2 = 0x0C,          // Rate_5 (RBR2)- 3.24 Gbps/Lane
  54        LINK_RATE_RATE_6 = 0x10,        // Rate_6               - 4.32 Gbps/Lane
  55        LINK_RATE_HIGH2 = 0x14,         // Rate_7 (HBR2)- 5.40 Gbps/Lane
  56        LINK_RATE_HIGH3 = 0x1E          // Rate_8 (HBR3)- 8.10 Gbps/Lane
  57};
  58
  59enum dc_link_spread {
  60        LINK_SPREAD_DISABLED = 0x00,
  61        /* 0.5 % downspread 30 kHz */
  62        LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
  63        /* 0.5 % downspread 33 kHz */
  64        LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
  65};
  66
  67enum dc_voltage_swing {
  68        VOLTAGE_SWING_LEVEL0 = 0,       /* direct HW translation! */
  69        VOLTAGE_SWING_LEVEL1,
  70        VOLTAGE_SWING_LEVEL2,
  71        VOLTAGE_SWING_LEVEL3,
  72        VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
  73};
  74
  75enum dc_pre_emphasis {
  76        PRE_EMPHASIS_DISABLED = 0,      /* direct HW translation! */
  77        PRE_EMPHASIS_LEVEL1,
  78        PRE_EMPHASIS_LEVEL2,
  79        PRE_EMPHASIS_LEVEL3,
  80        PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
  81};
  82/* Post Cursor 2 is optional for transmitter
  83 * and it applies only to the main link operating at HBR2
  84 */
  85enum dc_post_cursor2 {
  86        POST_CURSOR2_DISABLED = 0,      /* direct HW translation! */
  87        POST_CURSOR2_LEVEL1,
  88        POST_CURSOR2_LEVEL2,
  89        POST_CURSOR2_LEVEL3,
  90        POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
  91};
  92
  93struct dc_link_settings {
  94        enum dc_lane_count lane_count;
  95        enum dc_link_rate link_rate;
  96        enum dc_link_spread link_spread;
  97        bool use_link_rate_set;
  98        uint8_t link_rate_set;
  99};
 100
 101struct dc_lane_settings {
 102        enum dc_voltage_swing VOLTAGE_SWING;
 103        enum dc_pre_emphasis PRE_EMPHASIS;
 104        enum dc_post_cursor2 POST_CURSOR2;
 105};
 106
 107struct dc_link_training_settings {
 108        struct dc_link_settings link;
 109        struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 110};
 111
 112
 113union dpcd_rev {
 114        struct {
 115                uint8_t MINOR:4;
 116                uint8_t MAJOR:4;
 117        } bits;
 118        uint8_t raw;
 119};
 120
 121union max_lane_count {
 122        struct {
 123                uint8_t MAX_LANE_COUNT:5;
 124                uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
 125                uint8_t TPS3_SUPPORTED:1;
 126                uint8_t ENHANCED_FRAME_CAP:1;
 127        } bits;
 128        uint8_t raw;
 129};
 130
 131union max_down_spread {
 132        struct {
 133                uint8_t MAX_DOWN_SPREAD:1;
 134                uint8_t RESERVED:5;
 135                uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
 136                uint8_t TPS4_SUPPORTED:1;
 137        } bits;
 138        uint8_t raw;
 139};
 140
 141union mstm_cap {
 142        struct {
 143                uint8_t MST_CAP:1;
 144                uint8_t RESERVED:7;
 145        } bits;
 146        uint8_t raw;
 147};
 148
 149union lane_count_set {
 150        struct {
 151                uint8_t LANE_COUNT_SET:5;
 152                uint8_t POST_LT_ADJ_REQ_GRANTED:1;
 153                uint8_t RESERVED:1;
 154                uint8_t ENHANCED_FRAMING:1;
 155        } bits;
 156        uint8_t raw;
 157};
 158
 159union lane_status {
 160        struct {
 161                uint8_t CR_DONE_0:1;
 162                uint8_t CHANNEL_EQ_DONE_0:1;
 163                uint8_t SYMBOL_LOCKED_0:1;
 164                uint8_t RESERVED0:1;
 165                uint8_t CR_DONE_1:1;
 166                uint8_t CHANNEL_EQ_DONE_1:1;
 167                uint8_t SYMBOL_LOCKED_1:1;
 168                uint8_t RESERVED_1:1;
 169        } bits;
 170        uint8_t raw;
 171};
 172
 173union device_service_irq {
 174        struct {
 175                uint8_t REMOTE_CONTROL_CMD_PENDING:1;
 176                uint8_t AUTOMATED_TEST:1;
 177                uint8_t CP_IRQ:1;
 178                uint8_t MCCS_IRQ:1;
 179                uint8_t DOWN_REP_MSG_RDY:1;
 180                uint8_t UP_REQ_MSG_RDY:1;
 181                uint8_t SINK_SPECIFIC:1;
 182                uint8_t reserved:1;
 183        } bits;
 184        uint8_t raw;
 185};
 186
 187union sink_count {
 188        struct {
 189                uint8_t SINK_COUNT:6;
 190                uint8_t CPREADY:1;
 191                uint8_t RESERVED:1;
 192        } bits;
 193        uint8_t raw;
 194};
 195
 196union lane_align_status_updated {
 197        struct {
 198                uint8_t INTERLANE_ALIGN_DONE:1;
 199                uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
 200                uint8_t RESERVED:4;
 201                uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
 202                uint8_t LINK_STATUS_UPDATED:1;
 203        } bits;
 204        uint8_t raw;
 205};
 206
 207union lane_adjust {
 208        struct {
 209                uint8_t VOLTAGE_SWING_LANE:2;
 210                uint8_t PRE_EMPHASIS_LANE:2;
 211                uint8_t RESERVED:4;
 212        } bits;
 213        uint8_t raw;
 214};
 215
 216union dpcd_training_pattern {
 217        struct {
 218                uint8_t TRAINING_PATTERN_SET:4;
 219                uint8_t RECOVERED_CLOCK_OUT_EN:1;
 220                uint8_t SCRAMBLING_DISABLE:1;
 221                uint8_t SYMBOL_ERROR_COUNT_SEL:2;
 222        } v1_4;
 223        struct {
 224                uint8_t TRAINING_PATTERN_SET:2;
 225                uint8_t LINK_QUAL_PATTERN_SET:2;
 226                uint8_t RESERVED:4;
 227        } v1_3;
 228        uint8_t raw;
 229};
 230
 231/* Training Lane is used to configure downstream DP device's voltage swing
 232and pre-emphasis levels*/
 233/* The DPCD addresses are from 0x103 to 0x106*/
 234union dpcd_training_lane {
 235        struct {
 236                uint8_t VOLTAGE_SWING_SET:2;
 237                uint8_t MAX_SWING_REACHED:1;
 238                uint8_t PRE_EMPHASIS_SET:2;
 239                uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 240                uint8_t RESERVED:2;
 241        } bits;
 242        uint8_t raw;
 243};
 244
 245/* TMDS-converter related */
 246union dwnstream_port_caps_byte0 {
 247        struct {
 248                uint8_t DWN_STRM_PORTX_TYPE:3;
 249                uint8_t DWN_STRM_PORTX_HPD:1;
 250                uint8_t RESERVERD:4;
 251        } bits;
 252        uint8_t raw;
 253};
 254
 255/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
 256enum dpcd_downstream_port_detailed_type {
 257        DOWN_STREAM_DETAILED_DP = 0,
 258        DOWN_STREAM_DETAILED_VGA,
 259        DOWN_STREAM_DETAILED_DVI,
 260        DOWN_STREAM_DETAILED_HDMI,
 261        DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
 262        DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 263};
 264
 265union dwnstream_port_caps_byte2 {
 266        struct {
 267                uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 268                uint8_t RESERVED:6;
 269        } bits;
 270        uint8_t raw;
 271};
 272
 273union dp_downstream_port_present {
 274        uint8_t byte;
 275        struct {
 276                uint8_t PORT_PRESENT:1;
 277                uint8_t PORT_TYPE:2;
 278                uint8_t FMT_CONVERSION:1;
 279                uint8_t DETAILED_CAPS:1;
 280                uint8_t RESERVED:3;
 281        } fields;
 282};
 283
 284union dwnstream_port_caps_byte3_dvi {
 285        struct {
 286                uint8_t RESERVED1:1;
 287                uint8_t DUAL_LINK:1;
 288                uint8_t HIGH_COLOR_DEPTH:1;
 289                uint8_t RESERVED2:5;
 290        } bits;
 291        uint8_t raw;
 292};
 293
 294union dwnstream_port_caps_byte3_hdmi {
 295        struct {
 296                uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
 297                uint8_t YCrCr422_PASS_THROUGH:1;
 298                uint8_t YCrCr420_PASS_THROUGH:1;
 299                uint8_t YCrCr422_CONVERSION:1;
 300                uint8_t YCrCr420_CONVERSION:1;
 301                uint8_t RESERVED:3;
 302        } bits;
 303        uint8_t raw;
 304};
 305
 306/*4-byte structure for detailed capabilities of a down-stream port
 307(DP-to-TMDS converter).*/
 308union dwnstream_portxcaps {
 309        struct {
 310                union dwnstream_port_caps_byte0 byte0;
 311                unsigned char max_TMDS_clock;   //byte1
 312                union dwnstream_port_caps_byte2 byte2;
 313
 314                union {
 315                        union dwnstream_port_caps_byte3_dvi byteDVI;
 316                        union dwnstream_port_caps_byte3_hdmi byteHDMI;
 317                } byte3;
 318        } bytes;
 319
 320        unsigned char raw[4];
 321};
 322
 323union downstream_port {
 324        struct {
 325                unsigned char   present:1;
 326                unsigned char   type:2;
 327                unsigned char   format_conv:1;
 328                unsigned char   detailed_caps:1;
 329                unsigned char   reserved:3;
 330        } bits;
 331        unsigned char raw;
 332};
 333
 334
 335union sink_status {
 336        struct {
 337                uint8_t RX_PORT0_STATUS:1;
 338                uint8_t RX_PORT1_STATUS:1;
 339                uint8_t RESERVED:6;
 340        } bits;
 341        uint8_t raw;
 342};
 343
 344/*6-byte structure corresponding to 6 registers (200h-205h)
 345read during handling of HPD-IRQ*/
 346union hpd_irq_data {
 347        struct {
 348                union sink_count sink_cnt;/* 200h */
 349                union device_service_irq device_service_irq;/* 201h */
 350                union lane_status lane01_status;/* 202h */
 351                union lane_status lane23_status;/* 203h */
 352                union lane_align_status_updated lane_status_updated;/* 204h */
 353                union sink_status sink_status;
 354        } bytes;
 355        uint8_t raw[6];
 356};
 357
 358union down_stream_port_count {
 359        struct {
 360                uint8_t DOWN_STR_PORT_COUNT:4;
 361                uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
 362                /*Bit 6 = MSA_TIMING_PAR_IGNORED
 363                0 = Sink device requires the MSA timing parameters
 364                1 = Sink device is capable of rendering incoming video
 365                 stream without MSA timing parameters*/
 366                uint8_t IGNORE_MSA_TIMING_PARAM:1;
 367                /*Bit 7 = OUI Support
 368                0 = OUI not supported
 369                1 = OUI supported
 370                (OUI and Device Identification mandatory for DP 1.2)*/
 371                uint8_t OUI_SUPPORT:1;
 372        } bits;
 373        uint8_t raw;
 374};
 375
 376union down_spread_ctrl {
 377        struct {
 378                uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
 379        /* Bits 4 = SPREAD_AMP. Spreading amplitude
 380        0 = Main link signal is not downspread
 381        1 = Main link signal is downspread <= 0.5%
 382        with frequency in the range of 30kHz ~ 33kHz*/
 383                uint8_t SPREAD_AMP:1;
 384                uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
 385        /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
 386        0 = Source device will send valid data for the MSA Timing Params
 387        1 = Source device may send invalid data for these MSA Timing Params*/
 388                uint8_t IGNORE_MSA_TIMING_PARAM:1;
 389        } bits;
 390        uint8_t raw;
 391};
 392
 393union dpcd_edp_config {
 394        struct {
 395                uint8_t PANEL_MODE_EDP:1;
 396                uint8_t FRAMING_CHANGE_ENABLE:1;
 397                uint8_t RESERVED:5;
 398                uint8_t PANEL_SELF_TEST_ENABLE:1;
 399        } bits;
 400        uint8_t raw;
 401};
 402
 403struct dp_device_vendor_id {
 404        uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 405        uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 406};
 407
 408struct dp_sink_hw_fw_revision {
 409        uint8_t ieee_hw_rev;
 410        uint8_t ieee_fw_rev[2];
 411};
 412
 413/*DPCD register of DP receiver capability field bits-*/
 414union edp_configuration_cap {
 415        struct {
 416                uint8_t ALT_SCRAMBLER_RESET:1;
 417                uint8_t FRAMING_CHANGE:1;
 418                uint8_t RESERVED:1;
 419                uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
 420                uint8_t RESERVED2:4;
 421        } bits;
 422        uint8_t raw;
 423};
 424
 425union dprx_feature {
 426        struct {
 427                uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
 428                uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
 429                uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
 430                uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
 431                uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
 432                uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
 433                uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
 434                uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
 435        } bits;
 436        uint8_t raw;
 437};
 438
 439union training_aux_rd_interval {
 440        struct {
 441                uint8_t TRAINIG_AUX_RD_INTERVAL:7;
 442                uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
 443        } bits;
 444        uint8_t raw;
 445};
 446
 447/* Automated test structures */
 448union test_request {
 449        struct {
 450        uint8_t LINK_TRAINING         :1;
 451        uint8_t LINK_TEST_PATTRN      :1;
 452        uint8_t EDID_READ             :1;
 453        uint8_t PHY_TEST_PATTERN      :1;
 454        uint8_t AUDIO_TEST_PATTERN    :1;
 455        uint8_t RESERVED              :1;
 456        uint8_t TEST_STEREO_3D        :1;
 457        } bits;
 458        uint8_t raw;
 459};
 460
 461union test_response {
 462        struct {
 463                uint8_t ACK         :1;
 464                uint8_t NO_ACK      :1;
 465                uint8_t EDID_CHECKSUM_WRITE:1;
 466                uint8_t RESERVED    :5;
 467        } bits;
 468        uint8_t raw;
 469};
 470
 471union phy_test_pattern {
 472        struct {
 473                /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
 474                 * and 3 bits for DP1.2.
 475                 */
 476                uint8_t PATTERN     :3;
 477                /* BY speci, bit7:2 is 0 for DP1.1. */
 478                uint8_t RESERVED    :5;
 479        } bits;
 480        uint8_t raw;
 481};
 482
 483/* States of Compliance Test Specification (CTS DP1.2). */
 484union compliance_test_state {
 485        struct {
 486                unsigned char STEREO_3D_RUNNING        : 1;
 487                unsigned char RESERVED                 : 7;
 488        } bits;
 489        unsigned char raw;
 490};
 491
 492union link_test_pattern {
 493        struct {
 494                /* dpcd_link_test_patterns */
 495                unsigned char PATTERN :2;
 496                unsigned char RESERVED:6;
 497        } bits;
 498        unsigned char raw;
 499};
 500
 501union test_misc {
 502        struct dpcd_test_misc_bits {
 503                unsigned char SYNC_CLOCK :1;
 504                /* dpcd_test_color_format */
 505                unsigned char CLR_FORMAT :2;
 506                /* dpcd_test_dyn_range */
 507                unsigned char DYN_RANGE  :1;
 508                unsigned char YCBCR      :1;
 509                /* dpcd_test_bit_depth */
 510                unsigned char BPC        :3;
 511        } bits;
 512        unsigned char raw;
 513};
 514
 515#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 516/* FEC capability DPCD register field bits-*/
 517union dpcd_fec_capability {
 518        struct {
 519                uint8_t FEC_CAPABLE:1;
 520                uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 521                uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 522                uint8_t BIT_ERROR_COUNT_CAPABLE:1;
 523                uint8_t RESERVED:4;
 524        } bits;
 525        uint8_t raw;
 526};
 527
 528/* DSC capability DPCD register field bits-*/
 529struct dpcd_dsc_support {
 530        uint8_t DSC_SUPPORT             :1;
 531        uint8_t DSC_PASSTHROUGH_SUPPORT :1;
 532        uint8_t RESERVED                :6;
 533};
 534
 535struct dpcd_dsc_algorithm_revision {
 536        uint8_t DSC_VERSION_MAJOR       :4;
 537        uint8_t DSC_VERSION_MINOR       :4;
 538};
 539
 540struct dpcd_dsc_rc_buffer_block_size {
 541        uint8_t RC_BLOCK_BUFFER_SIZE    :2;
 542        uint8_t RESERVED                :6;
 543};
 544
 545struct dpcd_dsc_slice_capability1 {
 546        uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE        :1;
 547        uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 548        uint8_t RESERVED                                :1;
 549        uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE      :1;
 550        uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 551        uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE     :1;
 552        uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 553        uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE    :1;
 554};
 555
 556struct dpcd_dsc_line_buffer_bit_depth {
 557        uint8_t LINE_BUFFER_BIT_DEPTH   :4;
 558        uint8_t RESERVED                :4;
 559};
 560
 561struct dpcd_dsc_block_prediction_support {
 562        uint8_t BLOCK_PREDICTION_SUPPORT:1;
 563        uint8_t RESERVED                :7;
 564};
 565
 566struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
 567        uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW        :7;
 568        uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH       :7;
 569        uint8_t RESERVED                                                        :2;
 570};
 571
 572struct dpcd_dsc_decoder_color_format_capabilities {
 573        uint8_t RGB_SUPPORT                     :1;
 574        uint8_t Y_CB_CR_444_SUPPORT             :1;
 575        uint8_t Y_CB_CR_SIMPLE_422_SUPPORT      :1;
 576        uint8_t Y_CB_CR_NATIVE_422_SUPPORT      :1;
 577        uint8_t Y_CB_CR_NATIVE_420_SUPPORT      :1;
 578        uint8_t RESERVED                        :3;
 579};
 580
 581struct dpcd_dsc_decoder_color_depth_capabilities {
 582        uint8_t RESERVED0                       :1;
 583        uint8_t EIGHT_BITS_PER_COLOR_SUPPORT    :1;
 584        uint8_t TEN_BITS_PER_COLOR_SUPPORT      :1;
 585        uint8_t TWELVE_BITS_PER_COLOR_SUPPORT   :1;
 586        uint8_t RESERVED1                       :4;
 587};
 588
 589struct dpcd_peak_dsc_throughput_dsc_sink {
 590        uint8_t THROUGHPUT_MODE_0:4;
 591        uint8_t THROUGHPUT_MODE_1:4;
 592};
 593
 594struct dpcd_dsc_slice_capabilities_2 {
 595        uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE      :1;
 596        uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE       :1;
 597        uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE   :1;
 598        uint8_t RESERVED                                :5;
 599};
 600
 601struct dpcd_bits_per_pixel_increment{
 602        uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED   :3;
 603        uint8_t RESERVED                                :5;
 604};
 605union dpcd_dsc_basic_capabilities {
 606        struct {
 607                struct dpcd_dsc_support dsc_support;
 608                struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
 609                struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
 610                uint8_t dsc_rc_buffer_size;
 611                struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
 612                struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
 613                struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
 614                struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
 615                struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
 616                struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
 617                struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
 618                uint8_t dsc_maximum_slice_width;
 619                struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
 620                uint8_t reserved;
 621                struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
 622        } fields;
 623        uint8_t raw[16];
 624};
 625
 626union dpcd_dsc_ext_capabilities {
 627        struct {
 628                uint8_t BRANCH_OVERALL_THROUGHPUT_0;
 629                uint8_t BRANCH_OVERALL_THROUGHPUT_1;
 630                uint8_t BRANCH_MAX_LINE_WIDTH;
 631        } fields;
 632        uint8_t raw[3];
 633};
 634
 635struct dpcd_dsc_capabilities {
 636        union dpcd_dsc_basic_capabilities dsc_basic_caps;
 637        union dpcd_dsc_ext_capabilities dsc_ext_caps;
 638};
 639
 640#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
 641
 642#endif /* DC_DP_TYPES_H */
 643