LXR linux/drivers/gpu/drm/amd/display/dc/dc

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25#ifndef DC_TYPES_H_
  26#define DC_TYPES_H_
  27
  28#include "os_types.h"
  29#include "fixed31_32.h"
  30#include "irq_types.h"
  31#include "dc_dp_types.h"
  32#include "dc_hw_types.h"
  33#include "dal_types.h"
  34#include "grph_object_defs.h"
  35
  36/* forward declarations */
  37struct dc_plane_state;
  38struct dc_stream_state;
  39struct dc_link;
  40struct dc_sink;
  41struct dal;
  42
  43/********************************
  44 * Environment definitions
  45 ********************************/
  46enum dce_environment {
  47        DCE_ENV_PRODUCTION_DRV = 0,
  48        /* Emulation on FPGA, in "Maximus" System.
  49         * This environment enforces that *only* DC registers accessed.
  50         * (access to non-DC registers will hang FPGA) */
  51        DCE_ENV_FPGA_MAXIMUS,
  52        /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
  53         * requirements of Diagnostics team. */
  54        DCE_ENV_DIAG
  55};
  56
  57/* Note: use these macro definitions instead of direct comparison! */
  58#define IS_FPGA_MAXIMUS_DC(dce_environment) \
  59        (dce_environment == DCE_ENV_FPGA_MAXIMUS)
  60
  61#define IS_DIAG_DC(dce_environment) \
  62        (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
  63
  64struct hw_asic_id {
  65        uint32_t chip_id;
  66        uint32_t chip_family;
  67        uint32_t pci_revision_id;
  68        uint32_t hw_internal_rev;
  69        uint32_t vram_type;
  70        uint32_t vram_width;
  71        uint32_t feature_flags;
  72        uint32_t fake_paths_num;
  73        void *atombios_base_address;
  74};
  75
  76struct dc_perf_trace {
  77        unsigned long read_count;
  78        unsigned long write_count;
  79        unsigned long last_entry_read;
  80        unsigned long last_entry_write;
  81};
  82
  83struct dc_context {
  84        struct dc *dc;
  85
  86        void *driver_context; /* e.g. amdgpu_device */
  87        struct dc_perf_trace *perf_trace;
  88        void *cgs_device;
  89
  90        enum dce_environment dce_environment;
  91        struct hw_asic_id asic_id;
  92
  93        /* todo: below should probably move to dc.  to facilitate removal
  94         * of AS we will store these here
  95         */
  96        enum dce_version dce_version;
  97        struct dc_bios *dc_bios;
  98        bool created_bios;
  99        struct gpio_service *gpio_service;
 100        uint32_t dc_sink_id_count;
 101        uint32_t dc_stream_id_count;
 102        uint64_t fbc_gpu_addr;
 103};
 104
 105
 106#define DC_MAX_EDID_BUFFER_SIZE 1024
 107#define DC_EDID_BLOCK_SIZE 128
 108#define MAX_SURFACE_NUM 4
 109#define NUM_PIXEL_FORMATS 10
 110
 111#include "dc_ddc_types.h"
 112
 113enum tiling_mode {
 114        TILING_MODE_INVALID,
 115        TILING_MODE_LINEAR,
 116        TILING_MODE_TILED,
 117        TILING_MODE_COUNT
 118};
 119
 120enum view_3d_format {
 121        VIEW_3D_FORMAT_NONE = 0,
 122        VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
 123        VIEW_3D_FORMAT_SIDE_BY_SIDE,
 124        VIEW_3D_FORMAT_TOP_AND_BOTTOM,
 125        VIEW_3D_FORMAT_COUNT,
 126        VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
 127};
 128
 129enum plane_stereo_format {
 130        PLANE_STEREO_FORMAT_NONE = 0,
 131        PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
 132        PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
 133        PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
 134        PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
 135        PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
 136        PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
 137};
 138
 139/* TODO: Find way to calculate number of bits
 140 *  Please increase if pixel_format enum increases
 141 * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
 142 */
 143
 144enum dc_edid_connector_type {
 145        DC_EDID_CONNECTOR_UNKNOWN = 0,
 146        DC_EDID_CONNECTOR_ANALOG = 1,
 147        DC_EDID_CONNECTOR_DIGITAL = 10,
 148        DC_EDID_CONNECTOR_DVI = 11,
 149        DC_EDID_CONNECTOR_HDMIA = 12,
 150        DC_EDID_CONNECTOR_MDDI = 14,
 151        DC_EDID_CONNECTOR_DISPLAYPORT = 15
 152};
 153
 154enum dc_edid_status {
 155        EDID_OK,
 156        EDID_BAD_INPUT,
 157        EDID_NO_RESPONSE,
 158        EDID_BAD_CHECKSUM,
 159        EDID_THE_SAME,
 160};
 161
 162/* audio capability from EDID*/
 163struct dc_cea_audio_mode {
 164        uint8_t format_code; /* ucData[0] [6:3]*/
 165        uint8_t channel_count; /* ucData[0] [2:0]*/
 166        uint8_t sample_rate; /* ucData[1]*/
 167        union {
 168                uint8_t sample_size; /* for LPCM*/
 169                /*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
 170                uint8_t max_bit_rate;
 171                uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
 172        };
 173};
 174
 175struct dc_edid {
 176        uint32_t length;
 177        uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
 178};
 179
 180/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
 181 * is used. In this case we assume speaker location are: front left, front
 182 * right and front center. */
 183#define DEFAULT_SPEAKER_LOCATION 5
 184
 185#define DC_MAX_AUDIO_DESC_COUNT 16
 186
 187#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
 188
 189union display_content_support {
 190        unsigned int raw;
 191        struct {
 192                unsigned int valid_content_type :1;
 193                unsigned int game_content :1;
 194                unsigned int cinema_content :1;
 195                unsigned int photo_content :1;
 196                unsigned int graphics_content :1;
 197                unsigned int reserved :27;
 198        } bits;
 199};
 200
 201struct dc_panel_patch {
 202        unsigned int dppowerup_delay;
 203        unsigned int extra_t12_ms;
 204        unsigned int extra_delay_backlight_off;
 205};
 206
 207struct dc_edid_caps {
 208        /* sink identification */
 209        uint16_t manufacturer_id;
 210        uint16_t product_id;
 211        uint32_t serial_number;
 212        uint8_t manufacture_week;
 213        uint8_t manufacture_year;
 214        uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 215
 216        /* audio caps */
 217        uint8_t speaker_flags;
 218        uint32_t audio_mode_count;
 219        struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
 220        uint32_t audio_latency;
 221        uint32_t video_latency;
 222
 223        union display_content_support content_support;
 224
 225        uint8_t qs_bit;
 226        uint8_t qy_bit;
 227
 228        /*HDMI 2.0 caps*/
 229        bool lte_340mcsc_scramble;
 230
 231        bool edid_hdmi;
 232        bool hdr_supported;
 233
 234        struct dc_panel_patch panel_patch;
 235};
 236
 237struct view {
 238        uint32_t width;
 239        uint32_t height;
 240};
 241
 242struct dc_mode_flags {
 243        /* note: part of refresh rate flag*/
 244        uint32_t INTERLACE :1;
 245        /* native display timing*/
 246        uint32_t NATIVE :1;
 247        /* preferred is the recommended mode, one per display */
 248        uint32_t PREFERRED :1;
 249        /* true if this mode should use reduced blanking timings
 250         *_not_ related to the Reduced Blanking adjustment*/
 251        uint32_t REDUCED_BLANKING :1;
 252        /* note: part of refreshrate flag*/
 253        uint32_t VIDEO_OPTIMIZED_RATE :1;
 254        /* should be reported to upper layers as mode_flags*/
 255        uint32_t PACKED_PIXEL_FORMAT :1;
 256        /*< preferred view*/
 257        uint32_t PREFERRED_VIEW :1;
 258        /* this timing should be used only in tiled mode*/
 259        uint32_t TILED_MODE :1;
 260        uint32_t DSE_MODE :1;
 261        /* Refresh rate divider when Miracast sink is using a
 262         different rate than the output display device
 263         Must be zero for wired displays and non-zero for
 264         Miracast displays*/
 265        uint32_t MIRACAST_REFRESH_DIVIDER;
 266};
 267
 268
 269enum dc_timing_source {
 270        TIMING_SOURCE_UNDEFINED,
 271
 272        /* explicitly specifed by user, most important*/
 273        TIMING_SOURCE_USER_FORCED,
 274        TIMING_SOURCE_USER_OVERRIDE,
 275        TIMING_SOURCE_CUSTOM,
 276        TIMING_SOURCE_EXPLICIT,
 277
 278        /* explicitly specified by the display device, more important*/
 279        TIMING_SOURCE_EDID_CEA_SVD_3D,
 280        TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
 281        TIMING_SOURCE_EDID_CEA_SVD_420,
 282        TIMING_SOURCE_EDID_DETAILED,
 283        TIMING_SOURCE_EDID_ESTABLISHED,
 284        TIMING_SOURCE_EDID_STANDARD,
 285        TIMING_SOURCE_EDID_CEA_SVD,
 286        TIMING_SOURCE_EDID_CVT_3BYTE,
 287        TIMING_SOURCE_EDID_4BYTE,
 288        TIMING_SOURCE_VBIOS,
 289        TIMING_SOURCE_CV,
 290        TIMING_SOURCE_TV,
 291        TIMING_SOURCE_HDMI_VIC,
 292
 293        /* implicitly specified by display device, still safe but less important*/
 294        TIMING_SOURCE_DEFAULT,
 295
 296        /* only used for custom base modes */
 297        TIMING_SOURCE_CUSTOM_BASE,
 298
 299        /* these timing might not work, least important*/
 300        TIMING_SOURCE_RANGELIMIT,
 301        TIMING_SOURCE_OS_FORCED,
 302        TIMING_SOURCE_IMPLICIT,
 303
 304        /* only used by default mode list*/
 305        TIMING_SOURCE_BASICMODE,
 306
 307        TIMING_SOURCE_COUNT
 308};
 309
 310
 311struct stereo_3d_features {
 312        bool supported                  ;
 313        bool allTimings                 ;
 314        bool cloneMode                  ;
 315        bool scaling                    ;
 316        bool singleFrameSWPacked;
 317};
 318
 319enum dc_timing_support_method {
 320        TIMING_SUPPORT_METHOD_UNDEFINED,
 321        TIMING_SUPPORT_METHOD_EXPLICIT,
 322        TIMING_SUPPORT_METHOD_IMPLICIT,
 323        TIMING_SUPPORT_METHOD_NATIVE
 324};
 325
 326struct dc_mode_info {
 327        uint32_t pixel_width;
 328        uint32_t pixel_height;
 329        uint32_t field_rate;
 330        /* Vertical refresh rate for progressive modes.
 331        * Field rate for interlaced modes.*/
 332
 333        enum dc_timing_standard timing_standard;
 334        enum dc_timing_source timing_source;
 335        struct dc_mode_flags flags;
 336};
 337
 338enum dc_power_state {
 339        DC_POWER_STATE_ON = 1,
 340        DC_POWER_STATE_STANDBY,
 341        DC_POWER_STATE_SUSPEND,
 342        DC_POWER_STATE_OFF
 343};
 344
 345/* DC PowerStates */
 346enum dc_video_power_state {
 347        DC_VIDEO_POWER_UNSPECIFIED = 0,
 348        DC_VIDEO_POWER_ON = 1,
 349        DC_VIDEO_POWER_STANDBY,
 350        DC_VIDEO_POWER_SUSPEND,
 351        DC_VIDEO_POWER_OFF,
 352        DC_VIDEO_POWER_HIBERNATE,
 353        DC_VIDEO_POWER_SHUTDOWN,
 354        DC_VIDEO_POWER_ULPS,    /* BACO or Ultra-Light-Power-State */
 355        DC_VIDEO_POWER_AFTER_RESET,
 356        DC_VIDEO_POWER_MAXIMUM
 357};
 358
 359enum dc_acpi_cm_power_state {
 360        DC_ACPI_CM_POWER_STATE_D0 = 1,
 361        DC_ACPI_CM_POWER_STATE_D1 = 2,
 362        DC_ACPI_CM_POWER_STATE_D2 = 4,
 363        DC_ACPI_CM_POWER_STATE_D3 = 8
 364};
 365
 366enum dc_connection_type {
 367        dc_connection_none,
 368        dc_connection_single,
 369        dc_connection_mst_branch,
 370        dc_connection_active_dongle
 371};
 372
 373struct dc_csc_adjustments {
 374        struct fixed31_32 contrast;
 375        struct fixed31_32 saturation;
 376        struct fixed31_32 brightness;
 377        struct fixed31_32 hue;
 378};
 379
 380enum dpcd_downstream_port_max_bpc {
 381        DOWN_STREAM_MAX_8BPC = 0,
 382        DOWN_STREAM_MAX_10BPC,
 383        DOWN_STREAM_MAX_12BPC,
 384        DOWN_STREAM_MAX_16BPC
 385};
 386struct dc_dongle_caps {
 387        /* dongle type (DP converter, CV smart dongle) */
 388        enum display_dongle_type dongle_type;
 389        bool extendedCapValid;
 390        /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 391        indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 392        bool is_dp_hdmi_s3d_converter;
 393        bool is_dp_hdmi_ycbcr422_pass_through;
 394        bool is_dp_hdmi_ycbcr420_pass_through;
 395        bool is_dp_hdmi_ycbcr422_converter;
 396        bool is_dp_hdmi_ycbcr420_converter;
 397        uint32_t dp_hdmi_max_bpc;
 398        uint32_t dp_hdmi_max_pixel_clk_in_khz;
 399};
 400/* Scaling format */
 401enum scaling_transformation {
 402        SCALING_TRANSFORMATION_UNINITIALIZED,
 403        SCALING_TRANSFORMATION_IDENTITY = 0x0001,
 404        SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
 405        SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
 406        SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
 407        SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
 408        SCALING_TRANSFORMATION_INVALID = 0x80000000,
 409
 410        /* Flag the first and last */
 411        SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
 412        SCALING_TRANSFORMATION_END =
 413                SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
 414};
 415
 416enum display_content_type {
 417        DISPLAY_CONTENT_TYPE_NO_DATA = 0,
 418        DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
 419        DISPLAY_CONTENT_TYPE_PHOTO = 2,
 420        DISPLAY_CONTENT_TYPE_CINEMA = 4,
 421        DISPLAY_CONTENT_TYPE_GAME = 8
 422};
 423
 424#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 425/* writeback */
 426struct dwb_stereo_params {
 427        bool                            stereo_enabled;         /* false: normal mode, true: 3D stereo */
 428        enum dwb_stereo_type            stereo_type;            /* indicates stereo format */
 429        bool                            stereo_polarity;        /* indicates left eye or right eye comes first in stereo mode */
 430        enum dwb_stereo_eye_select      stereo_eye_select;      /* indicate which eye should be captured */
 431};
 432
 433struct dc_dwb_cnv_params {
 434        unsigned int            src_width;      /* input active width */
 435        unsigned int            src_height;     /* input active height (half-active height in interlaced mode) */
 436        unsigned int            crop_width;     /* cropped window width at cnv output */
 437        bool                    crop_en;        /* window cropping enable in cnv */
 438        unsigned int            crop_height;    /* cropped window height at cnv output */
 439        unsigned int            crop_x;         /* cropped window start x value at cnv output */
 440        unsigned int            crop_y;         /* cropped window start y value at cnv output */
 441        enum dwb_cnv_out_bpc cnv_out_bpc;       /* cnv output pixel depth - 8bpc or 10bpc */
 442};
 443
 444struct dc_dwb_params {
 445        struct dc_dwb_cnv_params        cnv_params;     /* CNV source size and cropping window parameters */
 446        unsigned int                    dest_width;     /* Destination width */
 447        unsigned int                    dest_height;    /* Destination height */
 448        enum dwb_scaler_mode            out_format;     /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
 449        enum dwb_output_depth           output_depth;   /* output pixel depth - 8bpc or 10bpc */
 450        enum dwb_capture_rate           capture_rate;   /* controls the frame capture rate */
 451        struct scaling_taps             scaler_taps;    /* Scaling taps */
 452        enum dwb_subsample_position     subsample_position;
 453        struct dc_transfer_func *out_transfer_func;
 454};
 455#endif
 456
 457/* audio*/
 458
 459union audio_sample_rates {
 460        struct sample_rates {
 461                uint8_t RATE_32:1;
 462                uint8_t RATE_44_1:1;
 463                uint8_t RATE_48:1;
 464                uint8_t RATE_88_2:1;
 465                uint8_t RATE_96:1;
 466                uint8_t RATE_176_4:1;
 467                uint8_t RATE_192:1;
 468        } rate;
 469
 470        uint8_t all;
 471};
 472
 473struct audio_speaker_flags {
 474        uint32_t FL_FR:1;
 475        uint32_t LFE:1;
 476        uint32_t FC:1;
 477        uint32_t RL_RR:1;
 478        uint32_t RC:1;
 479        uint32_t FLC_FRC:1;
 480        uint32_t RLC_RRC:1;
 481        uint32_t SUPPORT_AI:1;
 482};
 483
 484struct audio_speaker_info {
 485        uint32_t ALLSPEAKERS:7;
 486        uint32_t SUPPORT_AI:1;
 487};
 488
 489
 490struct audio_info_flags {
 491
 492        union {
 493
 494                struct audio_speaker_flags speaker_flags;
 495                struct audio_speaker_info   info;
 496
 497                uint8_t all;
 498        };
 499};
 500
 501enum audio_format_code {
 502        AUDIO_FORMAT_CODE_FIRST = 1,
 503        AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
 504
 505        AUDIO_FORMAT_CODE_AC3,
 506        /*Layers 1 & 2 */
 507        AUDIO_FORMAT_CODE_MPEG1,
 508        /*MPEG1 Layer 3 */
 509        AUDIO_FORMAT_CODE_MP3,
 510        /*multichannel */
 511        AUDIO_FORMAT_CODE_MPEG2,
 512        AUDIO_FORMAT_CODE_AAC,
 513        AUDIO_FORMAT_CODE_DTS,
 514        AUDIO_FORMAT_CODE_ATRAC,
 515        AUDIO_FORMAT_CODE_1BITAUDIO,
 516        AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
 517        AUDIO_FORMAT_CODE_DTS_HD,
 518        AUDIO_FORMAT_CODE_MAT_MLP,
 519        AUDIO_FORMAT_CODE_DST,
 520        AUDIO_FORMAT_CODE_WMAPRO,
 521        AUDIO_FORMAT_CODE_LAST,
 522        AUDIO_FORMAT_CODE_COUNT =
 523                AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
 524};
 525
 526struct audio_mode {
 527         /* ucData[0] [6:3] */
 528        enum audio_format_code format_code;
 529        /* ucData[0] [2:0] */
 530        uint8_t channel_count;
 531        /* ucData[1] */
 532        union audio_sample_rates sample_rates;
 533        union {
 534                /* for LPCM */
 535                uint8_t sample_size;
 536                /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
 537                uint8_t max_bit_rate;
 538                /* for Audio Formats 9-15 */
 539                uint8_t vendor_specific;
 540        };
 541};
 542
 543struct audio_info {
 544        struct audio_info_flags flags;
 545        uint32_t video_latency;
 546        uint32_t audio_latency;
 547        uint32_t display_index;
 548        uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 549        uint32_t manufacture_id;
 550        uint32_t product_id;
 551        /* PortID used for ContainerID when defined */
 552        uint32_t port_id[2];
 553        uint32_t mode_count;
 554        /* this field must be last in this struct */
 555        struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
 556};
 557
 558enum dc_infoframe_type {
 559        DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
 560        DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
 561        DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
 562        DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
 563#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 564        DC_DP_INFOFRAME_TYPE_PPS = 0x10,
 565#endif
 566};
 567
 568struct dc_info_packet {
 569        bool valid;
 570        uint8_t hb0;
 571        uint8_t hb1;
 572        uint8_t hb2;
 573        uint8_t hb3;
 574        uint8_t sb[32];
 575};
 576
 577struct dc_info_packet_128 {
 578        bool valid;
 579        uint8_t hb0;
 580        uint8_t hb1;
 581        uint8_t hb2;
 582        uint8_t hb3;
 583        uint8_t sb[128];
 584};
 585
 586#define DC_PLANE_UPDATE_TIMES_MAX 10
 587
 588struct dc_plane_flip_time {
 589        unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
 590        unsigned int index;
 591        unsigned int prev_update_time_in_us;
 592};
 593
 594struct psr_config {
 595        unsigned char psr_version;
 596        unsigned int psr_rfb_setup_time;
 597        bool psr_exit_link_training_required;
 598        bool psr_frame_capture_indication_req;
 599        unsigned int psr_sdp_transmit_line_num_deadline;
 600        bool allow_smu_optimizations;
 601};
 602
 603union dmcu_psr_level {
 604        struct {
 605                unsigned int SKIP_CRC:1;
 606                unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
 607                unsigned int SKIP_PHY_POWER_DOWN:1;
 608                unsigned int SKIP_AUX_ACK_CHECK:1;
 609                unsigned int SKIP_CRTC_DISABLE:1;
 610                unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
 611                unsigned int SKIP_SMU_NOTIFICATION:1;
 612                unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 613                unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 614                unsigned int SKIP_SINGLE_OTG_DISABLE:1;
 615                unsigned int RESERVED:22;
 616        } bits;
 617        unsigned int u32all;
 618};
 619
 620enum physical_phy_id {
 621        PHYLD_0,
 622        PHYLD_1,
 623        PHYLD_2,
 624        PHYLD_3,
 625        PHYLD_4,
 626        PHYLD_5,
 627        PHYLD_6,
 628        PHYLD_7,
 629        PHYLD_8,
 630        PHYLD_9,
 631        PHYLD_COUNT,
 632        PHYLD_UNKNOWN = (-1L)
 633};
 634
 635enum phy_type {
 636        PHY_TYPE_UNKNOWN  = 1,
 637        PHY_TYPE_PCIE_PHY = 2,
 638        PHY_TYPE_UNIPHY = 3,
 639};
 640
 641struct psr_context {
 642        /* ddc line */
 643        enum channel_id channel;
 644        /* Transmitter id */
 645        enum transmitter transmitterId;
 646        /* Engine Id is used for Dig Be source select */
 647        enum engine_id engineId;
 648        /* Controller Id used for Dig Fe source select */
 649        enum controller_id controllerId;
 650        /* Pcie or Uniphy */
 651        enum phy_type phyType;
 652        /* Physical PHY Id used by SMU interpretation */
 653        enum physical_phy_id smuPhyId;
 654        /* Vertical total pixels from crtc timing.
 655         * This is used for static screen detection.
 656         * ie. If we want to detect half a frame,
 657         * we use this to determine the hyst lines.
 658         */
 659        unsigned int crtcTimingVerticalTotal;
 660        /* PSR supported from panel capabilities and
 661         * current display configuration
 662         */
 663        bool psrSupportedDisplayConfig;
 664        /* Whether fast link training is supported by the panel */
 665        bool psrExitLinkTrainingRequired;
 666        /* If RFB setup time is greater than the total VBLANK time,
 667         * it is not possible for the sink to capture the video frame
 668         * in the same frame the SDP is sent. In this case,
 669         * the frame capture indication bit should be set and an extra
 670         * static frame should be transmitted to the sink.
 671         */
 672        bool psrFrameCaptureIndicationReq;
 673        /* Set the last possible line SDP may be transmitted without violating
 674         * the RFB setup time or entering the active video frame.
 675         */
 676        unsigned int sdpTransmitLineNumDeadline;
 677        /* The VSync rate in Hz used to calculate the
 678         * step size for smooth brightness feature
 679         */
 680        unsigned int vsyncRateHz;
 681        unsigned int skipPsrWaitForPllLock;
 682        unsigned int numberOfControllers;
 683        /* Unused, for future use. To indicate that first changed frame from
 684         * state3 shouldn't result in psr_inactive, but rather to perform
 685         * an automatic single frame rfb_update.
 686         */
 687        bool rfb_update_auto_en;
 688        /* Number of frame before entering static screen */
 689        unsigned int timehyst_frames;
 690        /* Partial frames before entering static screen */
 691        unsigned int hyst_lines;
 692        /* # of repeated AUX transaction attempts to make before
 693         * indicating failure to the driver
 694         */
 695        unsigned int aux_repeats;
 696        /* Controls hw blocks to power down during PSR active state */
 697        union dmcu_psr_level psr_level;
 698        /* Controls additional delay after remote frame capture before
 699         * continuing powerd own
 700         */
 701        unsigned int frame_delay;
 702        bool allow_smu_optimizations;
 703};
 704
 705struct colorspace_transform {
 706        struct fixed31_32 matrix[12];
 707        bool enable_remap;
 708};
 709
 710enum i2c_mot_mode {
 711        I2C_MOT_UNDEF,
 712        I2C_MOT_TRUE,
 713        I2C_MOT_FALSE
 714};
 715
 716struct AsicStateEx {
 717        unsigned int memoryClock;
 718        unsigned int displayClock;
 719        unsigned int engineClock;
 720        unsigned int maxSupportedDppClock;
 721        unsigned int dppClock;
 722        unsigned int socClock;
 723        unsigned int dcfClockDeepSleep;
 724        unsigned int fClock;
 725        unsigned int phyClock;
 726};
 727
 728#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 729/* DSC DPCD capabilities */
 730union dsc_slice_caps1 {
 731        struct {
 732                uint8_t NUM_SLICES_1 : 1;
 733                uint8_t NUM_SLICES_2 : 1;
 734                uint8_t RESERVED : 1;
 735                uint8_t NUM_SLICES_4 : 1;
 736                uint8_t NUM_SLICES_6 : 1;
 737                uint8_t NUM_SLICES_8 : 1;
 738                uint8_t NUM_SLICES_10 : 1;
 739                uint8_t NUM_SLICES_12 : 1;
 740        } bits;
 741        uint8_t raw;
 742};
 743
 744union dsc_slice_caps2 {
 745        struct {
 746                uint8_t NUM_SLICES_16 : 1;
 747                uint8_t NUM_SLICES_20 : 1;
 748                uint8_t NUM_SLICES_24 : 1;
 749                uint8_t RESERVED : 5;
 750        } bits;
 751        uint8_t raw;
 752};
 753
 754union dsc_color_formats {
 755        struct {
 756                uint8_t RGB : 1;
 757                uint8_t YCBCR_444 : 1;
 758                uint8_t YCBCR_SIMPLE_422 : 1;
 759                uint8_t YCBCR_NATIVE_422 : 1;
 760                uint8_t YCBCR_NATIVE_420 : 1;
 761                uint8_t RESERVED : 3;
 762        } bits;
 763        uint8_t raw;
 764};
 765
 766union dsc_color_depth {
 767        struct {
 768                uint8_t RESERVED1 : 1;
 769                uint8_t COLOR_DEPTH_8_BPC : 1;
 770                uint8_t COLOR_DEPTH_10_BPC : 1;
 771                uint8_t COLOR_DEPTH_12_BPC : 1;
 772                uint8_t RESERVED2 : 3;
 773        } bits;
 774        uint8_t raw;
 775};
 776
 777struct dsc_dec_dpcd_caps {
 778        bool is_dsc_supported;
 779        uint8_t dsc_version;
 780        int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
 781        union dsc_slice_caps1 slice_caps1;
 782        union dsc_slice_caps2 slice_caps2;
 783        int32_t lb_bit_depth;
 784        bool is_block_pred_supported;
 785        int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
 786        union dsc_color_formats color_formats;
 787        union dsc_color_depth color_depth;
 788        int32_t throughput_mode_0_mps; /* In MPs */
 789        int32_t throughput_mode_1_mps; /* In MPs */
 790        int32_t max_slice_width;
 791        uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
 792
 793        /* Extended DSC caps */
 794        uint32_t branch_overall_throughput_0_mps; /* In MPs */
 795        uint32_t branch_overall_throughput_1_mps; /* In MPs */
 796        uint32_t branch_max_line_width;
 797};
 798#endif
 799#endif /* DC_TYPES_H_ */
 800