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27#include <linux/slab.h>
28
29#include "dm_services.h"
30
31
32#include "stream_encoder.h"
33#include "resource.h"
34#include "include/irq_service_interface.h"
35#include "dce120_resource.h"
36
37#include "dce112/dce112_resource.h"
38
39#include "dce110/dce110_resource.h"
40#include "../virtual/virtual_stream_encoder.h"
41#include "dce120_timing_generator.h"
42#include "irq/dce120/irq_service_dce120.h"
43#include "dce/dce_opp.h"
44#include "dce/dce_clock_source.h"
45#include "dce/dce_ipp.h"
46#include "dce/dce_mem_input.h"
47
48#include "dce110/dce110_hw_sequencer.h"
49#include "dce120/dce120_hw_sequencer.h"
50#include "dce/dce_transform.h"
51#include "clk_mgr.h"
52#include "dce/dce_audio.h"
53#include "dce/dce_link_encoder.h"
54#include "dce/dce_stream_encoder.h"
55#include "dce/dce_hwseq.h"
56#include "dce/dce_abm.h"
57#include "dce/dce_dmcu.h"
58#include "dce/dce_aux.h"
59#include "dce/dce_i2c.h"
60
61#include "dce/dce_12_0_offset.h"
62#include "dce/dce_12_0_sh_mask.h"
63#include "soc15_hw_ip.h"
64#include "vega10_ip_offset.h"
65#include "nbio/nbio_6_1_offset.h"
66#include "mmhub/mmhub_9_4_0_offset.h"
67#include "mmhub/mmhub_9_4_0_sh_mask.h"
68#include "reg_helper.h"
69
70#include "dce100/dce100_resource.h"
71
72#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
74 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
76 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
78 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
80 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
82 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
84 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
86 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87#endif
88
89enum dce120_clk_src_array_id {
90 DCE120_CLK_SRC_PLL0,
91 DCE120_CLK_SRC_PLL1,
92 DCE120_CLK_SRC_PLL2,
93 DCE120_CLK_SRC_PLL3,
94 DCE120_CLK_SRC_PLL4,
95 DCE120_CLK_SRC_PLL5,
96
97 DCE120_CLK_SRC_TOTAL
98};
99
100static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
101 {
102 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
103 },
104 {
105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
106 },
107 {
108 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
109 },
110 {
111 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
112 },
113 {
114 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
118 }
119};
120
121
122
123
124#define BASE_INNER(seg) \
125 DCE_BASE__INST0_SEG ## seg
126
127#define NBIO_BASE_INNER(seg) \
128 NBIF_BASE__INST0_SEG ## seg
129
130#define NBIO_BASE(seg) \
131 NBIO_BASE_INNER(seg)
132
133
134#define BASE(seg) \
135 BASE_INNER(seg)
136
137#define SR(reg_name)\
138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
139 mm ## reg_name
140
141#define SRI(reg_name, block, id)\
142 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
144
145
146#define MMHUB_BASE_INNER(seg) \
147 MMHUB_BASE__INST0_SEG ## seg
148
149#define MMHUB_BASE(seg) \
150 MMHUB_BASE_INNER(seg)
151
152#define MMHUB_SR(reg_name)\
153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
154 mm ## reg_name
155
156
157
158
159
160static const struct dce_dmcu_registers dmcu_regs = {
161 DMCU_DCE110_COMMON_REG_LIST()
162};
163
164static const struct dce_dmcu_shift dmcu_shift = {
165 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
166};
167
168static const struct dce_dmcu_mask dmcu_mask = {
169 DMCU_MASK_SH_LIST_DCE110(_MASK)
170};
171
172static const struct dce_abm_registers abm_regs = {
173 ABM_DCE110_COMMON_REG_LIST()
174};
175
176static const struct dce_abm_shift abm_shift = {
177 ABM_MASK_SH_LIST_DCE110(__SHIFT)
178};
179
180static const struct dce_abm_mask abm_mask = {
181 ABM_MASK_SH_LIST_DCE110(_MASK)
182};
183
184#define ipp_regs(id)\
185[id] = {\
186 IPP_DCE110_REG_LIST_DCE_BASE(id)\
187}
188
189static const struct dce_ipp_registers ipp_regs[] = {
190 ipp_regs(0),
191 ipp_regs(1),
192 ipp_regs(2),
193 ipp_regs(3),
194 ipp_regs(4),
195 ipp_regs(5)
196};
197
198static const struct dce_ipp_shift ipp_shift = {
199 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
200};
201
202static const struct dce_ipp_mask ipp_mask = {
203 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
204};
205
206#define transform_regs(id)\
207[id] = {\
208 XFM_COMMON_REG_LIST_DCE110(id)\
209}
210
211static const struct dce_transform_registers xfm_regs[] = {
212 transform_regs(0),
213 transform_regs(1),
214 transform_regs(2),
215 transform_regs(3),
216 transform_regs(4),
217 transform_regs(5)
218};
219
220static const struct dce_transform_shift xfm_shift = {
221 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
222};
223
224static const struct dce_transform_mask xfm_mask = {
225 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
226};
227
228#define aux_regs(id)\
229[id] = {\
230 AUX_REG_LIST(id)\
231}
232
233static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 aux_regs(0),
235 aux_regs(1),
236 aux_regs(2),
237 aux_regs(3),
238 aux_regs(4),
239 aux_regs(5)
240};
241
242#define hpd_regs(id)\
243[id] = {\
244 HPD_REG_LIST(id)\
245}
246
247static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
248 hpd_regs(0),
249 hpd_regs(1),
250 hpd_regs(2),
251 hpd_regs(3),
252 hpd_regs(4),
253 hpd_regs(5)
254};
255
256#define link_regs(id)\
257[id] = {\
258 LE_DCE120_REG_LIST(id), \
259 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
260}
261
262static const struct dce110_link_enc_registers link_enc_regs[] = {
263 link_regs(0),
264 link_regs(1),
265 link_regs(2),
266 link_regs(3),
267 link_regs(4),
268 link_regs(5),
269 link_regs(6),
270};
271
272
273#define stream_enc_regs(id)\
274[id] = {\
275 SE_COMMON_REG_LIST(id),\
276 .TMDS_CNTL = 0,\
277}
278
279static const struct dce110_stream_enc_registers stream_enc_regs[] = {
280 stream_enc_regs(0),
281 stream_enc_regs(1),
282 stream_enc_regs(2),
283 stream_enc_regs(3),
284 stream_enc_regs(4),
285 stream_enc_regs(5)
286};
287
288static const struct dce_stream_encoder_shift se_shift = {
289 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
290};
291
292static const struct dce_stream_encoder_mask se_mask = {
293 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
294};
295
296#define opp_regs(id)\
297[id] = {\
298 OPP_DCE_120_REG_LIST(id),\
299}
300
301static const struct dce_opp_registers opp_regs[] = {
302 opp_regs(0),
303 opp_regs(1),
304 opp_regs(2),
305 opp_regs(3),
306 opp_regs(4),
307 opp_regs(5)
308};
309
310static const struct dce_opp_shift opp_shift = {
311 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
312};
313
314static const struct dce_opp_mask opp_mask = {
315 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
316};
317 #define aux_engine_regs(id)\
318[id] = {\
319 AUX_COMMON_REG_LIST(id), \
320 .AUX_RESET_MASK = 0 \
321}
322
323static const struct dce110_aux_registers aux_engine_regs[] = {
324 aux_engine_regs(0),
325 aux_engine_regs(1),
326 aux_engine_regs(2),
327 aux_engine_regs(3),
328 aux_engine_regs(4),
329 aux_engine_regs(5)
330};
331
332#define audio_regs(id)\
333[id] = {\
334 AUD_COMMON_REG_LIST(id)\
335}
336
337static const struct dce_audio_registers audio_regs[] = {
338 audio_regs(0),
339 audio_regs(1),
340 audio_regs(2),
341 audio_regs(3),
342 audio_regs(4),
343 audio_regs(5)
344};
345
346#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
348 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
349 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
350
351static const struct dce_audio_shift audio_shift = {
352 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
353};
354
355static const struct dce_aduio_mask audio_mask = {
356 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
357};
358
359#define clk_src_regs(index, id)\
360[index] = {\
361 CS_COMMON_REG_LIST_DCE_112(id),\
362}
363
364static const struct dce110_clk_src_regs clk_src_regs[] = {
365 clk_src_regs(0, A),
366 clk_src_regs(1, B),
367 clk_src_regs(2, C),
368 clk_src_regs(3, D),
369 clk_src_regs(4, E),
370 clk_src_regs(5, F)
371};
372
373static const struct dce110_clk_src_shift cs_shift = {
374 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
375};
376
377static const struct dce110_clk_src_mask cs_mask = {
378 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
379};
380
381struct output_pixel_processor *dce120_opp_create(
382 struct dc_context *ctx,
383 uint32_t inst)
384{
385 struct dce110_opp *opp =
386 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
387
388 if (!opp)
389 return NULL;
390
391 dce110_opp_construct(opp,
392 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
393 return &opp->base;
394}
395struct dce_aux *dce120_aux_engine_create(
396 struct dc_context *ctx,
397 uint32_t inst)
398{
399 struct aux_engine_dce110 *aux_engine =
400 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
401
402 if (!aux_engine)
403 return NULL;
404
405 dce110_aux_engine_construct(aux_engine, ctx, inst,
406 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
407 &aux_engine_regs[inst]);
408
409 return &aux_engine->base;
410}
411#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
412
413static const struct dce_i2c_registers i2c_hw_regs[] = {
414 i2c_inst_regs(1),
415 i2c_inst_regs(2),
416 i2c_inst_regs(3),
417 i2c_inst_regs(4),
418 i2c_inst_regs(5),
419 i2c_inst_regs(6),
420};
421
422static const struct dce_i2c_shift i2c_shifts = {
423 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
424};
425
426static const struct dce_i2c_mask i2c_masks = {
427 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
428};
429
430struct dce_i2c_hw *dce120_i2c_hw_create(
431 struct dc_context *ctx,
432 uint32_t inst)
433{
434 struct dce_i2c_hw *dce_i2c_hw =
435 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
436
437 if (!dce_i2c_hw)
438 return NULL;
439
440 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
441 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
442
443 return dce_i2c_hw;
444}
445static const struct bios_registers bios_regs = {
446 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
447 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
448};
449
450static const struct resource_caps res_cap = {
451 .num_timing_generator = 6,
452 .num_audio = 7,
453 .num_stream_encoder = 6,
454 .num_pll = 6,
455 .num_ddc = 6,
456};
457
458static const struct dc_plane_cap plane_cap = {
459 .type = DC_PLANE_TYPE_DCE_RGB,
460
461 .pixel_format_support = {
462 .argb8888 = true,
463 .nv12 = false,
464 .fp16 = false
465 },
466
467 .max_upscale_factor = {
468 .argb8888 = 16000,
469 .nv12 = 1,
470 .fp16 = 1
471 },
472
473 .max_downscale_factor = {
474 .argb8888 = 250,
475 .nv12 = 1,
476 .fp16 = 1
477 }
478};
479
480static const struct dc_debug_options debug_defaults = {
481 .disable_clock_gate = true,
482};
483
484static struct clock_source *dce120_clock_source_create(
485 struct dc_context *ctx,
486 struct dc_bios *bios,
487 enum clock_source_id id,
488 const struct dce110_clk_src_regs *regs,
489 bool dp_clk_src)
490{
491 struct dce110_clk_src *clk_src =
492 kzalloc(sizeof(*clk_src), GFP_KERNEL);
493
494 if (!clk_src)
495 return NULL;
496
497 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
498 regs, &cs_shift, &cs_mask)) {
499 clk_src->base.dp_clk_src = dp_clk_src;
500 return &clk_src->base;
501 }
502
503 BREAK_TO_DEBUGGER();
504 return NULL;
505}
506
507static void dce120_clock_source_destroy(struct clock_source **clk_src)
508{
509 kfree(TO_DCE110_CLK_SRC(*clk_src));
510 *clk_src = NULL;
511}
512
513
514static bool dce120_hw_sequencer_create(struct dc *dc)
515{
516
517
518
519 dce120_hw_sequencer_construct(dc);
520
521
522
523 return true;
524}
525
526static struct timing_generator *dce120_timing_generator_create(
527 struct dc_context *ctx,
528 uint32_t instance,
529 const struct dce110_timing_generator_offsets *offsets)
530{
531 struct dce110_timing_generator *tg110 =
532 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
533
534 if (!tg110)
535 return NULL;
536
537 dce120_timing_generator_construct(tg110, ctx, instance, offsets);
538 return &tg110->base;
539}
540
541static void dce120_transform_destroy(struct transform **xfm)
542{
543 kfree(TO_DCE_TRANSFORM(*xfm));
544 *xfm = NULL;
545}
546
547static void destruct(struct dce110_resource_pool *pool)
548{
549 unsigned int i;
550
551 for (i = 0; i < pool->base.pipe_count; i++) {
552 if (pool->base.opps[i] != NULL)
553 dce110_opp_destroy(&pool->base.opps[i]);
554
555 if (pool->base.transforms[i] != NULL)
556 dce120_transform_destroy(&pool->base.transforms[i]);
557
558 if (pool->base.ipps[i] != NULL)
559 dce_ipp_destroy(&pool->base.ipps[i]);
560
561 if (pool->base.mis[i] != NULL) {
562 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
563 pool->base.mis[i] = NULL;
564 }
565
566 if (pool->base.irqs != NULL) {
567 dal_irq_service_destroy(&pool->base.irqs);
568 }
569
570 if (pool->base.timing_generators[i] != NULL) {
571 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
572 pool->base.timing_generators[i] = NULL;
573 }
574 }
575
576 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
577 if (pool->base.engines[i] != NULL)
578 dce110_engine_destroy(&pool->base.engines[i]);
579 if (pool->base.hw_i2cs[i] != NULL) {
580 kfree(pool->base.hw_i2cs[i]);
581 pool->base.hw_i2cs[i] = NULL;
582 }
583 if (pool->base.sw_i2cs[i] != NULL) {
584 kfree(pool->base.sw_i2cs[i]);
585 pool->base.sw_i2cs[i] = NULL;
586 }
587 }
588
589 for (i = 0; i < pool->base.audio_count; i++) {
590 if (pool->base.audios[i])
591 dce_aud_destroy(&pool->base.audios[i]);
592 }
593
594 for (i = 0; i < pool->base.stream_enc_count; i++) {
595 if (pool->base.stream_enc[i] != NULL)
596 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
597 }
598
599 for (i = 0; i < pool->base.clk_src_count; i++) {
600 if (pool->base.clock_sources[i] != NULL)
601 dce120_clock_source_destroy(
602 &pool->base.clock_sources[i]);
603 }
604
605 if (pool->base.dp_clock_source != NULL)
606 dce120_clock_source_destroy(&pool->base.dp_clock_source);
607
608 if (pool->base.abm != NULL)
609 dce_abm_destroy(&pool->base.abm);
610
611 if (pool->base.dmcu != NULL)
612 dce_dmcu_destroy(&pool->base.dmcu);
613}
614
615static void read_dce_straps(
616 struct dc_context *ctx,
617 struct resource_straps *straps)
618{
619 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
620
621 straps->audio_stream_number = get_reg_field_value(reg_val,
622 CC_DC_MISC_STRAPS,
623 AUDIO_STREAM_NUMBER);
624 straps->hdmi_disable = get_reg_field_value(reg_val,
625 CC_DC_MISC_STRAPS,
626 HDMI_DISABLE);
627
628 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
629 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
630 DC_PINSTRAPS,
631 DC_PINSTRAPS_AUDIO);
632}
633
634static struct audio *create_audio(
635 struct dc_context *ctx, unsigned int inst)
636{
637 return dce_audio_create(ctx, inst,
638 &audio_regs[inst], &audio_shift, &audio_mask);
639}
640
641static const struct encoder_feature_support link_enc_feature = {
642 .max_hdmi_deep_color = COLOR_DEPTH_121212,
643 .max_hdmi_pixel_clock = 600000,
644 .hdmi_ycbcr420_supported = true,
645 .dp_ycbcr420_supported = false,
646 .flags.bits.IS_HBR2_CAPABLE = true,
647 .flags.bits.IS_HBR3_CAPABLE = true,
648 .flags.bits.IS_TPS3_CAPABLE = true,
649 .flags.bits.IS_TPS4_CAPABLE = true,
650};
651
652static struct link_encoder *dce120_link_encoder_create(
653 const struct encoder_init_data *enc_init_data)
654{
655 struct dce110_link_encoder *enc110 =
656 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
657
658 if (!enc110)
659 return NULL;
660
661 dce110_link_encoder_construct(enc110,
662 enc_init_data,
663 &link_enc_feature,
664 &link_enc_regs[enc_init_data->transmitter],
665 &link_enc_aux_regs[enc_init_data->channel - 1],
666 &link_enc_hpd_regs[enc_init_data->hpd_source]);
667
668 return &enc110->base;
669}
670
671static struct input_pixel_processor *dce120_ipp_create(
672 struct dc_context *ctx, uint32_t inst)
673{
674 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
675
676 if (!ipp) {
677 BREAK_TO_DEBUGGER();
678 return NULL;
679 }
680
681 dce_ipp_construct(ipp, ctx, inst,
682 &ipp_regs[inst], &ipp_shift, &ipp_mask);
683 return &ipp->base;
684}
685
686static struct stream_encoder *dce120_stream_encoder_create(
687 enum engine_id eng_id,
688 struct dc_context *ctx)
689{
690 struct dce110_stream_encoder *enc110 =
691 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
692
693 if (!enc110)
694 return NULL;
695
696 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
697 &stream_enc_regs[eng_id],
698 &se_shift, &se_mask);
699 return &enc110->base;
700}
701
702#define SRII(reg_name, block, id)\
703 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
704 mm ## block ## id ## _ ## reg_name
705
706static const struct dce_hwseq_registers hwseq_reg = {
707 HWSEQ_DCE120_REG_LIST()
708};
709
710static const struct dce_hwseq_shift hwseq_shift = {
711 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
712};
713
714static const struct dce_hwseq_mask hwseq_mask = {
715 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
716};
717
718
719static const struct dce_hwseq_registers dce121_hwseq_reg = {
720 HWSEQ_VG20_REG_LIST()
721};
722
723static const struct dce_hwseq_shift dce121_hwseq_shift = {
724 HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
725};
726
727static const struct dce_hwseq_mask dce121_hwseq_mask = {
728 HWSEQ_VG20_MASK_SH_LIST(_MASK)
729};
730
731static struct dce_hwseq *dce120_hwseq_create(
732 struct dc_context *ctx)
733{
734 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
735
736 if (hws) {
737 hws->ctx = ctx;
738 hws->regs = &hwseq_reg;
739 hws->shifts = &hwseq_shift;
740 hws->masks = &hwseq_mask;
741 }
742 return hws;
743}
744
745static struct dce_hwseq *dce121_hwseq_create(
746 struct dc_context *ctx)
747{
748 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
749
750 if (hws) {
751 hws->ctx = ctx;
752 hws->regs = &dce121_hwseq_reg;
753 hws->shifts = &dce121_hwseq_shift;
754 hws->masks = &dce121_hwseq_mask;
755 }
756 return hws;
757}
758
759static const struct resource_create_funcs res_create_funcs = {
760 .read_dce_straps = read_dce_straps,
761 .create_audio = create_audio,
762 .create_stream_encoder = dce120_stream_encoder_create,
763 .create_hwseq = dce120_hwseq_create,
764};
765
766static const struct resource_create_funcs dce121_res_create_funcs = {
767 .read_dce_straps = read_dce_straps,
768 .create_audio = create_audio,
769 .create_stream_encoder = dce120_stream_encoder_create,
770 .create_hwseq = dce121_hwseq_create,
771};
772
773
774#define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
775static const struct dce_mem_input_registers mi_regs[] = {
776 mi_inst_regs(0),
777 mi_inst_regs(1),
778 mi_inst_regs(2),
779 mi_inst_regs(3),
780 mi_inst_regs(4),
781 mi_inst_regs(5),
782};
783
784static const struct dce_mem_input_shift mi_shifts = {
785 MI_DCE12_MASK_SH_LIST(__SHIFT)
786};
787
788static const struct dce_mem_input_mask mi_masks = {
789 MI_DCE12_MASK_SH_LIST(_MASK)
790};
791
792static struct mem_input *dce120_mem_input_create(
793 struct dc_context *ctx,
794 uint32_t inst)
795{
796 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
797 GFP_KERNEL);
798
799 if (!dce_mi) {
800 BREAK_TO_DEBUGGER();
801 return NULL;
802 }
803
804 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
805 return &dce_mi->base;
806}
807
808static struct transform *dce120_transform_create(
809 struct dc_context *ctx,
810 uint32_t inst)
811{
812 struct dce_transform *transform =
813 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
814
815 if (!transform)
816 return NULL;
817
818 dce_transform_construct(transform, ctx, inst,
819 &xfm_regs[inst], &xfm_shift, &xfm_mask);
820 transform->lb_memory_size = 0x1404;
821 return &transform->base;
822}
823
824static void dce120_destroy_resource_pool(struct resource_pool **pool)
825{
826 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
827
828 destruct(dce110_pool);
829 kfree(dce110_pool);
830 *pool = NULL;
831}
832
833static const struct resource_funcs dce120_res_pool_funcs = {
834 .destroy = dce120_destroy_resource_pool,
835 .link_enc_create = dce120_link_encoder_create,
836 .validate_bandwidth = dce112_validate_bandwidth,
837 .validate_plane = dce100_validate_plane,
838 .add_stream_to_ctx = dce112_add_stream_to_ctx,
839 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
840};
841
842static void bw_calcs_data_update_from_pplib(struct dc *dc)
843{
844 struct dm_pp_clock_levels_with_latency eng_clks = {0};
845 struct dm_pp_clock_levels_with_latency mem_clks = {0};
846 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
847 int i;
848 unsigned int clk;
849 unsigned int latency;
850
851
852 if (!dm_pp_get_clock_levels_by_type_with_latency(
853 dc->ctx,
854 DM_PP_CLOCK_TYPE_ENGINE_CLK,
855 &eng_clks) || eng_clks.num_levels == 0) {
856
857 eng_clks.num_levels = 8;
858 clk = 300000;
859
860 for (i = 0; i < eng_clks.num_levels; i++) {
861 eng_clks.data[i].clocks_in_khz = clk;
862 clk += 100000;
863 }
864 }
865
866
867 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
868 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
869 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
870 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
871 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
872 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
873 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
874 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
875 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
876 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
877 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
878 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
879 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
880 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
881 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
882 eng_clks.data[0].clocks_in_khz, 1000);
883
884
885 if (!dm_pp_get_clock_levels_by_type_with_latency(
886 dc->ctx,
887 DM_PP_CLOCK_TYPE_MEMORY_CLK,
888 &mem_clks) || mem_clks.num_levels == 0) {
889
890 mem_clks.num_levels = 3;
891 clk = 250000;
892 latency = 45;
893
894 for (i = 0; i < eng_clks.num_levels; i++) {
895 mem_clks.data[i].clocks_in_khz = clk;
896 mem_clks.data[i].latency_in_us = latency;
897 clk += 500000;
898 latency -= 5;
899 }
900
901 }
902
903
904
905
906
907
908 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
909 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
910 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
911 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
912 1000);
913 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
914 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
915 1000);
916
917
918
919
920
921
922 clk_ranges.num_wm_sets = 4;
923 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
924 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
925 eng_clks.data[0].clocks_in_khz;
926 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
927 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
928 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
929 mem_clks.data[0].clocks_in_khz;
930 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
931 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
932
933 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
934 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
935 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
936
937 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
938 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
939 mem_clks.data[0].clocks_in_khz;
940 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
941 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
942
943 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
944 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
945 eng_clks.data[0].clocks_in_khz;
946 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
947 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
948 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
949 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
950
951 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
952
953 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
954 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
955 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
956
957 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
958 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
959 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
960
961 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
962
963
964 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
965}
966
967static uint32_t read_pipe_fuses(struct dc_context *ctx)
968{
969 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
970
971 value = value & 0x3f;
972 return value;
973}
974
975static bool construct(
976 uint8_t num_virtual_links,
977 struct dc *dc,
978 struct dce110_resource_pool *pool)
979{
980 unsigned int i;
981 int j;
982 struct dc_context *ctx = dc->ctx;
983 struct irq_service_init_data irq_init_data;
984 static const struct resource_create_funcs *res_funcs;
985 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
986 uint32_t pipe_fuses;
987
988 ctx->dc_bios->regs = &bios_regs;
989
990 pool->base.res_cap = &res_cap;
991 pool->base.funcs = &dce120_res_pool_funcs;
992
993
994 pool->base.pipe_count = res_cap.num_timing_generator;
995 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
996 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
997
998 dc->caps.max_downscale_ratio = 200;
999 dc->caps.i2c_speed_in_khz = 100;
1000 dc->caps.max_cursor_size = 128;
1001 dc->caps.dual_link_dvi = true;
1002 dc->caps.psp_setup_panel_mode = true;
1003
1004 dc->debug = debug_defaults;
1005
1006
1007
1008
1009
1010 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1011 dce120_clock_source_create(ctx, ctx->dc_bios,
1012 CLOCK_SOURCE_COMBO_PHY_PLL0,
1013 &clk_src_regs[0], false);
1014 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1015 dce120_clock_source_create(ctx, ctx->dc_bios,
1016 CLOCK_SOURCE_COMBO_PHY_PLL1,
1017 &clk_src_regs[1], false);
1018 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1019 dce120_clock_source_create(ctx, ctx->dc_bios,
1020 CLOCK_SOURCE_COMBO_PHY_PLL2,
1021 &clk_src_regs[2], false);
1022 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1023 dce120_clock_source_create(ctx, ctx->dc_bios,
1024 CLOCK_SOURCE_COMBO_PHY_PLL3,
1025 &clk_src_regs[3], false);
1026 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1027 dce120_clock_source_create(ctx, ctx->dc_bios,
1028 CLOCK_SOURCE_COMBO_PHY_PLL4,
1029 &clk_src_regs[4], false);
1030 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1031 dce120_clock_source_create(ctx, ctx->dc_bios,
1032 CLOCK_SOURCE_COMBO_PHY_PLL5,
1033 &clk_src_regs[5], false);
1034 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1035
1036 pool->base.dp_clock_source =
1037 dce120_clock_source_create(ctx, ctx->dc_bios,
1038 CLOCK_SOURCE_ID_DP_DTO,
1039 &clk_src_regs[0], true);
1040
1041 for (i = 0; i < pool->base.clk_src_count; i++) {
1042 if (pool->base.clock_sources[i] == NULL) {
1043 dm_error("DC: failed to create clock sources!\n");
1044 BREAK_TO_DEBUGGER();
1045 goto clk_src_create_fail;
1046 }
1047 }
1048
1049 pool->base.dmcu = dce_dmcu_create(ctx,
1050 &dmcu_regs,
1051 &dmcu_shift,
1052 &dmcu_mask);
1053 if (pool->base.dmcu == NULL) {
1054 dm_error("DC: failed to create dmcu!\n");
1055 BREAK_TO_DEBUGGER();
1056 goto res_create_fail;
1057 }
1058
1059 pool->base.abm = dce_abm_create(ctx,
1060 &abm_regs,
1061 &abm_shift,
1062 &abm_mask);
1063 if (pool->base.abm == NULL) {
1064 dm_error("DC: failed to create abm!\n");
1065 BREAK_TO_DEBUGGER();
1066 goto res_create_fail;
1067 }
1068
1069
1070 irq_init_data.ctx = dc->ctx;
1071 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1072 if (!pool->base.irqs)
1073 goto irqs_create_fail;
1074
1075
1076 if (is_vg20)
1077 pipe_fuses = read_pipe_fuses(ctx);
1078
1079
1080 j = 0;
1081 for (i = 0; i < pool->base.pipe_count; i++) {
1082 if (is_vg20) {
1083 if ((pipe_fuses & (1 << i)) != 0) {
1084 dm_error("DC: skip invalid pipe %d!\n", i);
1085 continue;
1086 }
1087 }
1088
1089 pool->base.timing_generators[j] =
1090 dce120_timing_generator_create(
1091 ctx,
1092 i,
1093 &dce120_tg_offsets[i]);
1094 if (pool->base.timing_generators[j] == NULL) {
1095 BREAK_TO_DEBUGGER();
1096 dm_error("DC: failed to create tg!\n");
1097 goto controller_create_fail;
1098 }
1099
1100 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1101
1102 if (pool->base.mis[j] == NULL) {
1103 BREAK_TO_DEBUGGER();
1104 dm_error(
1105 "DC: failed to create memory input!\n");
1106 goto controller_create_fail;
1107 }
1108
1109 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1110 if (pool->base.ipps[i] == NULL) {
1111 BREAK_TO_DEBUGGER();
1112 dm_error(
1113 "DC: failed to create input pixel processor!\n");
1114 goto controller_create_fail;
1115 }
1116
1117 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1118 if (pool->base.transforms[i] == NULL) {
1119 BREAK_TO_DEBUGGER();
1120 dm_error(
1121 "DC: failed to create transform!\n");
1122 goto res_create_fail;
1123 }
1124
1125 pool->base.opps[j] = dce120_opp_create(
1126 ctx,
1127 i);
1128 if (pool->base.opps[j] == NULL) {
1129 BREAK_TO_DEBUGGER();
1130 dm_error(
1131 "DC: failed to create output pixel processor!\n");
1132 }
1133
1134
1135 j++;
1136 }
1137
1138 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1139 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1140 if (pool->base.engines[i] == NULL) {
1141 BREAK_TO_DEBUGGER();
1142 dm_error(
1143 "DC:failed to create aux engine!!\n");
1144 goto res_create_fail;
1145 }
1146 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1147 if (pool->base.hw_i2cs[i] == NULL) {
1148 BREAK_TO_DEBUGGER();
1149 dm_error(
1150 "DC:failed to create i2c engine!!\n");
1151 goto res_create_fail;
1152 }
1153 pool->base.sw_i2cs[i] = NULL;
1154 }
1155
1156
1157 pool->base.pipe_count = j;
1158 pool->base.timing_generator_count = j;
1159
1160 if (is_vg20)
1161 res_funcs = &dce121_res_create_funcs;
1162 else
1163 res_funcs = &res_create_funcs;
1164
1165 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1166 goto res_create_fail;
1167
1168
1169 if (!dce120_hw_sequencer_create(dc))
1170 goto controller_create_fail;
1171
1172 dc->caps.max_planes = pool->base.pipe_count;
1173
1174 for (i = 0; i < dc->caps.max_planes; ++i)
1175 dc->caps.planes[i] = plane_cap;
1176
1177 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1178
1179 bw_calcs_data_update_from_pplib(dc);
1180
1181 return true;
1182
1183irqs_create_fail:
1184controller_create_fail:
1185clk_src_create_fail:
1186res_create_fail:
1187
1188 destruct(pool);
1189
1190 return false;
1191}
1192
1193struct resource_pool *dce120_create_resource_pool(
1194 uint8_t num_virtual_links,
1195 struct dc *dc)
1196{
1197 struct dce110_resource_pool *pool =
1198 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1199
1200 if (!pool)
1201 return NULL;
1202
1203 if (construct(num_virtual_links, dc, pool))
1204 return &pool->base;
1205
1206 BREAK_TO_DEBUGGER();
1207 return NULL;
1208}
1209