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26#include <linux/delay.h>
27
28#include "dc_bios_types.h"
29#include "dcn10_stream_encoder.h"
30#include "reg_helper.h"
31#include "hw_shared.h"
32
33#define DC_LOGGER \
34 enc1->base.ctx->logger
35
36
37#define REG(reg)\
38 (enc1->regs->reg)
39
40#undef FN
41#define FN(reg_name, field_name) \
42 enc1->se_shift->field_name, enc1->se_mask->field_name
43
44#define VBI_LINE_0 0
45#define DP_BLANK_MAX_RETRY 20
46#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48
49enum {
50 DP_MST_UPDATE_MAX_RETRY = 50
51};
52
53#define CTX \
54 enc1->base.ctx
55
56void enc1_update_generic_info_packet(
57 struct dcn10_stream_encoder *enc1,
58 uint32_t packet_index,
59 const struct dc_info_packet *info_packet)
60{
61 uint32_t regval;
62
63
64
65 uint32_t max_retries = 50;
66
67
68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
69
70 if (packet_index >= 8)
71 ASSERT(0);
72
73
74
75
76
77
78
79
80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
81 0, 10, max_retries);
82
83
84
85
86
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
88
89
90 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
91 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
92 AFMT_GENERIC_INDEX, packet_index);
93
94
95
96
97 REG_SET_4(AFMT_GENERIC_HDR, 0,
98 AFMT_GENERIC_HB0, info_packet->hb0,
99 AFMT_GENERIC_HB1, info_packet->hb1,
100 AFMT_GENERIC_HB2, info_packet->hb2,
101 AFMT_GENERIC_HB3, info_packet->hb3);
102
103
104
105
106
107 {
108 const uint32_t *content =
109 (const uint32_t *) &info_packet->sb[0];
110
111 REG_WRITE(AFMT_GENERIC_0, *content++);
112 REG_WRITE(AFMT_GENERIC_1, *content++);
113 REG_WRITE(AFMT_GENERIC_2, *content++);
114 REG_WRITE(AFMT_GENERIC_3, *content++);
115 REG_WRITE(AFMT_GENERIC_4, *content++);
116 REG_WRITE(AFMT_GENERIC_5, *content++);
117 REG_WRITE(AFMT_GENERIC_6, *content++);
118 REG_WRITE(AFMT_GENERIC_7, *content);
119 }
120
121 switch (packet_index) {
122 case 0:
123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
124 AFMT_GENERIC0_FRAME_UPDATE, 1);
125 break;
126 case 1:
127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
128 AFMT_GENERIC1_FRAME_UPDATE, 1);
129 break;
130 case 2:
131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
132 AFMT_GENERIC2_FRAME_UPDATE, 1);
133 break;
134 case 3:
135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
136 AFMT_GENERIC3_FRAME_UPDATE, 1);
137 break;
138 case 4:
139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
140 AFMT_GENERIC4_FRAME_UPDATE, 1);
141 break;
142 case 5:
143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
144 AFMT_GENERIC5_FRAME_UPDATE, 1);
145 break;
146 case 6:
147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
148 AFMT_GENERIC6_FRAME_UPDATE, 1);
149 break;
150 case 7:
151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
152 AFMT_GENERIC7_FRAME_UPDATE, 1);
153 break;
154 default:
155 break;
156 }
157}
158
159static void enc1_update_hdmi_info_packet(
160 struct dcn10_stream_encoder *enc1,
161 uint32_t packet_index,
162 const struct dc_info_packet *info_packet)
163{
164 uint32_t cont, send, line;
165
166 if (info_packet->valid) {
167 enc1_update_generic_info_packet(
168 enc1,
169 packet_index,
170 info_packet);
171
172
173
174
175 cont = 1;
176
177 send = 1;
178
179 line = 2;
180 } else {
181 cont = 0;
182 send = 0;
183 line = 0;
184 }
185
186
187 switch (packet_index) {
188 case 0:
189 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
190 HDMI_GENERIC0_CONT, cont,
191 HDMI_GENERIC0_SEND, send,
192 HDMI_GENERIC0_LINE, line);
193 break;
194 case 1:
195 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
196 HDMI_GENERIC1_CONT, cont,
197 HDMI_GENERIC1_SEND, send,
198 HDMI_GENERIC1_LINE, line);
199 break;
200 case 2:
201 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
202 HDMI_GENERIC0_CONT, cont,
203 HDMI_GENERIC0_SEND, send,
204 HDMI_GENERIC0_LINE, line);
205 break;
206 case 3:
207 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
208 HDMI_GENERIC1_CONT, cont,
209 HDMI_GENERIC1_SEND, send,
210 HDMI_GENERIC1_LINE, line);
211 break;
212 case 4:
213 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
214 HDMI_GENERIC0_CONT, cont,
215 HDMI_GENERIC0_SEND, send,
216 HDMI_GENERIC0_LINE, line);
217 break;
218 case 5:
219 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
220 HDMI_GENERIC1_CONT, cont,
221 HDMI_GENERIC1_SEND, send,
222 HDMI_GENERIC1_LINE, line);
223 break;
224 case 6:
225 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
226 HDMI_GENERIC0_CONT, cont,
227 HDMI_GENERIC0_SEND, send,
228 HDMI_GENERIC0_LINE, line);
229 break;
230 case 7:
231 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
232 HDMI_GENERIC1_CONT, cont,
233 HDMI_GENERIC1_SEND, send,
234 HDMI_GENERIC1_LINE, line);
235 break;
236 default:
237
238 DC_LOG_WARNING(
239 "Invalid HW packet index: %s()\n",
240 __func__);
241 return;
242 }
243}
244
245
246void enc1_stream_encoder_dp_set_stream_attribute(
247 struct stream_encoder *enc,
248 struct dc_crtc_timing *crtc_timing,
249 enum dc_color_space output_color_space,
250 uint32_t enable_sdp_splitting)
251{
252 uint32_t h_active_start;
253 uint32_t v_active_start;
254 uint32_t misc0 = 0;
255 uint32_t misc1 = 0;
256 uint32_t h_blank;
257 uint32_t h_back_porch;
258 uint8_t synchronous_clock = 0;
259 uint8_t colorimetry_bpc;
260 uint8_t dynamic_range_rgb = 0;
261 uint8_t dynamic_range_ycbcr = 1;
262 uint8_t dp_pixel_encoding = 0;
263 uint8_t dp_component_depth = 0;
264
265 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
266 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
267
268 if (hw_crtc_timing.flags.INTERLACE) {
269
270 hw_crtc_timing.v_total /= 2;
271 hw_crtc_timing.v_border_top /= 2;
272 hw_crtc_timing.v_addressable /= 2;
273 hw_crtc_timing.v_border_bottom /= 2;
274 hw_crtc_timing.v_front_porch /= 2;
275 hw_crtc_timing.v_sync_width /= 2;
276 }
277
278
279
280 switch (hw_crtc_timing.pixel_encoding) {
281 case PIXEL_ENCODING_YCBCR422:
282 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
283 break;
284 case PIXEL_ENCODING_YCBCR444:
285 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
286
287 if (hw_crtc_timing.flags.Y_ONLY)
288 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
289
290
291
292
293 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
294
295
296
297
298
299
300 break;
301 case PIXEL_ENCODING_YCBCR420:
302 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
303 break;
304 default:
305 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
306 break;
307 }
308
309 misc1 = REG_READ(DP_MSA_MISC);
310
311
312
313
314
315 if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
316 (output_color_space == COLOR_SPACE_2020_YCBCR) ||
317 (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
318 (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
319 misc1 = misc1 | 0x40;
320 else
321 misc1 = misc1 & ~0x40;
322
323
324 switch (hw_crtc_timing.display_color_depth) {
325 case COLOR_DEPTH_666:
326 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
327 break;
328 case COLOR_DEPTH_888:
329 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
330 break;
331 case COLOR_DEPTH_101010:
332 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
333 break;
334 case COLOR_DEPTH_121212:
335 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
336 break;
337 case COLOR_DEPTH_161616:
338 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
339 break;
340 default:
341 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
342 break;
343 }
344
345
346 REG_UPDATE_2(DP_PIXEL_FORMAT,
347 DP_PIXEL_ENCODING, dp_pixel_encoding,
348 DP_COMPONENT_DEPTH, dp_component_depth);
349
350
351
352 switch (hw_crtc_timing.display_color_depth) {
353 case COLOR_DEPTH_666:
354 colorimetry_bpc = 0;
355 break;
356 case COLOR_DEPTH_888:
357 colorimetry_bpc = 1;
358 break;
359 case COLOR_DEPTH_101010:
360 colorimetry_bpc = 2;
361 break;
362 case COLOR_DEPTH_121212:
363 colorimetry_bpc = 3;
364 break;
365 default:
366 colorimetry_bpc = 0;
367 break;
368 }
369
370 misc0 = misc0 | synchronous_clock;
371 misc0 = colorimetry_bpc << 5;
372
373 switch (output_color_space) {
374 case COLOR_SPACE_SRGB:
375 misc1 = misc1 & ~0x80;
376 dynamic_range_rgb = 0;
377 break;
378 case COLOR_SPACE_SRGB_LIMITED:
379 misc0 = misc0 | 0x8;
380 misc1 = misc1 & ~0x80;
381 dynamic_range_rgb = 1;
382 break;
383 case COLOR_SPACE_YCBCR601:
384 case COLOR_SPACE_YCBCR601_LIMITED:
385 misc0 = misc0 | 0x8;
386 misc1 = misc1 & ~0x80;
387 dynamic_range_ycbcr = 0;
388 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
389 misc0 = misc0 | 0x2;
390 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
391 misc0 = misc0 | 0x4;
392 break;
393 case COLOR_SPACE_YCBCR709:
394 case COLOR_SPACE_YCBCR709_LIMITED:
395 misc0 = misc0 | 0x18;
396 misc1 = misc1 & ~0x80;
397 dynamic_range_ycbcr = 1;
398 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
399 misc0 = misc0 | 0x2;
400 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
401 misc0 = misc0 | 0x4;
402 break;
403 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
404 dynamic_range_rgb = 1;
405 break;
406 case COLOR_SPACE_2020_RGB_FULLRANGE:
407 case COLOR_SPACE_2020_YCBCR:
408 case COLOR_SPACE_XR_RGB:
409 case COLOR_SPACE_MSREF_SCRGB:
410 case COLOR_SPACE_ADOBERGB:
411 case COLOR_SPACE_DCIP3:
412 case COLOR_SPACE_XV_YCC_709:
413 case COLOR_SPACE_XV_YCC_601:
414 case COLOR_SPACE_DISPLAYNATIVE:
415 case COLOR_SPACE_DOLBYVISION:
416 case COLOR_SPACE_APPCTRL:
417 case COLOR_SPACE_CUSTOMPOINTS:
418 case COLOR_SPACE_UNKNOWN:
419 case COLOR_SPACE_YCBCR709_BLACK:
420
421 break;
422 }
423
424 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
425 REG_WRITE(DP_MSA_MISC, misc1);
426
427
428
429
430 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
431 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
432 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
433
434
435
436
437
438 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
439 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
440
441 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
442 hw_crtc_timing.h_sync_width;
443
444
445 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
446
447
448 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
449 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
450 hw_crtc_timing.v_front_porch;
451
452
453
454 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
455 DP_MSA_HSTART, h_active_start,
456 DP_MSA_VSTART, v_active_start);
457
458 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
459 DP_MSA_HSYNCWIDTH,
460 hw_crtc_timing.h_sync_width,
461 DP_MSA_HSYNCPOLARITY,
462 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
463 DP_MSA_VSYNCWIDTH,
464 hw_crtc_timing.v_sync_width,
465 DP_MSA_VSYNCPOLARITY,
466 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
467
468
469 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
470 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
471 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
472 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
473 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
474}
475
476void enc1_stream_encoder_set_stream_attribute_helper(
477 struct dcn10_stream_encoder *enc1,
478 struct dc_crtc_timing *crtc_timing)
479{
480 switch (crtc_timing->pixel_encoding) {
481 case PIXEL_ENCODING_YCBCR422:
482 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
483 break;
484 default:
485 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
486 break;
487 }
488 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
489}
490
491
492void enc1_stream_encoder_hdmi_set_stream_attribute(
493 struct stream_encoder *enc,
494 struct dc_crtc_timing *crtc_timing,
495 int actual_pix_clk_khz,
496 bool enable_audio)
497{
498 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
499 struct bp_encoder_control cntl = {0};
500
501 cntl.action = ENCODER_CONTROL_SETUP;
502 cntl.engine_id = enc1->base.id;
503 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
504 cntl.enable_dp_audio = enable_audio;
505 cntl.pixel_clock = actual_pix_clk_khz;
506 cntl.lanes_number = LANE_COUNT_FOUR;
507
508 if (enc1->base.bp->funcs->encoder_control(
509 enc1->base.bp, &cntl) != BP_RESULT_OK)
510 return;
511
512 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
513
514
515 REG_UPDATE_5(HDMI_CONTROL,
516 HDMI_PACKET_GEN_VERSION, 1,
517 HDMI_KEEPOUT_MODE, 1,
518 HDMI_DEEP_COLOR_ENABLE, 0,
519 HDMI_DATA_SCRAMBLE_EN, 0,
520 HDMI_CLOCK_CHANNEL_RATE, 0);
521
522
523 switch (crtc_timing->display_color_depth) {
524 case COLOR_DEPTH_888:
525 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
526 break;
527 case COLOR_DEPTH_101010:
528 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
529 REG_UPDATE_2(HDMI_CONTROL,
530 HDMI_DEEP_COLOR_DEPTH, 1,
531 HDMI_DEEP_COLOR_ENABLE, 0);
532 } else {
533 REG_UPDATE_2(HDMI_CONTROL,
534 HDMI_DEEP_COLOR_DEPTH, 1,
535 HDMI_DEEP_COLOR_ENABLE, 1);
536 }
537 break;
538 case COLOR_DEPTH_121212:
539 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
540 REG_UPDATE_2(HDMI_CONTROL,
541 HDMI_DEEP_COLOR_DEPTH, 2,
542 HDMI_DEEP_COLOR_ENABLE, 0);
543 } else {
544 REG_UPDATE_2(HDMI_CONTROL,
545 HDMI_DEEP_COLOR_DEPTH, 2,
546 HDMI_DEEP_COLOR_ENABLE, 1);
547 }
548 break;
549 case COLOR_DEPTH_161616:
550 REG_UPDATE_2(HDMI_CONTROL,
551 HDMI_DEEP_COLOR_DEPTH, 3,
552 HDMI_DEEP_COLOR_ENABLE, 1);
553 break;
554 default:
555 break;
556 }
557
558 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
559
560
561
562
563 REG_UPDATE_2(HDMI_CONTROL,
564 HDMI_DATA_SCRAMBLE_EN, 1,
565 HDMI_CLOCK_CHANNEL_RATE, 1);
566 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
567
568
569
570
571
572
573
574
575 REG_UPDATE_2(HDMI_CONTROL,
576 HDMI_DATA_SCRAMBLE_EN, 1,
577 HDMI_CLOCK_CHANNEL_RATE, 0);
578 }
579
580
581 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
582 HDMI_GC_CONT, 1,
583 HDMI_GC_SEND, 1,
584 HDMI_NULL_SEND, 1);
585
586
587 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
588
589 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
590
591 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
592 VBI_LINE_0 + 2);
593
594 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
595}
596
597
598void enc1_stream_encoder_dvi_set_stream_attribute(
599 struct stream_encoder *enc,
600 struct dc_crtc_timing *crtc_timing,
601 bool is_dual_link)
602{
603 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
604 struct bp_encoder_control cntl = {0};
605
606 cntl.action = ENCODER_CONTROL_SETUP;
607 cntl.engine_id = enc1->base.id;
608 cntl.signal = is_dual_link ?
609 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
610 cntl.enable_dp_audio = false;
611 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
612 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
613
614 if (enc1->base.bp->funcs->encoder_control(
615 enc1->base.bp, &cntl) != BP_RESULT_OK)
616 return;
617
618 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
619 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
620 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
621}
622
623void enc1_stream_encoder_set_mst_bandwidth(
624 struct stream_encoder *enc,
625 struct fixed31_32 avg_time_slots_per_mtp)
626{
627 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
628 uint32_t x = dc_fixpt_floor(
629 avg_time_slots_per_mtp);
630 uint32_t y = dc_fixpt_ceil(
631 dc_fixpt_shl(
632 dc_fixpt_sub_int(
633 avg_time_slots_per_mtp,
634 x),
635 26));
636
637 REG_SET_2(DP_MSE_RATE_CNTL, 0,
638 DP_MSE_RATE_X, x,
639 DP_MSE_RATE_Y, y);
640
641
642
643
644 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
645 0,
646 10, DP_MST_UPDATE_MAX_RETRY);
647}
648
649static void enc1_stream_encoder_update_hdmi_info_packets(
650 struct stream_encoder *enc,
651 const struct encoder_info_frame *info_frame)
652{
653 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
654
655
656 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
657
658 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
659 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
660 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
661 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
662 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
663}
664
665static void enc1_stream_encoder_stop_hdmi_info_packets(
666 struct stream_encoder *enc)
667{
668 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
669
670
671 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
672 HDMI_GENERIC1_CONT, 0,
673 HDMI_GENERIC1_LINE, 0,
674 HDMI_GENERIC1_SEND, 0,
675 HDMI_GENERIC0_CONT, 0,
676 HDMI_GENERIC0_LINE, 0,
677 HDMI_GENERIC0_SEND, 0);
678
679
680 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
681 HDMI_GENERIC0_CONT, 0,
682 HDMI_GENERIC0_LINE, 0,
683 HDMI_GENERIC0_SEND, 0,
684 HDMI_GENERIC1_CONT, 0,
685 HDMI_GENERIC1_LINE, 0,
686 HDMI_GENERIC1_SEND, 0);
687
688
689 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
690 HDMI_GENERIC0_CONT, 0,
691 HDMI_GENERIC0_LINE, 0,
692 HDMI_GENERIC0_SEND, 0,
693 HDMI_GENERIC1_CONT, 0,
694 HDMI_GENERIC1_LINE, 0,
695 HDMI_GENERIC1_SEND, 0);
696
697 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
698 HDMI_GENERIC0_CONT, 0,
699 HDMI_GENERIC0_LINE, 0,
700 HDMI_GENERIC0_SEND, 0,
701 HDMI_GENERIC1_CONT, 0,
702 HDMI_GENERIC1_LINE, 0,
703 HDMI_GENERIC1_SEND, 0);
704}
705
706void enc1_stream_encoder_update_dp_info_packets(
707 struct stream_encoder *enc,
708 const struct encoder_info_frame *info_frame)
709{
710 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
711 uint32_t value = 0;
712
713 if (info_frame->vsc.valid)
714 enc1_update_generic_info_packet(
715 enc1,
716 0,
717 &info_frame->vsc);
718
719 if (info_frame->spd.valid)
720 enc1_update_generic_info_packet(
721 enc1,
722 2,
723 &info_frame->spd);
724
725 if (info_frame->hdrsmd.valid)
726 enc1_update_generic_info_packet(
727 enc1,
728 3,
729 &info_frame->hdrsmd);
730
731
732
733
734
735
736
737
738 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
739 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
740 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
741
742
743
744
745
746
747
748
749
750 value = REG_READ(DP_SEC_CNTL);
751 if (value)
752 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
753}
754
755void enc1_stream_encoder_send_immediate_sdp_message(
756 struct stream_encoder *enc,
757 const uint8_t *custom_sdp_message,
758 unsigned int sdp_message_size)
759{
760 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
761 uint32_t value = 0;
762
763
764
765
766 uint32_t max_retries = 50;
767
768
769 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
770 0, 10, max_retries);
771
772
773 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
774
775
776 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
777
778
779 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
780
781
782 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
783 0, 10, max_retries);
784
785
786
787
788
789 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
790
791
792 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
793 AFMT_GENERIC_INDEX, 4);
794
795
796
797
798 REG_SET_4(AFMT_GENERIC_HDR, 0,
799 AFMT_GENERIC_HB0, custom_sdp_message[0],
800 AFMT_GENERIC_HB1, custom_sdp_message[1],
801 AFMT_GENERIC_HB2, custom_sdp_message[2],
802 AFMT_GENERIC_HB3, custom_sdp_message[3]);
803
804
805
806
807
808 {
809 const uint32_t *content =
810 (const uint32_t *) &custom_sdp_message[4];
811
812 REG_WRITE(AFMT_GENERIC_0, *content++);
813 REG_WRITE(AFMT_GENERIC_1, *content++);
814 REG_WRITE(AFMT_GENERIC_2, *content++);
815 REG_WRITE(AFMT_GENERIC_3, *content++);
816 REG_WRITE(AFMT_GENERIC_4, *content++);
817 REG_WRITE(AFMT_GENERIC_5, *content++);
818 REG_WRITE(AFMT_GENERIC_6, *content++);
819 REG_WRITE(AFMT_GENERIC_7, *content);
820 }
821
822
823
824
825 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
826 0, 10, max_retries);
827
828
829
830
831 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
832 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
833
834
835 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
836
837
838
839
840
841
842
843
844 value = REG_READ(DP_SEC_CNTL);
845 if (value)
846 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
847}
848
849void enc1_stream_encoder_stop_dp_info_packets(
850 struct stream_encoder *enc)
851{
852
853 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
854 uint32_t value = 0;
855
856 REG_SET_10(DP_SEC_CNTL, 0,
857 DP_SEC_GSP0_ENABLE, 0,
858 DP_SEC_GSP1_ENABLE, 0,
859 DP_SEC_GSP2_ENABLE, 0,
860 DP_SEC_GSP3_ENABLE, 0,
861 DP_SEC_GSP4_ENABLE, 0,
862 DP_SEC_GSP5_ENABLE, 0,
863 DP_SEC_GSP6_ENABLE, 0,
864 DP_SEC_GSP7_ENABLE, 0,
865 DP_SEC_MPG_ENABLE, 0,
866 DP_SEC_STREAM_ENABLE, 0);
867
868
869
870
871 value = REG_READ(DP_SEC_CNTL);
872 if (value)
873 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
874
875}
876
877void enc1_stream_encoder_dp_blank(
878 struct stream_encoder *enc)
879{
880 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
881 uint32_t reg1 = 0;
882 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
883
884
885
886
887
888
889
890
891 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
892 if ((reg1 & 0x1) == 0)
893
894 return;
895
896
897
898 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
899
900
901
902
903 max_retries = DP_BLANK_MAX_RETRY * 250;
904
905
906 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
907
908
909
910
911
912
913 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
914 0,
915 10, max_retries);
916
917
918
919
920
921
922
923 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
924}
925
926
927void enc1_stream_encoder_dp_unblank(
928 struct stream_encoder *enc,
929 const struct encoder_unblank_param *param)
930{
931 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
932
933 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
934 uint32_t n_vid = 0x8000;
935 uint32_t m_vid;
936 uint32_t n_multiply = 0;
937 uint64_t m_vid_l = n_vid;
938
939
940 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
941
942 n_multiply = 1;
943 }
944
945
946
947
948 m_vid_l *= param->timing.pix_clk_100hz / 10;
949 m_vid_l = div_u64(m_vid_l,
950 param->link_settings.link_rate
951 * LINK_RATE_REF_FREQ_IN_KHZ);
952
953 m_vid = (uint32_t) m_vid_l;
954
955
956
957 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
958
959
960
961
962
963 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
964
965 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
966
967 REG_UPDATE_2(DP_VID_TIMING,
968 DP_VID_M_N_GEN_EN, 1,
969 DP_VID_N_MUL, n_multiply);
970 }
971
972
973
974 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
975
976
977
978 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
979
980
981
982
983 udelay(100);
984
985
986
987
988
989
990
991
992
993 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
994}
995
996void enc1_stream_encoder_set_avmute(
997 struct stream_encoder *enc,
998 bool enable)
999{
1000 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1001 unsigned int value = enable ? 1 : 0;
1002
1003 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1004}
1005
1006
1007#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1008#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1009
1010#include "include/audio_types.h"
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
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1038
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1074
1075
1076
1077
1078
1079
1080
1081union audio_cea_channels {
1082 uint8_t all;
1083 struct audio_cea_channels_bits {
1084 uint32_t FL:1;
1085 uint32_t FR:1;
1086 uint32_t LFE:1;
1087 uint32_t FC:1;
1088 uint32_t RL_RC:1;
1089 uint32_t RR:1;
1090 uint32_t RC_RLC_FLC:1;
1091 uint32_t RRC_FRC:1;
1092 } channels;
1093};
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static const struct audio_clock_info audio_clock_info_table[16] = {
1109 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1110 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1111 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1112 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1113 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1114 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1115 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1116 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1117 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1118 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1119 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1120 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1121 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1122 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1123 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1124 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1125};
1126
1127static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1128 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1129 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1130 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1131 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1132 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1133 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1134 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1135 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1136 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1137 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1138 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1139 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1140 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1141 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1142};
1143
1144static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1145 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1146 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1147 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1148 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1149 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1150 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1151 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1152 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1153 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1154 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1155 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1156 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1157 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1158 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1159
1160
1161};
1162
1163static union audio_cea_channels speakers_to_channels(
1164 struct audio_speaker_flags speaker_flags)
1165{
1166 union audio_cea_channels cea_channels = {0};
1167
1168
1169 cea_channels.channels.FL = speaker_flags.FL_FR;
1170 cea_channels.channels.FR = speaker_flags.FL_FR;
1171 cea_channels.channels.LFE = speaker_flags.LFE;
1172 cea_channels.channels.FC = speaker_flags.FC;
1173
1174
1175
1176
1177 if (speaker_flags.RL_RR) {
1178 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1179 cea_channels.channels.RR = speaker_flags.RL_RR;
1180 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1181 } else {
1182 cea_channels.channels.RL_RC = speaker_flags.RC;
1183 }
1184
1185
1186 if (speaker_flags.FLC_FRC) {
1187 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1188 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1189 } else {
1190 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1191 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1192 }
1193
1194 return cea_channels;
1195}
1196
1197void get_audio_clock_info(
1198 enum dc_color_depth color_depth,
1199 uint32_t crtc_pixel_clock_in_khz,
1200 uint32_t actual_pixel_clock_in_khz,
1201 struct audio_clock_info *audio_clock_info)
1202{
1203 const struct audio_clock_info *clock_info;
1204 uint32_t index;
1205 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1206 uint32_t audio_array_size;
1207
1208 switch (color_depth) {
1209 case COLOR_DEPTH_161616:
1210 clock_info = audio_clock_info_table_48bpc;
1211 audio_array_size = ARRAY_SIZE(
1212 audio_clock_info_table_48bpc);
1213 break;
1214 case COLOR_DEPTH_121212:
1215 clock_info = audio_clock_info_table_36bpc;
1216 audio_array_size = ARRAY_SIZE(
1217 audio_clock_info_table_36bpc);
1218 break;
1219 default:
1220 clock_info = audio_clock_info_table;
1221 audio_array_size = ARRAY_SIZE(
1222 audio_clock_info_table);
1223 break;
1224 }
1225
1226 if (clock_info != NULL) {
1227
1228 for (index = 0; index < audio_array_size; index++) {
1229 if (clock_info[index].pixel_clock_in_10khz >
1230 crtc_pixel_clock_in_10khz)
1231 break;
1232 else if (clock_info[index].pixel_clock_in_10khz ==
1233 crtc_pixel_clock_in_10khz) {
1234
1235 *audio_clock_info = clock_info[index];
1236 return;
1237 }
1238 }
1239 }
1240
1241
1242 if (actual_pixel_clock_in_khz == 0)
1243 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1244
1245
1246
1247 audio_clock_info->pixel_clock_in_10khz =
1248 actual_pixel_clock_in_khz / 10;
1249 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1250 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1251 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1252
1253 audio_clock_info->n_32khz = 4096;
1254 audio_clock_info->n_44khz = 6272;
1255 audio_clock_info->n_48khz = 6144;
1256}
1257
1258static void enc1_se_audio_setup(
1259 struct stream_encoder *enc,
1260 unsigned int az_inst,
1261 struct audio_info *audio_info)
1262{
1263 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1264
1265 uint32_t speakers = 0;
1266 uint32_t channels = 0;
1267
1268 ASSERT(audio_info);
1269 if (audio_info == NULL)
1270
1271 return;
1272
1273 speakers = audio_info->flags.info.ALLSPEAKERS;
1274 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1275
1276
1277 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1278
1279
1280 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1281}
1282
1283static void enc1_se_setup_hdmi_audio(
1284 struct stream_encoder *enc,
1285 const struct audio_crtc_info *crtc_info)
1286{
1287 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1288
1289 struct audio_clock_info audio_clock_info = {0};
1290
1291
1292 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1293 HDMI_AUDIO_DELAY_EN, 1);
1294
1295
1296 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1297
1298
1299 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1300 AFMT_AUDIO_LAYOUT_OVRD, 0,
1301 AFMT_60958_OSF_OVRD, 0);
1302
1303
1304 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1305 HDMI_ACR_AUTO_SEND, 1,
1306 HDMI_ACR_SOURCE, 0,
1307 HDMI_ACR_AUDIO_PRIORITY, 0);
1308
1309
1310 get_audio_clock_info(crtc_info->color_depth,
1311 crtc_info->requested_pixel_clock,
1312 crtc_info->calculated_pixel_clock,
1313 &audio_clock_info);
1314 DC_LOG_HW_AUDIO(
1315 "\n%s:Input::requested_pixel_clock = %d" \
1316 "calculated_pixel_clock = %d \n", __func__, \
1317 crtc_info->requested_pixel_clock, \
1318 crtc_info->calculated_pixel_clock);
1319
1320
1321 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1322
1323
1324 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1325
1326
1327 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1328
1329
1330 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1331
1332
1333 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1334
1335
1336 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347 REG_UPDATE_2(AFMT_60958_0,
1348 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1349 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1350
1351
1352 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1353
1354
1355
1356
1357 REG_UPDATE_6(AFMT_60958_2,
1358 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1359 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1360 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1361 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1362 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1363 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1364}
1365
1366static void enc1_se_setup_dp_audio(
1367 struct stream_encoder *enc)
1368{
1369 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1370
1371
1372
1373
1374 REG_SET(DP_SEC_AUD_N, 0,
1375 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1376
1377
1378 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1379 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1380
1381
1382
1383
1384
1385
1386 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1387
1388
1389
1390 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1391 AFMT_AUDIO_LAYOUT_OVRD, 0,
1392 AFMT_60958_OSF_OVRD, 0);
1393
1394
1395 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1396
1397
1398 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1399}
1400
1401void enc1_se_enable_audio_clock(
1402 struct stream_encoder *enc,
1403 bool enable)
1404{
1405 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1406
1407 if (REG(AFMT_CNTL) == 0)
1408 return;
1409
1410 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421}
1422
1423void enc1_se_enable_dp_audio(
1424 struct stream_encoder *enc)
1425{
1426 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1427
1428
1429 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1430
1431
1432 REG_UPDATE_2(DP_SEC_CNTL,
1433 DP_SEC_ATP_ENABLE, 1,
1434 DP_SEC_AIP_ENABLE, 1);
1435
1436
1437 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1438}
1439
1440static void enc1_se_disable_dp_audio(
1441 struct stream_encoder *enc)
1442{
1443 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1444 uint32_t value = 0;
1445
1446
1447 REG_UPDATE_5(DP_SEC_CNTL,
1448 DP_SEC_ASP_ENABLE, 0,
1449 DP_SEC_ATP_ENABLE, 0,
1450 DP_SEC_AIP_ENABLE, 0,
1451 DP_SEC_ACM_ENABLE, 0,
1452 DP_SEC_STREAM_ENABLE, 0);
1453
1454
1455
1456
1457 value = REG_READ(DP_SEC_CNTL);
1458 if (value != 0)
1459 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1460
1461}
1462
1463void enc1_se_audio_mute_control(
1464 struct stream_encoder *enc,
1465 bool mute)
1466{
1467 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1468
1469 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1470}
1471
1472void enc1_se_dp_audio_setup(
1473 struct stream_encoder *enc,
1474 unsigned int az_inst,
1475 struct audio_info *info)
1476{
1477 enc1_se_audio_setup(enc, az_inst, info);
1478}
1479
1480void enc1_se_dp_audio_enable(
1481 struct stream_encoder *enc)
1482{
1483 enc1_se_enable_audio_clock(enc, true);
1484 enc1_se_setup_dp_audio(enc);
1485 enc1_se_enable_dp_audio(enc);
1486}
1487
1488void enc1_se_dp_audio_disable(
1489 struct stream_encoder *enc)
1490{
1491 enc1_se_disable_dp_audio(enc);
1492 enc1_se_enable_audio_clock(enc, false);
1493}
1494
1495void enc1_se_hdmi_audio_setup(
1496 struct stream_encoder *enc,
1497 unsigned int az_inst,
1498 struct audio_info *info,
1499 struct audio_crtc_info *audio_crtc_info)
1500{
1501 enc1_se_enable_audio_clock(enc, true);
1502 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1503 enc1_se_audio_setup(enc, az_inst, info);
1504}
1505
1506void enc1_se_hdmi_audio_disable(
1507 struct stream_encoder *enc)
1508{
1509 enc1_se_enable_audio_clock(enc, false);
1510}
1511
1512
1513void enc1_setup_stereo_sync(
1514 struct stream_encoder *enc,
1515 int tg_inst, bool enable)
1516{
1517 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1518 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1519 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1520}
1521
1522void enc1_dig_connect_to_otg(
1523 struct stream_encoder *enc,
1524 int tg_inst)
1525{
1526 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1527
1528 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1529}
1530
1531static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1532 .dp_set_stream_attribute =
1533 enc1_stream_encoder_dp_set_stream_attribute,
1534 .hdmi_set_stream_attribute =
1535 enc1_stream_encoder_hdmi_set_stream_attribute,
1536 .dvi_set_stream_attribute =
1537 enc1_stream_encoder_dvi_set_stream_attribute,
1538 .set_mst_bandwidth =
1539 enc1_stream_encoder_set_mst_bandwidth,
1540 .update_hdmi_info_packets =
1541 enc1_stream_encoder_update_hdmi_info_packets,
1542 .stop_hdmi_info_packets =
1543 enc1_stream_encoder_stop_hdmi_info_packets,
1544 .update_dp_info_packets =
1545 enc1_stream_encoder_update_dp_info_packets,
1546 .send_immediate_sdp_message =
1547 enc1_stream_encoder_send_immediate_sdp_message,
1548 .stop_dp_info_packets =
1549 enc1_stream_encoder_stop_dp_info_packets,
1550 .dp_blank =
1551 enc1_stream_encoder_dp_blank,
1552 .dp_unblank =
1553 enc1_stream_encoder_dp_unblank,
1554 .audio_mute_control = enc1_se_audio_mute_control,
1555
1556 .dp_audio_setup = enc1_se_dp_audio_setup,
1557 .dp_audio_enable = enc1_se_dp_audio_enable,
1558 .dp_audio_disable = enc1_se_dp_audio_disable,
1559
1560 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1561 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1562 .setup_stereo_sync = enc1_setup_stereo_sync,
1563 .set_avmute = enc1_stream_encoder_set_avmute,
1564 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1565};
1566
1567void dcn10_stream_encoder_construct(
1568 struct dcn10_stream_encoder *enc1,
1569 struct dc_context *ctx,
1570 struct dc_bios *bp,
1571 enum engine_id eng_id,
1572 const struct dcn10_stream_enc_registers *regs,
1573 const struct dcn10_stream_encoder_shift *se_shift,
1574 const struct dcn10_stream_encoder_mask *se_mask)
1575{
1576 enc1->base.funcs = &dcn10_str_enc_funcs;
1577 enc1->base.ctx = ctx;
1578 enc1->base.id = eng_id;
1579 enc1->base.bp = bp;
1580 enc1->regs = regs;
1581 enc1->se_shift = se_shift;
1582 enc1->se_mask = se_mask;
1583}
1584
1585