1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25#ifndef __DISPLAY_MODE_STRUCTS_H__ 26#define __DISPLAY_MODE_STRUCTS_H__ 27 28#define MAX_CLOCK_LIMIT_STATES 8 29 30typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 31typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 32typedef struct _vcs_dpi_ip_params_st ip_params_st; 33typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 34typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 35typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 36typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 37typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 38typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 39typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 40typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 41typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 42typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 43typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 44typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 45typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 46typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 47typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 48typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 49typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 50typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 51typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 52typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 53typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 54 55struct _vcs_dpi_voltage_scaling_st { 56 int state; 57 double dscclk_mhz; 58 double dcfclk_mhz; 59 double socclk_mhz; 60 double phyclk_d18_mhz; 61 double dram_speed_mts; 62 double fabricclk_mhz; 63 double dispclk_mhz; 64 double phyclk_mhz; 65 double dppclk_mhz; 66}; 67 68struct _vcs_dpi_soc_bounding_box_st { 69 double sr_exit_time_us; 70 double sr_enter_plus_exit_time_us; 71 double urgent_latency_us; 72 double urgent_latency_pixel_data_only_us; 73 double urgent_latency_pixel_mixed_with_vm_data_us; 74 double urgent_latency_vm_data_only_us; 75 double writeback_latency_us; 76 double ideal_dram_bw_after_urgent_percent; 77 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 78 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 79 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 80 double max_avg_sdp_bw_use_normal_percent; 81 double max_avg_dram_bw_use_normal_percent; 82 unsigned int max_request_size_bytes; 83 double downspread_percent; 84 double dram_page_open_time_ns; 85 double dram_rw_turnaround_time_ns; 86 double dram_return_buffer_per_channel_bytes; 87 double dram_channel_width_bytes; 88 double fabric_datapath_to_dcn_data_return_bytes; 89 double dcn_downspread_percent; 90 double dispclk_dppclk_vco_speed_mhz; 91 double dfs_vco_period_ps; 92 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 93 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 94 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 95 unsigned int round_trip_ping_latency_dcfclk_cycles; 96 unsigned int urgent_out_of_order_return_per_channel_bytes; 97 unsigned int channel_interleave_bytes; 98 unsigned int num_banks; 99 unsigned int num_chans; 100 unsigned int vmm_page_size_bytes; 101 unsigned int hostvm_min_page_size_bytes; 102 double dram_clock_change_latency_us; 103 double writeback_dram_clock_change_latency_us; 104 unsigned int return_bus_width_bytes; 105 unsigned int voltage_override; 106 double xfc_bus_transport_time_us; 107 double xfc_xbuf_latency_tolerance_us; 108 int use_urgent_burst_bw; 109 unsigned int num_states; 110 struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; 111}; 112 113struct _vcs_dpi_ip_params_st { 114 bool gpuvm_enable; 115 bool hostvm_enable; 116 unsigned int gpuvm_max_page_table_levels; 117 unsigned int hostvm_max_page_table_levels; 118 unsigned int hostvm_cached_page_table_levels; 119 unsigned int pte_group_size_bytes; 120 unsigned int max_inter_dcn_tile_repeaters; 121 unsigned int num_dsc; 122 unsigned int odm_capable; 123 unsigned int rob_buffer_size_kbytes; 124 unsigned int det_buffer_size_kbytes; 125 unsigned int dpte_buffer_size_in_pte_reqs_luma; 126 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 127 unsigned int pde_proc_buffer_size_64k_reqs; 128 unsigned int dpp_output_buffer_pixels; 129 unsigned int opp_output_buffer_lines; 130 unsigned int pixel_chunk_size_kbytes; 131 unsigned char pte_enable; 132 unsigned int pte_chunk_size_kbytes; 133 unsigned int meta_chunk_size_kbytes; 134 unsigned int writeback_chunk_size_kbytes; 135 unsigned int line_buffer_size_bits; 136 unsigned int max_line_buffer_lines; 137 unsigned int writeback_luma_buffer_size_kbytes; 138 unsigned int writeback_chroma_buffer_size_kbytes; 139 unsigned int writeback_chroma_line_buffer_width_pixels; 140 141 unsigned int writeback_interface_buffer_size_kbytes; 142 unsigned int writeback_line_buffer_buffer_size; 143 144#ifdef CONFIG_DRM_AMD_DC_DCN2_0 145 unsigned int writeback_10bpc420_supported; 146 double writeback_max_hscl_ratio; 147 double writeback_max_vscl_ratio; 148 double writeback_min_hscl_ratio; 149 double writeback_min_vscl_ratio; 150 unsigned int writeback_max_hscl_taps; 151 unsigned int writeback_max_vscl_taps; 152 unsigned int writeback_line_buffer_luma_buffer_size; 153 unsigned int writeback_line_buffer_chroma_buffer_size; 154#endif 155 156 unsigned int max_page_table_levels; 157 unsigned int max_num_dpp; 158 unsigned int max_num_otg; 159 unsigned int cursor_chunk_size; 160 unsigned int cursor_buffer_size; 161 unsigned int max_num_wb; 162 unsigned int max_dchub_pscl_bw_pix_per_clk; 163 unsigned int max_pscl_lb_bw_pix_per_clk; 164 unsigned int max_lb_vscl_bw_pix_per_clk; 165 unsigned int max_vscl_hscl_bw_pix_per_clk; 166 double max_hscl_ratio; 167 double max_vscl_ratio; 168 unsigned int hscl_mults; 169 unsigned int vscl_mults; 170 unsigned int max_hscl_taps; 171 unsigned int max_vscl_taps; 172 unsigned int xfc_supported; 173 unsigned int ptoi_supported; 174 unsigned int gfx7_compat_tiling_supported; 175 176 bool odm_combine_4to1_supported; 177 bool dynamic_metadata_vm_enabled; 178 unsigned int max_num_hdmi_frl_outputs; 179 180 unsigned int xfc_fill_constant_bytes; 181 double dispclk_ramp_margin_percent; 182 double xfc_fill_bw_overhead_percent; 183 double underscan_factor; 184 unsigned int min_vblank_lines; 185 unsigned int dppclk_delay_subtotal; 186 unsigned int dispclk_delay_subtotal; 187 unsigned int dcfclk_cstate_latency; 188 unsigned int dppclk_delay_scl; 189 unsigned int dppclk_delay_scl_lb_only; 190 unsigned int dppclk_delay_cnvc_formatter; 191 unsigned int dppclk_delay_cnvc_cursor; 192 unsigned int is_line_buffer_bpp_fixed; 193 unsigned int line_buffer_fixed_bpp; 194 unsigned int dcc_supported; 195 196 unsigned int IsLineBufferBppFixed; 197 unsigned int LineBufferFixedBpp; 198 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 199 unsigned int bug_forcing_LC_req_same_size_fixed; 200}; 201 202struct _vcs_dpi_display_xfc_params_st { 203 double xfc_tslv_vready_offset_us; 204 double xfc_tslv_vupdate_width_us; 205 double xfc_tslv_vupdate_offset_us; 206 int xfc_slv_chunk_size_bytes; 207}; 208 209struct _vcs_dpi_display_pipe_source_params_st { 210 int source_format; 211 unsigned char dcc; 212 unsigned int dcc_rate; 213 unsigned char dcc_use_global; 214 unsigned char vm; 215 bool gpuvm; // gpuvm enabled 216 bool hostvm; // hostvm enabled 217 bool gpuvm_levels_force_en; 218 unsigned int gpuvm_levels_force; 219 bool hostvm_levels_force_en; 220 unsigned int hostvm_levels_force; 221 int source_scan; 222 int sw_mode; 223 int macro_tile_size; 224 unsigned int viewport_width; 225 unsigned int viewport_height; 226 unsigned int viewport_y_y; 227 unsigned int viewport_y_c; 228 unsigned int viewport_width_c; 229 unsigned int viewport_height_c; 230 unsigned int data_pitch; 231 unsigned int data_pitch_c; 232 unsigned int meta_pitch; 233 unsigned int meta_pitch_c; 234 unsigned int cur0_src_width; 235 int cur0_bpp; 236 unsigned int cur1_src_width; 237 int cur1_bpp; 238 int num_cursors; 239 unsigned char is_hsplit; 240 unsigned char dynamic_metadata_enable; 241 unsigned int dynamic_metadata_lines_before_active; 242 unsigned int dynamic_metadata_xmit_bytes; 243 unsigned int hsplit_grp; 244 unsigned char xfc_enable; 245 unsigned char xfc_slave; 246 unsigned char immediate_flip; 247 struct _vcs_dpi_display_xfc_params_st xfc_params; 248 //for vstartuplines calculation freesync 249 unsigned char v_total_min; 250 unsigned char v_total_max; 251}; 252struct writeback_st { 253 int wb_src_height; 254 int wb_src_width; 255 int wb_dst_width; 256 int wb_dst_height; 257 int wb_pixel_format; 258 int wb_htaps_luma; 259 int wb_vtaps_luma; 260 int wb_htaps_chroma; 261 int wb_vtaps_chroma; 262 double wb_hratio; 263 double wb_vratio; 264}; 265 266struct _vcs_dpi_display_output_params_st { 267 int dp_lanes; 268 int output_bpp; 269 int dsc_enable; 270 int wb_enable; 271 int num_active_wb; 272 int output_bpc; 273 int output_type; 274 int output_format; 275 int dsc_slices; 276 struct writeback_st wb; 277}; 278 279struct _vcs_dpi_scaler_ratio_depth_st { 280 double hscl_ratio; 281 double vscl_ratio; 282 double hscl_ratio_c; 283 double vscl_ratio_c; 284 double vinit; 285 double vinit_c; 286 double vinit_bot; 287 double vinit_bot_c; 288 int lb_depth; 289 int scl_enable; 290}; 291 292struct _vcs_dpi_scaler_taps_st { 293 unsigned int htaps; 294 unsigned int vtaps; 295 unsigned int htaps_c; 296 unsigned int vtaps_c; 297}; 298 299struct _vcs_dpi_display_pipe_dest_params_st { 300 unsigned int recout_width; 301 unsigned int recout_height; 302 unsigned int full_recout_width; 303 unsigned int full_recout_height; 304 unsigned int hblank_start; 305 unsigned int hblank_end; 306 unsigned int vblank_start; 307 unsigned int vblank_end; 308 unsigned int htotal; 309 unsigned int vtotal; 310 unsigned int vactive; 311 unsigned int hactive; 312 unsigned int vstartup_start; 313 unsigned int vupdate_offset; 314 unsigned int vupdate_width; 315 unsigned int vready_offset; 316 unsigned char interlaced; 317 double pixel_rate_mhz; 318 unsigned char synchronized_vblank_all_planes; 319 unsigned char otg_inst; 320 unsigned char odm_combine; 321 unsigned char use_maximum_vstartup; 322 unsigned int vtotal_max; 323 unsigned int vtotal_min; 324}; 325 326struct _vcs_dpi_display_pipe_params_st { 327 display_pipe_source_params_st src; 328 display_pipe_dest_params_st dest; 329 scaler_ratio_depth_st scale_ratio_depth; 330 scaler_taps_st scale_taps; 331}; 332 333struct _vcs_dpi_display_clocks_and_cfg_st { 334 int voltage; 335 double dppclk_mhz; 336 double refclk_mhz; 337 double dispclk_mhz; 338 double dcfclk_mhz; 339 double socclk_mhz; 340}; 341 342struct _vcs_dpi_display_e2e_pipe_params_st { 343 display_pipe_params_st pipe; 344 display_output_params_st dout; 345 display_clocks_and_cfg_st clks_cfg; 346}; 347 348struct _vcs_dpi_display_data_rq_misc_params_st { 349 unsigned int full_swath_bytes; 350 unsigned int stored_swath_bytes; 351 unsigned int blk256_height; 352 unsigned int blk256_width; 353 unsigned int req_height; 354 unsigned int req_width; 355}; 356 357struct _vcs_dpi_display_data_rq_sizing_params_st { 358 unsigned int chunk_bytes; 359 unsigned int min_chunk_bytes; 360 unsigned int meta_chunk_bytes; 361 unsigned int min_meta_chunk_bytes; 362 unsigned int mpte_group_bytes; 363 unsigned int dpte_group_bytes; 364}; 365 366struct _vcs_dpi_display_data_rq_dlg_params_st { 367 unsigned int swath_width_ub; 368 unsigned int swath_height; 369 unsigned int req_per_swath_ub; 370 unsigned int meta_pte_bytes_per_frame_ub; 371 unsigned int dpte_req_per_row_ub; 372 unsigned int dpte_groups_per_row_ub; 373 unsigned int dpte_row_height; 374 unsigned int dpte_bytes_per_row_ub; 375 unsigned int meta_chunks_per_row_ub; 376 unsigned int meta_req_per_row_ub; 377 unsigned int meta_row_height; 378 unsigned int meta_bytes_per_row_ub; 379}; 380 381struct _vcs_dpi_display_rq_dlg_params_st { 382 display_data_rq_dlg_params_st rq_l; 383 display_data_rq_dlg_params_st rq_c; 384}; 385 386struct _vcs_dpi_display_rq_sizing_params_st { 387 display_data_rq_sizing_params_st rq_l; 388 display_data_rq_sizing_params_st rq_c; 389}; 390 391struct _vcs_dpi_display_rq_misc_params_st { 392 display_data_rq_misc_params_st rq_l; 393 display_data_rq_misc_params_st rq_c; 394}; 395 396struct _vcs_dpi_display_rq_params_st { 397 unsigned char yuv420; 398 unsigned char yuv420_10bpc; 399 display_rq_misc_params_st misc; 400 display_rq_sizing_params_st sizing; 401 display_rq_dlg_params_st dlg; 402}; 403 404struct _vcs_dpi_display_dlg_regs_st { 405 unsigned int refcyc_h_blank_end; 406 unsigned int dlg_vblank_end; 407 unsigned int min_dst_y_next_start; 408 unsigned int refcyc_per_htotal; 409 unsigned int refcyc_x_after_scaler; 410 unsigned int dst_y_after_scaler; 411 unsigned int dst_y_prefetch; 412 unsigned int dst_y_per_vm_vblank; 413 unsigned int dst_y_per_row_vblank; 414 unsigned int dst_y_per_vm_flip; 415 unsigned int dst_y_per_row_flip; 416 unsigned int ref_freq_to_pix_freq; 417 unsigned int vratio_prefetch; 418 unsigned int vratio_prefetch_c; 419 unsigned int refcyc_per_pte_group_vblank_l; 420 unsigned int refcyc_per_pte_group_vblank_c; 421 unsigned int refcyc_per_meta_chunk_vblank_l; 422 unsigned int refcyc_per_meta_chunk_vblank_c; 423 unsigned int refcyc_per_pte_group_flip_l; 424 unsigned int refcyc_per_pte_group_flip_c; 425 unsigned int refcyc_per_meta_chunk_flip_l; 426 unsigned int refcyc_per_meta_chunk_flip_c; 427 unsigned int dst_y_per_pte_row_nom_l; 428 unsigned int dst_y_per_pte_row_nom_c; 429 unsigned int refcyc_per_pte_group_nom_l; 430 unsigned int refcyc_per_pte_group_nom_c; 431 unsigned int dst_y_per_meta_row_nom_l; 432 unsigned int dst_y_per_meta_row_nom_c; 433 unsigned int refcyc_per_meta_chunk_nom_l; 434 unsigned int refcyc_per_meta_chunk_nom_c; 435 unsigned int refcyc_per_line_delivery_pre_l; 436 unsigned int refcyc_per_line_delivery_pre_c; 437 unsigned int refcyc_per_line_delivery_l; 438 unsigned int refcyc_per_line_delivery_c; 439 unsigned int chunk_hdl_adjust_cur0; 440 unsigned int chunk_hdl_adjust_cur1; 441 unsigned int vready_after_vcount0; 442 unsigned int dst_y_offset_cur0; 443 unsigned int dst_y_offset_cur1; 444 unsigned int xfc_reg_transfer_delay; 445 unsigned int xfc_reg_precharge_delay; 446 unsigned int xfc_reg_remote_surface_flip_latency; 447 unsigned int xfc_reg_prefetch_margin; 448 unsigned int dst_y_delta_drq_limit; 449 unsigned int refcyc_per_vm_group_vblank; 450 unsigned int refcyc_per_vm_group_flip; 451 unsigned int refcyc_per_vm_req_vblank; 452 unsigned int refcyc_per_vm_req_flip; 453 unsigned int refcyc_per_vm_dmdata; 454}; 455 456struct _vcs_dpi_display_ttu_regs_st { 457 unsigned int qos_level_low_wm; 458 unsigned int qos_level_high_wm; 459 unsigned int min_ttu_vblank; 460 unsigned int qos_level_flip; 461 unsigned int refcyc_per_req_delivery_l; 462 unsigned int refcyc_per_req_delivery_c; 463 unsigned int refcyc_per_req_delivery_cur0; 464 unsigned int refcyc_per_req_delivery_cur1; 465 unsigned int refcyc_per_req_delivery_pre_l; 466 unsigned int refcyc_per_req_delivery_pre_c; 467 unsigned int refcyc_per_req_delivery_pre_cur0; 468 unsigned int refcyc_per_req_delivery_pre_cur1; 469 unsigned int qos_level_fixed_l; 470 unsigned int qos_level_fixed_c; 471 unsigned int qos_level_fixed_cur0; 472 unsigned int qos_level_fixed_cur1; 473 unsigned int qos_ramp_disable_l; 474 unsigned int qos_ramp_disable_c; 475 unsigned int qos_ramp_disable_cur0; 476 unsigned int qos_ramp_disable_cur1; 477}; 478 479struct _vcs_dpi_display_data_rq_regs_st { 480 unsigned int chunk_size; 481 unsigned int min_chunk_size; 482 unsigned int meta_chunk_size; 483 unsigned int min_meta_chunk_size; 484 unsigned int dpte_group_size; 485 unsigned int mpte_group_size; 486 unsigned int swath_height; 487 unsigned int pte_row_height_linear; 488}; 489 490struct _vcs_dpi_display_rq_regs_st { 491 display_data_rq_regs_st rq_regs_l; 492 display_data_rq_regs_st rq_regs_c; 493 unsigned int drq_expansion_mode; 494 unsigned int prq_expansion_mode; 495 unsigned int mrq_expansion_mode; 496 unsigned int crq_expansion_mode; 497 unsigned int plane1_base_address; 498}; 499 500struct _vcs_dpi_display_dlg_sys_params_st { 501 double t_mclk_wm_us; 502 double t_urg_wm_us; 503 double t_sr_wm_us; 504 double t_extra_us; 505 double mem_trip_us; 506 double t_srx_delay_us; 507 double deepsleep_dcfclk_mhz; 508 double total_flip_bw; 509 unsigned int total_flip_bytes; 510}; 511 512struct _vcs_dpi_display_arb_params_st { 513 int max_req_outstanding; 514 int min_req_outstanding; 515 int sat_level_us; 516}; 517 518#endif /*__DISPLAY_MODE_STRUCTS_H__*/ 519