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26#ifndef __DAL_CLK_MGR_INTERNAL_H__
27#define __DAL_CLK_MGR_INTERNAL_H__
28
29#include "clk_mgr.h"
30#include "dc.h"
31
32
33
34
35
36#include "resource.h"
37
38
39
40enum dentist_base_divider_id {
41 DENTIST_BASE_DID_1 = 0x08,
42 DENTIST_BASE_DID_2 = 0x40,
43 DENTIST_BASE_DID_3 = 0x60,
44 DENTIST_BASE_DID_4 = 0x7e,
45 DENTIST_MAX_DID = 0x7f
46};
47
48
49enum dentist_divider_range {
50 DENTIST_DIVIDER_RANGE_1_START = 8,
51 DENTIST_DIVIDER_RANGE_1_STEP = 1,
52 DENTIST_DIVIDER_RANGE_2_START = 64,
53 DENTIST_DIVIDER_RANGE_2_STEP = 2,
54 DENTIST_DIVIDER_RANGE_3_START = 128,
55 DENTIST_DIVIDER_RANGE_3_STEP = 4,
56 DENTIST_DIVIDER_RANGE_4_START = 248,
57 DENTIST_DIVIDER_RANGE_4_STEP = 264,
58 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
59};
60
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65
66
67#define TO_CLK_MGR_INTERNAL(clk_mgr)\
68 container_of(clk_mgr, struct clk_mgr_internal, base)
69
70#define CTX \
71 clk_mgr->base.ctx
72#define DC_LOGGER \
73 clk_mgr->ctx->logger
74
75
76
77
78#define CLK_BASE(inst) \
79 CLK_BASE_INNER(inst)
80
81#define CLK_SRI(reg_name, block, inst)\
82 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
83 mm ## block ## _ ## inst ## _ ## reg_name
84
85#define CLK_COMMON_REG_LIST_DCE_BASE() \
86 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
87 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
88
89#define CLK_COMMON_REG_LIST_DCN_BASE() \
90 SR(DENTIST_DISPCLK_CNTL)
91
92#define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
93 .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
94 .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
95 .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
96
97#ifdef CONFIG_DRM_AMD_DC_DCN2_0
98#define CLK_REG_LIST_NV10() \
99 SR(DENTIST_DISPCLK_CNTL), \
100 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
101 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
102#endif
103
104#define CLK_SF(reg_name, field_name, post_fix)\
105 .field_name = reg_name ## __ ## field_name ## post_fix
106
107#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
108 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
109 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
110
111#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
112 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
113 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
114
115#define CLK_MASK_SH_LIST_RV1(mask_sh) \
116 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
117 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
118 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
119 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
120
121#ifdef CONFIG_DRM_AMD_DC_DCN2_0
122#define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
123 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
124 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
125 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
126
127#define CLK_MASK_SH_LIST_NV10(mask_sh) \
128 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
129 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
130 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
131#endif
132
133#define CLK_REG_FIELD_LIST(type) \
134 type DPREFCLK_SRC_SEL; \
135 type DENTIST_DPREFCLK_WDIVIDER; \
136 type DENTIST_DISPCLK_WDIVIDER; \
137 type DENTIST_DISPCLK_CHG_DONE;
138
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143
144#ifdef CONFIG_DRM_AMD_DC_DCN2_0
145#define CLK20_REG_FIELD_LIST(type) \
146 type DENTIST_DPPCLK_WDIVIDER; \
147 type DENTIST_DPPCLK_CHG_DONE; \
148 type FbMult_int; \
149 type FbMult_frac;
150#endif
151
152#define VBIOS_SMU_REG_FIELD_LIST(type) \
153 type CONTENT;
154
155struct clk_mgr_shift {
156 CLK_REG_FIELD_LIST(uint8_t)
157#ifdef CONFIG_DRM_AMD_DC_DCN2_0
158 CLK20_REG_FIELD_LIST(uint8_t)
159#endif
160 VBIOS_SMU_REG_FIELD_LIST(uint32_t)
161};
162
163struct clk_mgr_mask {
164 CLK_REG_FIELD_LIST(uint32_t)
165#ifdef CONFIG_DRM_AMD_DC_DCN2_0
166 CLK20_REG_FIELD_LIST(uint32_t)
167#endif
168 VBIOS_SMU_REG_FIELD_LIST(uint32_t)
169};
170
171struct clk_mgr_registers {
172 uint32_t DPREFCLK_CNTL;
173 uint32_t DENTIST_DISPCLK_CNTL;
174
175#ifdef CONFIG_DRM_AMD_DC_DCN2_0
176 uint32_t CLK3_CLK2_DFS_CNTL;
177 uint32_t CLK3_CLK_PLL_REQ;
178#endif
179
180 uint32_t MP1_SMN_C2PMSG_67;
181 uint32_t MP1_SMN_C2PMSG_83;
182 uint32_t MP1_SMN_C2PMSG_91;
183};
184
185struct state_dependent_clocks {
186 int display_clk_khz;
187 int pixel_clk_khz;
188};
189
190struct clk_mgr_internal {
191 struct clk_mgr base;
192 struct pp_smu_funcs *pp_smu;
193 struct clk_mgr_internal_funcs *funcs;
194
195 struct dccg *dccg;
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203 const struct clk_mgr_registers *regs;
204 const struct clk_mgr_shift *clk_mgr_shift;
205 const struct clk_mgr_mask *clk_mgr_mask;
206
207 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
208
209
210 int dentist_vco_freq_khz;
211
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213 bool dfs_bypass_enabled;
214
215 bool dfs_bypass_active;
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220 int dfs_bypass_disp_clk;
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227 bool ss_on_dprefclk;
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234
235 bool xgmi_enabled;
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246 int dprefclk_ss_percentage;
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253 int dprefclk_ss_divider;
254
255 enum dm_pp_clocks_state max_clks_state;
256 enum dm_pp_clocks_state cur_min_clks_state;
257};
258
259struct clk_mgr_internal_funcs {
260 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
261 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
262};
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272static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
273{
274 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
275}
276
277static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
278{
279
280 return (calc_support != cur_support) ? !safe_to_lower : false;
281}
282
283int clk_mgr_helper_get_active_display_cnt(
284 struct dc *dc,
285 struct dc_state *context);
286
287
288
289#endif
290