LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

   1/* Copyright 2012-17 Advanced Micro Devices, Inc.
   2 *
   3 * Permission is hereby granted, free of charge, to any person obtaining a
   4 * copy of this software and associated documentation files (the "Software"),
   5 * to deal in the Software without restriction, including without limitation
   6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7 * and/or sell copies of the Software, and to permit persons to whom the
   8 * Software is furnished to do so, subject to the following conditions:
   9 *
  10 * The above copyright notice and this permission notice shall be included in
  11 * all copies or substantial portions of the Software.
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19 * OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * Authors: AMD
  22 *
  23 */
  24
  25#ifndef __DC_DWBC_H__
  26#define __DC_DWBC_H__
  27
  28#include "dc_hw_types.h"
  29
  30
  31#define DWB_SW_V2       1
  32#define DWB_MCIF_BUF_COUNT 4
  33
  34/* forward declaration of mcif_wb struct */
  35struct mcif_wb;
  36
  37enum dce_version;
  38
  39enum dwb_sw_version {
  40        dwb_ver_1_0 = 1,
  41        dwb_ver_2_0 = 2,
  42};
  43
  44enum dwb_source {
  45        dwb_src_scl = 0,        /* for DCE7x/9x, DCN won't support. */
  46        dwb_src_blnd,           /* for DCE7x/9x */
  47        dwb_src_fmt,            /* for DCE7x/9x */
  48#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  49        dwb_src_otg0 = 0x100,   /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
  50        dwb_src_otg1,           /* for DCN1.x/DCN2.x */
  51        dwb_src_otg2,           /* for DCN1.x/DCN2.x */
  52        dwb_src_otg3,           /* for DCN1.x/DCN2.x */
  53#else
  54        dwb_src_otg0 = 0x100,   /* for DCN1.x, register: mmDWB_SOURCE_SELECT */
  55        dwb_src_otg1,           /* for DCN1.x */
  56        dwb_src_otg2,           /* for DCN1.x */
  57        dwb_src_otg3,           /* for DCN1.x */
  58#endif
  59        dwb_src_mpc0 = 0x200,   /* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
  60        dwb_src_mpc1,           /* for DCN2 */
  61        dwb_src_mpc2,           /* for DCN2 */
  62        dwb_src_mpc3,           /* for DCN2 */
  63        dwb_src_mpc4,           /* for DCN2 */
  64};
  65
  66#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  67/* DCN1.x, DCN2.x support 2 pipes */
  68#else
  69/* DCN1.x supports 2 pipes */
  70#endif
  71enum dwb_pipe {
  72        dwb_pipe0 = 0,
  73#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  74        dwb_pipe1,
  75#endif
  76        dwb_pipe_max_num,
  77};
  78
  79#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  80enum dwb_frame_capture_enable {
  81        DWB_FRAME_CAPTURE_DISABLE = 0,
  82        DWB_FRAME_CAPTURE_ENABLE = 1,
  83};
  84
  85enum wbscl_coef_filter_type_sel {
  86        WBSCL_COEF_LUMA_VERT_FILTER = 0,
  87        WBSCL_COEF_CHROMA_VERT_FILTER = 1,
  88        WBSCL_COEF_LUMA_HORZ_FILTER = 2,
  89        WBSCL_COEF_CHROMA_HORZ_FILTER = 3
  90};
  91
  92#endif
  93
  94#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  95struct dwb_warmup_params {
  96        bool    warmup_en;      /* false: normal mode, true: enable pattern generator */
  97        bool    warmup_mode;    /* false: 420, true: 444 */
  98        bool    warmup_depth;   /* false: 8bit, true: 10bit */
  99        int     warmup_data;    /* Data to be sent by pattern generator (same for each pixel component) */
 100        int     warmup_width;   /* Pattern width (pixels) */
 101        int     warmup_height;  /* Pattern height (lines) */
 102};
 103#endif
 104
 105struct dwb_caps {
 106        enum dce_version hw_version;    /* DCN engine version. */
 107        enum dwb_sw_version sw_version; /* DWB sw implementation version. */
 108        unsigned int    reserved[6];    /* Reserved for future use, MUST BE 0. */
 109        unsigned int    adapter_id;
 110        unsigned int    num_pipes;      /* number of DWB pipes */
 111        struct {
 112                unsigned int support_dwb        :1;
 113                unsigned int support_ogam       :1;
 114                unsigned int support_wbscl      :1;
 115                unsigned int support_ocsc       :1;
 116                unsigned int support_stereo :1;
 117        } caps;
 118        unsigned int     reserved2[9];  /* Reserved for future use, MUST BE 0. */
 119};
 120
 121struct dwbc {
 122        const struct dwbc_funcs *funcs;
 123        struct dc_context *ctx;
 124        int inst;
 125        struct mcif_wb *mcif;
 126        bool status;
 127        int inputSrcSelect;
 128        bool dwb_output_black;
 129        enum dc_transfer_func_predefined tf;
 130        enum dc_color_space output_color_space;
 131        bool dwb_is_efc_transition;
 132        bool dwb_is_drc;
 133        int wb_src_plane_inst;/*hubp, mpcc, inst*/
 134        bool update_privacymask;
 135        uint32_t mask_id;
 136
 137};
 138
 139struct dwbc_funcs {
 140        bool (*get_caps)(
 141                struct dwbc *dwbc,
 142                struct dwb_caps *caps);
 143
 144        bool (*enable)(
 145                struct dwbc *dwbc,
 146                struct dc_dwb_params *params);
 147
 148        bool (*disable)(struct dwbc *dwbc);
 149
 150        bool (*update)(
 151                struct dwbc *dwbc,
 152                struct dc_dwb_params *params);
 153
 154        bool (*is_enabled)(
 155                struct dwbc *dwbc);
 156
 157        void (*set_stereo)(
 158                struct dwbc *dwbc,
 159                struct dwb_stereo_params *stereo_params);
 160
 161        void (*set_new_content)(
 162                struct dwbc *dwbc,
 163                bool is_new_content);
 164
 165#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 166
 167        void (*set_warmup)(
 168                struct dwbc *dwbc,
 169                struct dwb_warmup_params *warmup_params);
 170
 171#endif
 172
 173        bool (*get_dwb_status)(
 174                struct dwbc *dwbc);
 175        void (*dwb_set_scaler)(
 176                struct dwbc *dwbc,
 177                struct dc_dwb_params *params);
 178};
 179
 180#endif
 181