LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw/link

   1/*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23/*
  24 * link_encoder.h
  25 *
  26 *  Created on: Oct 6, 2015
  27 *      Author: yonsun
  28 */
  29
  30#ifndef LINK_ENCODER_H_
  31#define LINK_ENCODER_H_
  32
  33#include "grph_object_defs.h"
  34#include "signal_types.h"
  35#include "dc_types.h"
  36
  37struct dc_context;
  38struct encoder_set_dp_phy_pattern_param;
  39struct link_mst_stream_allocation_table;
  40struct dc_link_settings;
  41struct link_training_settings;
  42struct pipe_ctx;
  43
  44struct encoder_init_data {
  45        enum channel_id channel;
  46        struct graphics_object_id connector;
  47        enum hpd_source_id hpd_source;
  48        /* TODO: in DAL2, here was pointer to EventManagerInterface */
  49        struct graphics_object_id encoder;
  50        struct dc_context *ctx;
  51        enum transmitter transmitter;
  52};
  53
  54struct encoder_feature_support {
  55        union {
  56                struct {
  57                        uint32_t IS_HBR2_CAPABLE:1;
  58                        uint32_t IS_HBR3_CAPABLE:1;
  59                        uint32_t IS_TPS3_CAPABLE:1;
  60                        uint32_t IS_TPS4_CAPABLE:1;
  61                        uint32_t HDMI_6GB_EN:1;
  62                        uint32_t DP_IS_USB_C:1;
  63                } bits;
  64                uint32_t raw;
  65        } flags;
  66
  67        enum dc_color_depth max_hdmi_deep_color;
  68        unsigned int max_hdmi_pixel_clock;
  69        bool hdmi_ycbcr420_supported;
  70        bool dp_ycbcr420_supported;
  71};
  72
  73union dpcd_psr_configuration {
  74        struct {
  75                unsigned char ENABLE                    : 1;
  76                unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
  77                unsigned char CRC_VERIFICATION          : 1;
  78                unsigned char FRAME_CAPTURE_INDICATION  : 1;
  79                /* For eDP 1.4, PSR v2*/
  80                unsigned char LINE_CAPTURE_INDICATION   : 1;
  81                /* For eDP 1.4, PSR v2*/
  82                unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
  83                unsigned char RESERVED                  : 2;
  84        } bits;
  85        unsigned char raw;
  86};
  87
  88union psr_error_status {
  89        struct {
  90                unsigned char LINK_CRC_ERROR        :1;
  91                unsigned char RFB_STORAGE_ERROR     :1;
  92                unsigned char RESERVED              :6;
  93        } bits;
  94        unsigned char raw;
  95};
  96
  97union psr_sink_psr_status {
  98        struct {
  99        unsigned char SINK_SELF_REFRESH_STATUS  :3;
 100        unsigned char RESERVED                  :5;
 101        } bits;
 102        unsigned char raw;
 103};
 104
 105struct link_encoder {
 106        const struct link_encoder_funcs *funcs;
 107        int32_t aux_channel_offset;
 108        struct dc_context *ctx;
 109        struct graphics_object_id id;
 110        struct graphics_object_id connector;
 111        uint32_t output_signals;
 112        enum engine_id preferred_engine;
 113        struct encoder_feature_support features;
 114        enum transmitter transmitter;
 115        enum hpd_source_id hpd_source;
 116#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 117        bool usbc_combo_phy;
 118#endif
 119};
 120
 121#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 122struct link_enc_state {
 123
 124                uint32_t dphy_fec_en;
 125                uint32_t dphy_fec_ready_shadow;
 126                uint32_t dphy_fec_active_status;
 127
 128};
 129#endif
 130
 131struct link_encoder_funcs {
 132#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 133        void (*read_state)(
 134                        struct link_encoder *enc, struct link_enc_state *s);
 135#endif
 136        bool (*validate_output_with_stream)(
 137                struct link_encoder *enc, const struct dc_stream_state *stream);
 138        void (*hw_init)(struct link_encoder *enc);
 139        void (*setup)(struct link_encoder *enc,
 140                enum signal_type signal);
 141        void (*enable_tmds_output)(struct link_encoder *enc,
 142                enum clock_source_id clock_source,
 143                enum dc_color_depth color_depth,
 144                enum signal_type signal,
 145                uint32_t pixel_clock);
 146        void (*enable_dp_output)(struct link_encoder *enc,
 147                const struct dc_link_settings *link_settings,
 148                enum clock_source_id clock_source);
 149        void (*enable_dp_mst_output)(struct link_encoder *enc,
 150                const struct dc_link_settings *link_settings,
 151                enum clock_source_id clock_source);
 152        void (*enable_lvds_output)(struct link_encoder *enc,
 153                enum clock_source_id clock_source,
 154                uint32_t pixel_clock);
 155        void (*disable_output)(struct link_encoder *link_enc,
 156                enum signal_type signal);
 157        void (*dp_set_lane_settings)(struct link_encoder *enc,
 158                const struct link_training_settings *link_settings);
 159        void (*dp_set_phy_pattern)(struct link_encoder *enc,
 160                const struct encoder_set_dp_phy_pattern_param *para);
 161        void (*update_mst_stream_allocation_table)(
 162                struct link_encoder *enc,
 163                const struct link_mst_stream_allocation_table *table);
 164        void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
 165                        bool exit_link_training_required);
 166        void (*psr_program_secondary_packet)(struct link_encoder *enc,
 167                                unsigned int sdp_transmit_line_num_deadline);
 168        void (*connect_dig_be_to_fe)(struct link_encoder *enc,
 169                enum engine_id engine,
 170                bool connect);
 171        void (*enable_hpd)(struct link_encoder *enc);
 172        void (*disable_hpd)(struct link_encoder *enc);
 173        bool (*is_dig_enabled)(struct link_encoder *enc);
 174        unsigned int (*get_dig_frontend)(struct link_encoder *enc);
 175        void (*destroy)(struct link_encoder **enc);
 176
 177#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 178        void (*fec_set_enable)(struct link_encoder *enc,
 179                bool enable);
 180
 181        void (*fec_set_ready)(struct link_encoder *enc,
 182                bool ready);
 183
 184        bool (*fec_is_active)(struct link_encoder *enc);
 185#endif
 186};
 187
 188#endif /* LINK_ENCODER_H_ */
 189