1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef DCE_6_0_D_H 24#define DCE_6_0_D_H 25 26#define ixATTR00 0x0000 27#define ixATTR01 0x0001 28#define ixATTR02 0x0002 29#define ixATTR03 0x0003 30#define ixATTR04 0x0004 31#define ixATTR05 0x0005 32#define ixATTR06 0x0006 33#define ixATTR07 0x0007 34#define ixATTR08 0x0008 35#define ixATTR09 0x0009 36#define ixATTR0A 0x000A 37#define ixATTR0B 0x000B 38#define ixATTR0C 0x000C 39#define ixATTR0D 0x000D 40#define ixATTR0E 0x000E 41#define ixATTR0F 0x000F 42#define ixATTR10 0x0010 43#define ixATTR11 0x0011 44#define ixATTR12 0x0012 45#define ixATTR13 0x0013 46#define ixATTR14 0x0014 47#define ixAUDIO_DESCRIPTOR0 0x0001 48#define ixAUDIO_DESCRIPTOR10 0x000B 49#define ixAUDIO_DESCRIPTOR1 0x0002 50#define ixAUDIO_DESCRIPTOR11 0x000C 51#define ixAUDIO_DESCRIPTOR12 0x000D 52#define ixAUDIO_DESCRIPTOR13 0x000E 53#define ixAUDIO_DESCRIPTOR2 0x0003 54#define ixAUDIO_DESCRIPTOR3 0x0004 55#define ixAUDIO_DESCRIPTOR4 0x0005 56#define ixAUDIO_DESCRIPTOR5 0x0006 57#define ixAUDIO_DESCRIPTOR6 0x0007 58#define ixAUDIO_DESCRIPTOR7 0x0008 59#define ixAUDIO_DESCRIPTOR8 0x0009 60#define ixAUDIO_DESCRIPTOR9 0x000A 61#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 62#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 63#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 64#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 65#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 66#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 67#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 68#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 69#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 70#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 71#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 72#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 73#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 74#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 75#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 76#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 77#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 78#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 79#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 80#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A 81#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B 82#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C 83#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D 84#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E 85#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F 86#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 87#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 88#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 89#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 90#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 91#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 92#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 93#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 94#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 95#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 96#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 97#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A 98#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B 99#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C 100#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D 101#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E 102#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F 103#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 104#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 105#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 106#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 107#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 108#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 109#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 110#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 111#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 112#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A 113#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B 114#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C 115#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D 116#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E 117#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F 118#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 119#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 120#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 121#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 122#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D 123#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E 124#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E 125#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 126#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 127#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B 128#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A 129#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 130#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 131#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 132#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF 133#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 134#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 135#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 136#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 137#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 138#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F 139#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B 140#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 141#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A 142#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 143#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 144#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 145#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 146#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 147#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 148#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 149#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C 150#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B 151#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 152#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 153#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 154#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 155#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 156#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 157#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 158#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A 159#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 160#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 161#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 162#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 163#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 164#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C 165#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D 166#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E 167#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F 168#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 169#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 170#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 171#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 172#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 173#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 174#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 175#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C 176#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E 177#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 178#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 179#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 180#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A 181#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B 182#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C 183#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D 184#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E 185#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F 186#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 187#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 188#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 189#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 190#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 191#define ixAZALIA_STREAM_DEBUG 0x0005 192#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 193#define ixCRT00 0x0000 194#define ixCRT01 0x0001 195#define ixCRT02 0x0002 196#define ixCRT03 0x0003 197#define ixCRT04 0x0004 198#define ixCRT05 0x0005 199#define ixCRT06 0x0006 200#define ixCRT07 0x0007 201#define ixCRT08 0x0008 202#define ixCRT09 0x0009 203#define ixCRT0A 0x000A 204#define ixCRT0B 0x000B 205#define ixCRT0C 0x000C 206#define ixCRT0D 0x000D 207#define ixCRT0E 0x000E 208#define ixCRT0F 0x000F 209#define ixCRT10 0x0010 210#define ixCRT11 0x0011 211#define ixCRT12 0x0012 212#define ixCRT13 0x0013 213#define ixCRT14 0x0014 214#define ixCRT15 0x0015 215#define ixCRT16 0x0016 216#define ixCRT17 0x0017 217#define ixCRT18 0x0018 218#define ixCRT1E 0x001E 219#define ixCRT1F 0x001F 220#define ixCRT22 0x0022 221#define ixDCIO_DEBUG10 0x0010 222#define ixDCIO_DEBUG1 0x0001 223#define ixDCIO_DEBUG11 0x0011 224#define ixDCIO_DEBUG12 0x0012 225#define ixDCIO_DEBUG13 0x0013 226#define ixDCIO_DEBUG2 0x0002 227#define ixDCIO_DEBUG3 0x0003 228#define ixDCIO_DEBUG4 0x0004 229#define ixDCIO_DEBUG5 0x0005 230#define ixDCIO_DEBUG6 0x0006 231#define ixDCIO_DEBUG7 0x0007 232#define ixDCIO_DEBUG8 0x0008 233#define ixDCIO_DEBUG9 0x0009 234#define ixDCIO_DEBUGA 0x000A 235#define ixDCIO_DEBUGB 0x000B 236#define ixDCIO_DEBUGC 0x000C 237#define ixDCIO_DEBUGD 0x000D 238#define ixDCIO_DEBUGE 0x000E 239#define ixDCIO_DEBUGF 0x000F 240#define ixDCIO_DEBUG_ID 0x0000 241#define ixDMIF_DEBUG02_CORE0 0x0002 242#define ixDMIF_DEBUG02_CORE1 0x000A 243#define ixDP_AUX1_DEBUG_A 0x0010 244#define ixDP_AUX1_DEBUG_B 0x0011 245#define ixDP_AUX1_DEBUG_C 0x0012 246#define ixDP_AUX1_DEBUG_D 0x0013 247#define ixDP_AUX1_DEBUG_E 0x0014 248#define ixDP_AUX1_DEBUG_F 0x0015 249#define ixDP_AUX1_DEBUG_G 0x0016 250#define ixDP_AUX1_DEBUG_H 0x0017 251#define ixDP_AUX1_DEBUG_I 0x0018 252#define ixDP_AUX2_DEBUG_A 0x0020 253#define ixDP_AUX2_DEBUG_B 0x0021 254#define ixDP_AUX2_DEBUG_C 0x0022 255#define ixDP_AUX2_DEBUG_D 0x0023 256#define ixDP_AUX2_DEBUG_E 0x0024 257#define ixDP_AUX2_DEBUG_F 0x0025 258#define ixDP_AUX2_DEBUG_G 0x0026 259#define ixDP_AUX2_DEBUG_H 0x0027 260#define ixDP_AUX2_DEBUG_I 0x0028 261#define ixDP_AUX3_DEBUG_A 0x0030 262#define ixDP_AUX3_DEBUG_B 0x0031 263#define ixDP_AUX3_DEBUG_C 0x0032 264#define ixDP_AUX3_DEBUG_D 0x0033 265#define ixDP_AUX3_DEBUG_E 0x0034 266#define ixDP_AUX3_DEBUG_F 0x0035 267#define ixDP_AUX3_DEBUG_G 0x0036 268#define ixDP_AUX3_DEBUG_H 0x0037 269#define ixDP_AUX3_DEBUG_I 0x0038 270#define ixDP_AUX4_DEBUG_A 0x0040 271#define ixDP_AUX4_DEBUG_B 0x0041 272#define ixDP_AUX4_DEBUG_C 0x0042 273#define ixDP_AUX4_DEBUG_D 0x0043 274#define ixDP_AUX4_DEBUG_E 0x0044 275#define ixDP_AUX4_DEBUG_F 0x0045 276#define ixDP_AUX4_DEBUG_G 0x0046 277#define ixDP_AUX4_DEBUG_H 0x0047 278#define ixDP_AUX4_DEBUG_I 0x0048 279#define ixDP_AUX5_DEBUG_A 0x0070 280#define ixDP_AUX5_DEBUG_B 0x0071 281#define ixDP_AUX5_DEBUG_C 0x0072 282#define ixDP_AUX5_DEBUG_D 0x0073 283#define ixDP_AUX5_DEBUG_E 0x0074 284#define ixDP_AUX5_DEBUG_F 0x0075 285#define ixDP_AUX5_DEBUG_G 0x0076 286#define ixDP_AUX5_DEBUG_H 0x0077 287#define ixDP_AUX5_DEBUG_I 0x0078 288#define ixDP_AUX6_DEBUG_A 0x0080 289#define ixDP_AUX6_DEBUG_B 0x0081 290#define ixDP_AUX6_DEBUG_C 0x0082 291#define ixDP_AUX6_DEBUG_D 0x0083 292#define ixDP_AUX6_DEBUG_E 0x0084 293#define ixDP_AUX6_DEBUG_F 0x0085 294#define ixDP_AUX6_DEBUG_G 0x0086 295#define ixDP_AUX6_DEBUG_H 0x0087 296#define ixDP_AUX6_DEBUG_I 0x0088 297#define ixFMT_DEBUG0 0x0001 298#define ixFMT_DEBUG1 0x0002 299#define ixFMT_DEBUG2 0x0003 300#define ixFMT_DEBUG_ID 0x0000 301#define ixGRA00 0x0000 302#define ixGRA01 0x0001 303#define ixGRA02 0x0002 304#define ixGRA03 0x0003 305#define ixGRA04 0x0004 306#define ixGRA05 0x0005 307#define ixGRA06 0x0006 308#define ixGRA07 0x0007 309#define ixGRA08 0x0008 310#define ixIDDCCIF02_DBG_DCCIF_C 0x0009 311#define ixIDDCCIF04_DBG_DCCIF_E 0x000B 312#define ixIDDCCIF05_DBG_DCCIF_F 0x000C 313#define ixMVP_DEBUG_12 0x000C 314#define ixMVP_DEBUG_13 0x000D 315#define ixMVP_DEBUG_14 0x000E 316#define ixMVP_DEBUG_15 0x000F 317#define ixMVP_DEBUG_16 0x0010 318#define ixMVP_DEBUG_17 0x0011 319#define ixSEQ00 0x0000 320#define ixSEQ01 0x0001 321#define ixSEQ02 0x0002 322#define ixSEQ03 0x0003 323#define ixSEQ04 0x0004 324#define ixSINK_DESCRIPTION0 0x0005 325#define ixSINK_DESCRIPTION10 0x000F 326#define ixSINK_DESCRIPTION1 0x0006 327#define ixSINK_DESCRIPTION11 0x0010 328#define ixSINK_DESCRIPTION12 0x0011 329#define ixSINK_DESCRIPTION13 0x0012 330#define ixSINK_DESCRIPTION14 0x0013 331#define ixSINK_DESCRIPTION15 0x0014 332#define ixSINK_DESCRIPTION16 0x0015 333#define ixSINK_DESCRIPTION17 0x0016 334#define ixSINK_DESCRIPTION2 0x0007 335#define ixSINK_DESCRIPTION3 0x0008 336#define ixSINK_DESCRIPTION4 0x0009 337#define ixSINK_DESCRIPTION5 0x000A 338#define ixSINK_DESCRIPTION6 0x000B 339#define ixSINK_DESCRIPTION7 0x000C 340#define ixSINK_DESCRIPTION8 0x000D 341#define ixSINK_DESCRIPTION9 0x000E 342#define ixVGADCC_DBG_DCCIF_C 0x007E 343#define mmABM_TEST_DEBUG_DATA 0x169F 344#define mmABM_TEST_DEBUG_INDEX 0x169E 345#define mmAFMT_60958_0 0x1C41 346#define mmAFMT_60958_1 0x1C42 347#define mmAFMT_60958_2 0x1C48 348#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 349#define mmAFMT_AUDIO_CRC_RESULT 0x1C49 350#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 351#define mmAFMT_AUDIO_INFO0 0x1C3F 352#define mmAFMT_AUDIO_INFO1 0x1C40 353#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B 354#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 355#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F 356#define mmAFMT_AVI_INFO0 0x1C21 357#define mmAFMT_AVI_INFO1 0x1C22 358#define mmAFMT_AVI_INFO2 0x1C23 359#define mmAFMT_AVI_INFO3 0x1C24 360#define mmAFMT_GENERIC_0 0x1C28 361#define mmAFMT_GENERIC_1 0x1C29 362#define mmAFMT_GENERIC_2 0x1C2A 363#define mmAFMT_GENERIC_3 0x1C2B 364#define mmAFMT_GENERIC_4 0x1C2C 365#define mmAFMT_GENERIC_5 0x1C2D 366#define mmAFMT_GENERIC_6 0x1C2E 367#define mmAFMT_GENERIC_7 0x1C2F 368#define mmAFMT_GENERIC_HDR 0x1C27 369#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D 370#define mmAFMT_INTERRUPT_STATUS 0x1C14 371#define mmAFMT_ISRC1_0 0x1C18 372#define mmAFMT_ISRC1_1 0x1C19 373#define mmAFMT_ISRC1_2 0x1C1A 374#define mmAFMT_ISRC1_3 0x1C1B 375#define mmAFMT_ISRC1_4 0x1C1C 376#define mmAFMT_ISRC2_0 0x1C1D 377#define mmAFMT_ISRC2_1 0x1C1E 378#define mmAFMT_ISRC2_2 0x1C1F 379#define mmAFMT_ISRC2_3 0x1C20 380#define mmAFMT_MPEG_INFO0 0x1C25 381#define mmAFMT_MPEG_INFO1 0x1C26 382#define mmAFMT_RAMP_CONTROL0 0x1C44 383#define mmAFMT_RAMP_CONTROL1 0x1C45 384#define mmAFMT_RAMP_CONTROL2 0x1C46 385#define mmAFMT_RAMP_CONTROL3 0x1C47 386#define mmAFMT_STATUS 0x1C4A 387#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C 388#define mmATTRDR 0x00F0 389#define mmATTRDW 0x00F0 390#define mmATTRX 0x00F0 391#define mmAUX_ARB_CONTROL 0x1882 392#define mmAUX_CONTROL 0x1880 393#define mmAUX_DPHY_RX_CONTROL0 0x188A 394#define mmAUX_DPHY_RX_CONTROL1 0x188B 395#define mmAUX_DPHY_RX_STATUS 0x188D 396#define mmAUX_DPHY_TX_CONTROL 0x1889 397#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 398#define mmAUX_DPHY_TX_STATUS 0x188C 399#define mmAUX_GTC_SYNC_CONTROL 0x188E 400#define mmAUX_GTC_SYNC_DATA 0x1890 401#define mmAUX_INTERRUPT_CONTROL 0x1883 402#define mmAUX_LS_DATA 0x1887 403#define mmAUX_LS_STATUS 0x1885 404#define mmAUXN_IMPCAL 0x190C 405#define mmAUXP_IMPCAL 0x190B 406#define mmAUX_SW_CONTROL 0x1881 407#define mmAUX_SW_DATA 0x1886 408#define mmAUX_SW_STATUS 0x1884 409#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 410#define mmAZALIA_AUDIO_DTO 0x17BA 411#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB 412#define mmAZALIA_BDL_DMA_CONTROL 0x17BF 413#define mmAZALIA_CONTROLLER_DEBUG 0x17CF 414#define mmAZALIA_CORB_DMA_CONTROL 0x17C1 415#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA 416#define mmAZALIA_DATA_DMA_CONTROL 0x17BE 417#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 418#define mmAZALIA_F0_CODEC_DEBUG 0x17DF 419#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 420#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 421#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE 422#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB 423#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC 424#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD 425#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 426#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA 427#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 428#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 429#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 430#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 431#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 432#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB 433#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC 434#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD 435#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 436#define mmAZALIA_SCLK_CONTROL 0x17BC 437#define mmAZALIA_STREAM_DATA 0x17E9 438#define mmAZALIA_STREAM_INDEX 0x17E8 439#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD 440#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 441#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 442#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 443#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 444#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D 445#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C 446#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 447#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 448#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 449#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 450#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F 451#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E 452#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 453#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 454#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED 455#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC 456#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 457#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 458#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 459#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 460#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 461#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 462#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD 463#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC 464#define mmAZ_TEST_DEBUG_DATA 0x17D1 465#define mmAZ_TEST_DEBUG_INDEX 0x17D0 466#define mmBL1_PWM_ABM_CNTL 0x162E 467#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 468#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F 469#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B 470#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C 471#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 472#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D 473#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A 474#define mmBL1_PWM_USER_LEVEL 0x1629 475#define mmBL_PWM_CNTL 0x191E 476#define mmBL_PWM_CNTL2 0x191F 477#define mmBL_PWM_GRP1_REG_LOCK 0x1921 478#define mmBL_PWM_PERIOD_CNTL 0x1920 479#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE 480#define mmBPHYC_DAC_MACRO_CNTL 0x19FD 481#define mmCC_DC_PIPE_DIS 0x177F 482#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 483#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 484#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 485#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 486#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 487#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 488#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 489#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 490#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A 491#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B 492#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C 493#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D 494#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E 495#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 496#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 497#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 498#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D 499#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 500#define mmCRTC0_CRTC_CONTROL 0x1B9C 501#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 502#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA 503#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C 504#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 505#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 506#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 507#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 508#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 509#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B 510#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 511#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A 512#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D 513#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 514#define mmCRTC0_CRTC_H_SYNC_A 0x1B82 515#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 516#define mmCRTC0_CRTC_H_SYNC_B 0x1B84 517#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 518#define mmCRTC0_CRTC_H_TOTAL 0x1B80 519#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E 520#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F 521#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 522#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB 523#define mmCRTC0_CRTC_MASTER_EN 0x1BC2 524#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF 525#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 526#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 527#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 528#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 529#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 530#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 531#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 532#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF 533#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 534#define mmCRTC0_CRTC_STATUS 0x1BA3 535#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 536#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 537#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 538#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 539#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE 540#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B 541#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD 542#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 543#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 544#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC 545#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA 546#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB 547#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 548#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 549#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 550#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 551#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 552#define mmCRTC0_CRTC_VBI_END 0x1B86 553#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D 554#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC 555#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 556#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E 557#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F 558#define mmCRTC0_CRTC_V_SYNC_B 0x1B90 559#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 560#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C 561#define mmCRTC0_CRTC_V_TOTAL 0x1B87 562#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A 563#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B 564#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 565#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 566#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 567#define mmCRTC0_DCFE_DBG_SEL 0x1B7E 568#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F 569#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD 570#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE 571#define mmCRTC0_PIXEL_RATE_CNTL 0x0140 572#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 573#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 574#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 575#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D 576#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 577#define mmCRTC1_CRTC_CONTROL 0x1E9C 578#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 579#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA 580#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C 581#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 582#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 583#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 584#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 585#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 586#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B 587#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 588#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A 589#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D 590#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 591#define mmCRTC1_CRTC_H_SYNC_A 0x1E82 592#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 593#define mmCRTC1_CRTC_H_SYNC_B 0x1E84 594#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 595#define mmCRTC1_CRTC_H_TOTAL 0x1E80 596#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E 597#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F 598#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 599#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB 600#define mmCRTC1_CRTC_MASTER_EN 0x1EC2 601#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF 602#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 603#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 604#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 605#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 606#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 607#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 608#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 609#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF 610#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 611#define mmCRTC1_CRTC_STATUS 0x1EA3 612#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 613#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 614#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 615#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 616#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE 617#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B 618#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD 619#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 620#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 621#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC 622#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA 623#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB 624#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 625#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 626#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 627#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 628#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 629#define mmCRTC1_CRTC_VBI_END 0x1E86 630#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D 631#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC 632#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 633#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E 634#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F 635#define mmCRTC1_CRTC_V_SYNC_B 0x1E90 636#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 637#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C 638#define mmCRTC1_CRTC_V_TOTAL 0x1E87 639#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A 640#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B 641#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 642#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 643#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 644#define mmCRTC1_DCFE_DBG_SEL 0x1E7E 645#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F 646#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD 647#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE 648#define mmCRTC1_PIXEL_RATE_CNTL 0x0144 649#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 650#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 651#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 652#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D 653#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 654#define mmCRTC2_CRTC_CONTROL 0x419C 655#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 656#define mmCRTC2_CRTC_COUNT_RESET 0x41AA 657#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C 658#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 659#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 660#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 661#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 662#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 663#define mmCRTC2_CRTC_GSL_CONTROL 0x417B 664#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 665#define mmCRTC2_CRTC_GSL_WINDOW 0x417A 666#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D 667#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 668#define mmCRTC2_CRTC_H_SYNC_A 0x4182 669#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 670#define mmCRTC2_CRTC_H_SYNC_B 0x4184 671#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 672#define mmCRTC2_CRTC_H_TOTAL 0x4180 673#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E 674#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F 675#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 676#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB 677#define mmCRTC2_CRTC_MASTER_EN 0x41C2 678#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF 679#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 680#define mmCRTC2_CRTC_MVP_STATUS 0x41C1 681#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 682#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 683#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 684#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 685#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 686#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF 687#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 688#define mmCRTC2_CRTC_STATUS 0x41A3 689#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 690#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 691#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 692#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 693#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE 694#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B 695#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD 696#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 697#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 698#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC 699#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA 700#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB 701#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 702#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 703#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 704#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 705#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 706#define mmCRTC2_CRTC_VBI_END 0x4186 707#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D 708#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC 709#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 710#define mmCRTC2_CRTC_V_SYNC_A 0x418E 711#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F 712#define mmCRTC2_CRTC_V_SYNC_B 0x4190 713#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 714#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C 715#define mmCRTC2_CRTC_V_TOTAL 0x4187 716#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A 717#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B 718#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 719#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 720#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 721#define mmCRTC2_DCFE_DBG_SEL 0x417E 722#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F 723#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD 724#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE 725#define mmCRTC2_PIXEL_RATE_CNTL 0x0148 726#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 727#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 728#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 729#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D 730#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 731#define mmCRTC3_CRTC_CONTROL 0x449C 732#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 733#define mmCRTC3_CRTC_COUNT_RESET 0x44AA 734#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C 735#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 736#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 737#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 738#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 739#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 740#define mmCRTC3_CRTC_GSL_CONTROL 0x447B 741#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 742#define mmCRTC3_CRTC_GSL_WINDOW 0x447A 743#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D 744#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 745#define mmCRTC3_CRTC_H_SYNC_A 0x4482 746#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 747#define mmCRTC3_CRTC_H_SYNC_B 0x4484 748#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 749#define mmCRTC3_CRTC_H_TOTAL 0x4480 750#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E 751#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F 752#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 753#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB 754#define mmCRTC3_CRTC_MASTER_EN 0x44C2 755#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF 756#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 757#define mmCRTC3_CRTC_MVP_STATUS 0x44C1 758#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 759#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 760#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 761#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 762#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 763#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF 764#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 765#define mmCRTC3_CRTC_STATUS 0x44A3 766#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 767#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 768#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 769#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 770#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE 771#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B 772#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD 773#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 774#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 775#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC 776#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA 777#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB 778#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 779#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 780#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 781#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 782#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 783#define mmCRTC3_CRTC_VBI_END 0x4486 784#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D 785#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC 786#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 787#define mmCRTC3_CRTC_V_SYNC_A 0x448E 788#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F 789#define mmCRTC3_CRTC_V_SYNC_B 0x4490 790#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 791#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C 792#define mmCRTC3_CRTC_V_TOTAL 0x4487 793#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A 794#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B 795#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 796#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 797#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 798#define mmCRTC3_DCFE_DBG_SEL 0x447E 799#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F 800#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 801#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD 802#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE 803#define mmCRTC3_PIXEL_RATE_CNTL 0x014C 804#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 805#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 806#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 807#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D 808#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 809#define mmCRTC4_CRTC_CONTROL 0x479C 810#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 811#define mmCRTC4_CRTC_COUNT_RESET 0x47AA 812#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C 813#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 814#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 815#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 816#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 817#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 818#define mmCRTC4_CRTC_GSL_CONTROL 0x477B 819#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 820#define mmCRTC4_CRTC_GSL_WINDOW 0x477A 821#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D 822#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 823#define mmCRTC4_CRTC_H_SYNC_A 0x4782 824#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 825#define mmCRTC4_CRTC_H_SYNC_B 0x4784 826#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 827#define mmCRTC4_CRTC_H_TOTAL 0x4780 828#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E 829#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F 830#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 831#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB 832#define mmCRTC4_CRTC_MASTER_EN 0x47C2 833#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF 834#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 835#define mmCRTC4_CRTC_MVP_STATUS 0x47C1 836#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 837#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 838#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 839#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 840#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 841#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF 842#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 843#define mmCRTC4_CRTC_STATUS 0x47A3 844#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 845#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 846#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 847#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 848#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE 849#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B 850#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD 851#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 852#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 853#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC 854#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA 855#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB 856#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 857#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 858#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 859#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 860#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 861#define mmCRTC4_CRTC_VBI_END 0x4786 862#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D 863#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC 864#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 865#define mmCRTC4_CRTC_V_SYNC_A 0x478E 866#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F 867#define mmCRTC4_CRTC_V_SYNC_B 0x4790 868#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 869#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C 870#define mmCRTC4_CRTC_V_TOTAL 0x4787 871#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A 872#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B 873#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 874#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 875#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 876#define mmCRTC4_DCFE_DBG_SEL 0x477E 877#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F 878#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD 879#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE 880#define mmCRTC4_PIXEL_RATE_CNTL 0x0150 881#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 882#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 883#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 884#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D 885#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 886#define mmCRTC5_CRTC_CONTROL 0x4A9C 887#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 888#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA 889#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C 890#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 891#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 892#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 893#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 894#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 895#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B 896#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 897#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A 898#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D 899#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 900#define mmCRTC5_CRTC_H_SYNC_A 0x4A82 901#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 902#define mmCRTC5_CRTC_H_SYNC_B 0x4A84 903#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 904#define mmCRTC5_CRTC_H_TOTAL 0x4A80 905#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E 906#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F 907#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 908#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB 909#define mmCRTC5_CRTC_MASTER_EN 0x4AC2 910#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF 911#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 912#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 913#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 914#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 915#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 916#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 917#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 918#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF 919#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 920#define mmCRTC5_CRTC_STATUS 0x4AA3 921#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 922#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 923#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 924#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 925#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE 926#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B 927#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD 928#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 929#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 930#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC 931#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA 932#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB 933#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 934#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 935#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 936#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 937#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 938#define mmCRTC5_CRTC_VBI_END 0x4A86 939#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D 940#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC 941#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 942#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E 943#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F 944#define mmCRTC5_CRTC_V_SYNC_B 0x4A90 945#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 946#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C 947#define mmCRTC5_CRTC_V_TOTAL 0x4A87 948#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A 949#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B 950#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 951#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 952#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 953#define mmCRTC5_DCFE_DBG_SEL 0x4A7E 954#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F 955#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD 956#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE 957#define mmCRTC5_PIXEL_RATE_CNTL 0x0154 958#define mmCRTC8_DATA 0x00ED 959#define mmCRTC8_IDX 0x00ED 960#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 961#define mmCRTC_BLACK_COLOR 0x1BA2 962#define mmCRTC_BLANK_CONTROL 0x1B9D 963#define mmCRTC_BLANK_DATA_COLOR 0x1BA1 964#define mmCRTC_CONTROL 0x1B9C 965#define mmCRTC_COUNT_CONTROL 0x1BA9 966#define mmCRTC_COUNT_RESET 0x1BAA 967#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C 968#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 969#define mmCRTC_DTMTEST_CNTL 0x1B92 970#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 971#define mmCRTC_FLOW_CONTROL 0x1B99 972#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 973#define mmCRTC_GSL_CONTROL 0x1B7B 974#define mmCRTC_GSL_VSYNC_GAP 0x1B79 975#define mmCRTC_GSL_WINDOW 0x1B7A 976#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D 977#define mmCRTC_H_BLANK_START_END 0x1B81 978#define mmCRTC_H_SYNC_A 0x1B82 979#define mmCRTC_H_SYNC_A_CNTL 0x1B83 980#define mmCRTC_H_SYNC_B 0x1B84 981#define mmCRTC_H_SYNC_B_CNTL 0x1B85 982#define mmCRTC_H_TOTAL 0x1B80 983#define mmCRTC_INTERLACE_CONTROL 0x1B9E 984#define mmCRTC_INTERLACE_STATUS 0x1B9F 985#define mmCRTC_INTERRUPT_CONTROL 0x1BB4 986#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB 987#define mmCRTC_MASTER_EN 0x1BC2 988#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF 989#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 990#define mmCRTC_MVP_STATUS 0x1BC1 991#define mmCRTC_NOM_VERT_POSITION 0x1BA5 992#define mmCRTC_OVERSCAN_COLOR 0x1BA0 993#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 994#define mmCRTC_SNAPSHOT_FRAME 0x1BB2 995#define mmCRTC_SNAPSHOT_POSITION 0x1BB1 996#define mmCRTC_SNAPSHOT_STATUS 0x1BAF 997#define mmCRTC_START_LINE_CONTROL 0x1BB3 998#define mmCRTC_STATUS 0x1BA3 999#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 1000#define mmCRTC_STATUS_HV_COUNT 0x1BA8
1001#define mmCRTC_STATUS_POSITION 0x1BA4 1002#define mmCRTC_STATUS_VF_COUNT 0x1BA7 1003#define mmCRTC_STEREO_CONTROL 0x1BAE 1004#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B 1005#define mmCRTC_STEREO_STATUS 0x1BAD 1006#define mmCRTC_TEST_DEBUG_DATA 0x1BC7 1007#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 1008#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC 1009#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA 1010#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB 1011#define mmCRTC_TRIGA_CNTL 0x1B94 1012#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 1013#define mmCRTC_TRIGB_CNTL 0x1B96 1014#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 1015#define mmCRTC_UPDATE_LOCK 0x1BB5 1016#define mmCRTC_VBI_END 0x1B86 1017#define mmCRTC_V_BLANK_START_END 0x1B8D 1018#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC 1019#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 1020#define mmCRTC_V_SYNC_A 0x1B8E 1021#define mmCRTC_V_SYNC_A_CNTL 0x1B8F 1022#define mmCRTC_V_SYNC_B 0x1B90 1023#define mmCRTC_V_SYNC_B_CNTL 0x1B91 1024#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C 1025#define mmCRTC_V_TOTAL 0x1B87 1026#define mmCRTC_V_TOTAL_CONTROL 0x1B8A 1027#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B 1028#define mmCRTC_V_TOTAL_MAX 0x1B89 1029#define mmCRTC_V_TOTAL_MIN 0x1B88 1030#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 1031#define mmCUR_COLOR1 0x1A6C 1032#define mmCUR_COLOR2 0x1A6D 1033#define mmCUR_CONTROL 0x1A66 1034#define mmCUR_HOT_SPOT 0x1A6B 1035#define mmCUR_POSITION 0x1A6A 1036#define mmCUR_REQUEST_FILTER_CNTL 0x1A99 1037#define mmCUR_SIZE 0x1A68 1038#define mmCUR_SURFACE_ADDRESS 0x1A67 1039#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 1040#define mmCUR_UPDATE 0x1A6E 1041#define mmD1VGA_CONTROL 0x00CC 1042#define mmD2VGA_CONTROL 0x00CE 1043#define mmD3VGA_CONTROL 0x00F8 1044#define mmD4VGA_CONTROL 0x00F9 1045#define mmD5VGA_CONTROL 0x00FA 1046#define mmD6VGA_CONTROL 0x00FB 1047#define mmDAC_AUTODETECT_CONTROL 0x19EE 1048#define mmDAC_AUTODETECT_CONTROL2 0x19EF 1049#define mmDAC_AUTODETECT_CONTROL3 0x19F0 1050#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 1051#define mmDAC_AUTODETECT_STATUS 0x19F1 1052#define mmDAC_CLK_ENABLE 0x0128 1053#define mmDAC_COMPARATOR_ENABLE 0x19F7 1054#define mmDAC_COMPARATOR_OUTPUT 0x19F8 1055#define mmDAC_CONTROL 0x19F6 1056#define mmDAC_CRC_CONTROL 0x19E7 1057#define mmDAC_CRC_EN 0x19E6 1058#define mmDAC_CRC_SIG_CONTROL 0x19EB 1059#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 1060#define mmDAC_CRC_SIG_RGB 0x19EA 1061#define mmDAC_CRC_SIG_RGB_MASK 0x19E8 1062#define mmDAC_DATA 0x00F2 1063#define mmDAC_DFT_CONFIG 0x19FA 1064#define mmDAC_ENABLE 0x19E4 1065#define mmDAC_FIFO_STATUS 0x19FB 1066#define mmDAC_FORCE_DATA 0x19F4 1067#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 1068#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC 1069#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD 1070#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE 1071#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF 1072#define mmDAC_MASK 0x00F1 1073#define mmDAC_POWERDOWN 0x19F5 1074#define mmDAC_PWR_CNTL 0x19F9 1075#define mmDAC_R_INDEX 0x00F1 1076#define mmDAC_SOURCE_SELECT 0x19E5 1077#define mmDAC_STEREOSYNC_SELECT 0x19ED 1078#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC 1079#define mmDAC_W_INDEX 0x00F2 1080#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 1081#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A 1082#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B 1083#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C 1084#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D 1085#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E 1086#define mmDC_ABM1_ACE_THRES_12 0x163F 1087#define mmDC_ABM1_ACE_THRES_34 0x1640 1088#define mmDC_ABM1_BL_MASTER_LOCK 0x169C 1089#define mmDC_ABM1_CNTL 0x1638 1090#define mmDC_ABM1_DEBUG_MISC 0x1649 1091#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 1092#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 1093#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 1094#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A 1095#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 1096#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A 1097#define mmDC_ABM1_HG_MISC_CTRL 0x164B 1098#define mmDC_ABM1_HG_RESULT_10 0x1664 1099#define mmDC_ABM1_HG_RESULT_1 0x165B 1100#define mmDC_ABM1_HG_RESULT_11 0x1665 1101#define mmDC_ABM1_HG_RESULT_12 0x1666 1102#define mmDC_ABM1_HG_RESULT_13 0x1667 1103#define mmDC_ABM1_HG_RESULT_14 0x1668 1104#define mmDC_ABM1_HG_RESULT_15 0x1669 1105#define mmDC_ABM1_HG_RESULT_16 0x166A 1106#define mmDC_ABM1_HG_RESULT_17 0x166B 1107#define mmDC_ABM1_HG_RESULT_18 0x166C 1108#define mmDC_ABM1_HG_RESULT_19 0x166D 1109#define mmDC_ABM1_HG_RESULT_20 0x166E 1110#define mmDC_ABM1_HG_RESULT_2 0x165C 1111#define mmDC_ABM1_HG_RESULT_21 0x166F 1112#define mmDC_ABM1_HG_RESULT_22 0x1670 1113#define mmDC_ABM1_HG_RESULT_23 0x1671 1114#define mmDC_ABM1_HG_RESULT_24 0x1672 1115#define mmDC_ABM1_HG_RESULT_3 0x165D 1116#define mmDC_ABM1_HG_RESULT_4 0x165E 1117#define mmDC_ABM1_HG_RESULT_5 0x165F 1118#define mmDC_ABM1_HG_RESULT_6 0x1660 1119#define mmDC_ABM1_HG_RESULT_7 0x1661 1120#define mmDC_ABM1_HG_RESULT_8 0x1662 1121#define mmDC_ABM1_HG_RESULT_9 0x1663 1122#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 1123#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 1124#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E 1125#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 1126#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D 1127#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 1128#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 1129#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 1130#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F 1131#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 1132#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C 1133#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B 1134#define mmDCCG_AUDIO_DTO0_MODULE 0x016D 1135#define mmDCCG_AUDIO_DTO0_PHASE 0x016C 1136#define mmDCCG_AUDIO_DTO1_MODULE 0x0171 1137#define mmDCCG_AUDIO_DTO1_PHASE 0x0170 1138#define mmDCCG_AUDIO_DTO_SOURCE 0x016B 1139#define mmDCCG_CAC_STATUS 0x0137 1140#define mmDCCG_GATE_DISABLE_CNTL 0x0134 1141#define mmDCCG_GTC_CNTL 0x0120 1142#define mmDCCG_GTC_CURRENT 0x0123 1143#define mmDCCG_GTC_DTO_MODULO 0x0122 1144#define mmDCCG_PERFMON_CNTL 0x0133 1145#define mmDCCG_PLL0_PLL_ANALOG 0x1708 1146#define mmDCCG_PLL0_PLL_CNTL 0x1707 1147#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B 1148#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F 1149#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E 1150#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 1151#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 1152#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 1153#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 1154#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 1155#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 1156#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 1157#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A 1158#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D 1159#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C 1160#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 1161#define mmDCCG_PLL1_PLL_ANALOG 0x1718 1162#define mmDCCG_PLL1_PLL_CNTL 0x1717 1163#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B 1164#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F 1165#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E 1166#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 1167#define mmDCCG_PLL1_PLL_FB_DIV 0x1711 1168#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 1169#define mmDCCG_PLL1_PLL_POST_DIV 0x1712 1170#define mmDCCG_PLL1_PLL_REF_DIV 0x1710 1171#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 1172#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 1173#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A 1174#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D 1175#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C 1176#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 1177#define mmDCCG_PLL2_PLL_ANALOG 0x1728 1178#define mmDCCG_PLL2_PLL_CNTL 0x1727 1179#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B 1180#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F 1181#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E 1182#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 1183#define mmDCCG_PLL2_PLL_FB_DIV 0x1721 1184#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 1185#define mmDCCG_PLL2_PLL_POST_DIV 0x1722 1186#define mmDCCG_PLL2_PLL_REF_DIV 0x1720 1187#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 1188#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 1189#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A 1190#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D 1191#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C 1192#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 1193#define mmDCCG_SOFT_RESET 0x015F 1194#define mmDCCG_TEST_CLK_SEL 0x017E 1195#define mmDCCG_TEST_DEBUG_DATA 0x017D 1196#define mmDCCG_TEST_DEBUG_INDEX 0x017C 1197#define mmDCCG_VPCLK_CNTL 0x031F 1198#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 1199#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 1200#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 1201#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 1202#define mmDCDEBUG_OUT_CNTL 0x186B 1203#define mmDCDEBUG_OUT_DATA 0x186E 1204#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A 1205#define mmDC_DMCU_SCRATCH 0x1618 1206#define mmDC_DVODATA_CONFIG 0x1905 1207#define mmDCFE0_SOFT_RESET 0x0158 1208#define mmDCFE1_SOFT_RESET 0x0159 1209#define mmDCFE2_SOFT_RESET 0x015A 1210#define mmDCFE3_SOFT_RESET 0x015B 1211#define mmDCFE4_SOFT_RESET 0x015C 1212#define mmDCFE5_SOFT_RESET 0x015D 1213#define mmDCFE_DBG_SEL 0x1B7E 1214#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F 1215#define mmDC_GENERICA 0x1900 1216#define mmDC_GENERICB 0x1901 1217#define mmDC_GPIO_DDC1_A 0x194D 1218#define mmDC_GPIO_DDC1_EN 0x194E 1219#define mmDC_GPIO_DDC1_MASK 0x194C 1220#define mmDC_GPIO_DDC1_Y 0x194F 1221#define mmDC_GPIO_DDC2_A 0x1951 1222#define mmDC_GPIO_DDC2_EN 0x1952 1223#define mmDC_GPIO_DDC2_MASK 0x1950 1224#define mmDC_GPIO_DDC2_Y 0x1953 1225#define mmDC_GPIO_DDC3_A 0x1955 1226#define mmDC_GPIO_DDC3_EN 0x1956 1227#define mmDC_GPIO_DDC3_MASK 0x1954 1228#define mmDC_GPIO_DDC3_Y 0x1957 1229#define mmDC_GPIO_DDC4_A 0x1959 1230#define mmDC_GPIO_DDC4_EN 0x195A 1231#define mmDC_GPIO_DDC4_MASK 0x1958 1232#define mmDC_GPIO_DDC4_Y 0x195B 1233#define mmDC_GPIO_DDC5_A 0x195D 1234#define mmDC_GPIO_DDC5_EN 0x195E 1235#define mmDC_GPIO_DDC5_MASK 0x195C 1236#define mmDC_GPIO_DDC5_Y 0x195F 1237#define mmDC_GPIO_DDC6_A 0x1961 1238#define mmDC_GPIO_DDC6_EN 0x1962 1239#define mmDC_GPIO_DDC6_MASK 0x1960 1240#define mmDC_GPIO_DDC6_Y 0x1963 1241#define mmDC_GPIO_DDCVGA_A 0x1971 1242#define mmDC_GPIO_DDCVGA_EN 0x1972 1243#define mmDC_GPIO_DDCVGA_MASK 0x1970 1244#define mmDC_GPIO_DDCVGA_Y 0x1973 1245#define mmDC_GPIO_DEBUG 0x1904 1246#define mmDC_GPIO_DVODATA_A 0x1949 1247#define mmDC_GPIO_DVODATA_EN 0x194A 1248#define mmDC_GPIO_DVODATA_MASK 0x1948 1249#define mmDC_GPIO_DVODATA_Y 0x194B 1250#define mmDC_GPIO_GENERIC_A 0x1945 1251#define mmDC_GPIO_GENERIC_EN 0x1946 1252#define mmDC_GPIO_GENERIC_MASK 0x1944 1253#define mmDC_GPIO_GENERIC_Y 0x1947 1254#define mmDC_GPIO_GENLK_A 0x1969 1255#define mmDC_GPIO_GENLK_EN 0x196A 1256#define mmDC_GPIO_GENLK_MASK 0x1968 1257#define mmDC_GPIO_GENLK_Y 0x196B 1258#define mmDC_GPIO_HPD_A 0x196D 1259#define mmDC_GPIO_HPD_EN 0x196E 1260#define mmDC_GPIO_HPD_MASK 0x196C 1261#define mmDC_GPIO_HPD_Y 0x196F 1262#define mmDC_GPIO_I2CPAD_A 0x1975 1263#define mmDC_GPIO_I2CPAD_EN 0x1976 1264#define mmDC_GPIO_I2CPAD_MASK 0x1974 1265#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A 1266#define mmDC_GPIO_I2CPAD_Y 0x1977 1267#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 1268#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 1269#define mmDC_GPIO_PWRSEQ_A 0x1941 1270#define mmDC_GPIO_PWRSEQ_EN 0x1942 1271#define mmDC_GPIO_PWRSEQ_MASK 0x1940 1272#define mmDC_GPIO_PWRSEQ_Y 0x1943 1273#define mmDC_GPIO_SYNCA_A 0x1965 1274#define mmDC_GPIO_SYNCA_EN 0x1966 1275#define mmDC_GPIO_SYNCA_MASK 0x1964 1276#define mmDC_GPIO_SYNCA_Y 0x1967 1277#define mmDC_GPU_TIMER_READ 0x1929 1278#define mmDC_GPU_TIMER_READ_CNTL 0x192A 1279#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 1280#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 1281#define mmDC_HPD1_CONTROL 0x1809 1282#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 1283#define mmDC_HPD1_INT_CONTROL 0x1808 1284#define mmDC_HPD1_INT_STATUS 0x1807 1285#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC 1286#define mmDC_HPD2_CONTROL 0x180C 1287#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 1288#define mmDC_HPD2_INT_CONTROL 0x180B 1289#define mmDC_HPD2_INT_STATUS 0x180A 1290#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD 1291#define mmDC_HPD3_CONTROL 0x180F 1292#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 1293#define mmDC_HPD3_INT_CONTROL 0x180E 1294#define mmDC_HPD3_INT_STATUS 0x180D 1295#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE 1296#define mmDC_HPD4_CONTROL 0x1812 1297#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 1298#define mmDC_HPD4_INT_CONTROL 0x1811 1299#define mmDC_HPD4_INT_STATUS 0x1810 1300#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC 1301#define mmDC_HPD5_CONTROL 0x1815 1302#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 1303#define mmDC_HPD5_INT_CONTROL 0x1814 1304#define mmDC_HPD5_INT_STATUS 0x1813 1305#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD 1306#define mmDC_HPD6_CONTROL 0x1818 1307#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 1308#define mmDC_HPD6_INT_CONTROL 0x1817 1309#define mmDC_HPD6_INT_STATUS 0x1816 1310#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE 1311#define mmDC_I2C_ARBITRATION 0x181A 1312#define mmDC_I2C_CONTROL 0x1819 1313#define mmDC_I2C_DATA 0x1833 1314#define mmDC_I2C_DDC1_HW_STATUS 0x181D 1315#define mmDC_I2C_DDC1_SETUP 0x1824 1316#define mmDC_I2C_DDC1_SPEED 0x1823 1317#define mmDC_I2C_DDC2_HW_STATUS 0x181E 1318#define mmDC_I2C_DDC2_SETUP 0x1826 1319#define mmDC_I2C_DDC2_SPEED 0x1825 1320#define mmDC_I2C_DDC3_HW_STATUS 0x181F 1321#define mmDC_I2C_DDC3_SETUP 0x1828 1322#define mmDC_I2C_DDC3_SPEED 0x1827 1323#define mmDC_I2C_DDC4_HW_STATUS 0x1820 1324#define mmDC_I2C_DDC4_SETUP 0x182A 1325#define mmDC_I2C_DDC4_SPEED 0x1829 1326#define mmDC_I2C_DDC5_HW_STATUS 0x1821 1327#define mmDC_I2C_DDC5_SETUP 0x182C 1328#define mmDC_I2C_DDC5_SPEED 0x182B 1329#define mmDC_I2C_DDC6_HW_STATUS 0x1822 1330#define mmDC_I2C_DDC6_SETUP 0x182E 1331#define mmDC_I2C_DDC6_SPEED 0x182D 1332#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 1333#define mmDC_I2C_DDCVGA_SETUP 0x1857 1334#define mmDC_I2C_DDCVGA_SPEED 0x1856 1335#define mmDC_I2C_EDID_DETECT_CTRL 0x186F 1336#define mmDC_I2C_INTERRUPT_CONTROL 0x181B 1337#define mmDC_I2C_SW_STATUS 0x181C 1338#define mmDC_I2C_TRANSACTION0 0x182F 1339#define mmDC_I2C_TRANSACTION1 0x1830 1340#define mmDC_I2C_TRANSACTION2 0x1831 1341#define mmDC_I2C_TRANSACTION3 0x1832 1342#define mmDCI_CLK_CNTL 0x031E 1343#define mmDCI_CLK_RAMP_CNTL 0x0324 1344#define mmDCI_DEBUG_CONFIG 0x0323 1345#define mmDCI_MEM_PWR_CNTL 0x0326 1346#define mmDCI_MEM_PWR_STATE 0x031B 1347#define mmDCI_MEM_PWR_STATE2 0x0322 1348#define mmDCIO_DEBUG 0x192E 1349#define mmDCIO_GSL0_CNTL 0x1924 1350#define mmDCIO_GSL1_CNTL 0x1925 1351#define mmDCIO_GSL2_CNTL 0x1926 1352#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 1353#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 1354#define mmDCIO_IMPCAL_CNTL_AB 0x190D 1355#define mmDCIO_IMPCAL_CNTL_CD 0x1911 1356#define mmDCIO_IMPCAL_CNTL_EF 0x1915 1357#define mmDCIO_TEST_DEBUG_DATA 0x1930 1358#define mmDCIO_TEST_DEBUG_INDEX 0x192F 1359#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C 1360#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E 1361#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A 1362#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D 1363#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 1364#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 1365#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 1366#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 1367#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 1368#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 1369#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B 1370#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 1371#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 1372#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 1373#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 1374#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C 1375#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E 1376#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A 1377#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D 1378#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 1379#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 1380#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 1381#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 1382#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 1383#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 1384#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B 1385#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 1386#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 1387#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 1388#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 1389#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC 1390#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE 1391#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA 1392#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD 1393#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 1394#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 1395#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 1396#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 1397#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 1398#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 1399#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB 1400#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 1401#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 1402#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 1403#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 1404#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC 1405#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE 1406#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA 1407#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD 1408#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 1409#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 1410#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 1411#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 1412#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 1413#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 1414#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB 1415#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 1416#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 1417#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 1418#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 1419#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC 1420#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE 1421#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA 1422#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD 1423#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 1424#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 1425#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 1426#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 1427#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 1428#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 1429#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB 1430#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 1431#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 1432#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 1433#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 1434#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC 1435#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE 1436#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA 1437#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD 1438#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 1439#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 1440#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 1441#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 1442#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 1443#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 1444#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB 1445#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 1446#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 1447#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 1448#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 1449#define mmDCI_SOFT_RESET 0x015E 1450#define mmDCI_TEST_DEBUG_DATA 0x0321 1451#define mmDCI_TEST_DEBUG_INDEX 0x0320 1452#define mmDC_LUT_30_COLOR 0x1A7C 1453#define mmDC_LUT_AUTOFILL 0x1A7F 1454#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 1455#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 1456#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 1457#define mmDC_LUT_CONTROL 0x1A80 1458#define mmDC_LUT_PWL_DATA 0x1A7B 1459#define mmDC_LUT_RW_INDEX 0x1A79 1460#define mmDC_LUT_RW_MODE 0x1A78 1461#define mmDC_LUT_SEQ_COLOR 0x1A7A 1462#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D 1463#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 1464#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 1465#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 1466#define mmDC_LUT_WRITE_EN_MASK 0x1A7E 1467#define mmDC_MVP_LB_CONTROL 0x1ADB 1468#define mmDCO_CLK_CNTL 0x192B 1469#define mmDCO_CLK_RAMP_CNTL 0x192C 1470#define mmDCO_LIGHT_SLEEP_DIS 0x1907 1471#define mmDCO_MEM_POWER_STATE 0x1906 1472#define mmDCO_SOFT_RESET 0x0167 1473#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 1474#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 1475#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 1476#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 1477#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 1478#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 1479#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 1480#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A 1481#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B 1482#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C 1483#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D 1484#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E 1485#define mmDCP0_CUR_COLOR1 0x1A6C 1486#define mmDCP0_CUR_COLOR2 0x1A6D 1487#define mmDCP0_CUR_CONTROL 0x1A66 1488#define mmDCP0_CUR_HOT_SPOT 0x1A6B 1489#define mmDCP0_CUR_POSITION 0x1A6A 1490#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 1491#define mmDCP0_CUR_SIZE 0x1A68 1492#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 1493#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 1494#define mmDCP0_CUR_UPDATE 0x1A6E 1495#define mmDCP0_DC_LUT_30_COLOR 0x1A7C 1496#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F 1497#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 1498#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 1499#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 1500#define mmDCP0_DC_LUT_CONTROL 0x1A80 1501#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B 1502#define mmDCP0_DC_LUT_RW_INDEX 0x1A79 1503#define mmDCP0_DC_LUT_RW_MODE 0x1A78 1504#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A 1505#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D 1506#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 1507#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 1508#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 1509#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E 1510#define mmDCP0_DCP_CRC_CONTROL 0x1A87 1511#define mmDCP0_DCP_CRC_CURRENT 0x1A89 1512#define mmDCP0_DCP_CRC_LAST 0x1A8B 1513#define mmDCP0_DCP_CRC_MASK 0x1A88 1514#define mmDCP0_DCP_DEBUG 0x1A8D 1515#define mmDCP0_DCP_DEBUG2 0x1A98 1516#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 1517#define mmDCP0_DCP_GSL_CONTROL 0x1A90 1518#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 1519#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 1520#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 1521#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 1522#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 1523#define mmDCP0_DEGAMMA_CONTROL 0x1A58 1524#define mmDCP0_DENORM_CONTROL 0x1A50 1525#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A 1526#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B 1527#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C 1528#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D 1529#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E 1530#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F 1531#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 1532#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A 1533#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 1534#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B 1535#define mmDCP0_GRPH_CONTROL 0x1A01 1536#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 1537#define mmDCP0_GRPH_DFQ_STATUS 0x1A15 1538#define mmDCP0_GRPH_ENABLE 0x1A00 1539#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 1540#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 1541#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 1542#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 1543#define mmDCP0_GRPH_PITCH 0x1A06 1544#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 1545#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 1546#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 1547#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 1548#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 1549#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 1550#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 1551#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 1552#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A 1553#define mmDCP0_GRPH_SWAP_CNTL 0x1A03 1554#define mmDCP0_GRPH_UPDATE 0x1A11 1555#define mmDCP0_GRPH_X_END 0x1A0D 1556#define mmDCP0_GRPH_X_START 0x1A0B 1557#define mmDCP0_GRPH_Y_END 0x1A0E 1558#define mmDCP0_GRPH_Y_START 0x1A0C 1559#define mmDCP0_INPUT_CSC_C11_C12 0x1A36 1560#define mmDCP0_INPUT_CSC_C13_C14 0x1A37 1561#define mmDCP0_INPUT_CSC_C21_C22 0x1A38 1562#define mmDCP0_INPUT_CSC_C23_C24 0x1A39 1563#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A 1564#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B 1565#define mmDCP0_INPUT_CSC_CONTROL 0x1A35 1566#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 1567#define mmDCP0_KEY_CONTROL 0x1A53 1568#define mmDCP0_KEY_RANGE_ALPHA 0x1A54 1569#define mmDCP0_KEY_RANGE_BLUE 0x1A57 1570#define mmDCP0_KEY_RANGE_GREEN 0x1A56 1571#define mmDCP0_KEY_RANGE_RED 0x1A55 1572#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D 1573#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E 1574#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F 1575#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 1576#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 1577#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 1578#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C 1579#define mmDCP0_OUT_ROUND_CONTROL 0x1A51 1580#define mmDCP0_OVL_CONTROL1 0x1A1D 1581#define mmDCP0_OVL_CONTROL2 0x1A1E 1582#define mmDCP0_OVL_DFQ_CONTROL 0x1A29 1583#define mmDCP0_OVL_DFQ_STATUS 0x1A2A 1584#define mmDCP0_OVL_ENABLE 0x1A1C 1585#define mmDCP0_OVL_END 0x1A26 1586#define mmDCP0_OVL_PITCH 0x1A21 1587#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C 1588#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 1589#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 1590#define mmDCP0_OVL_START 0x1A25 1591#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 1592#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 1593#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 1594#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B 1595#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 1596#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 1597#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 1598#define mmDCP0_OVL_SWAP_CNTL 0x1A1F 1599#define mmDCP0_OVL_UPDATE 0x1A27 1600#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D 1601#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 1602#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 1603#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F 1604#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E 1605#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 1606#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 1607#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 1608#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 1609#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 1610#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 1611#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD 1612#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE 1613#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF 1614#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 1615#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA 1616#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB 1617#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC 1618#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 1619#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 1620#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 1621#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 1622#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 1623#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 1624#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA 1625#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB 1626#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 1627#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 1628#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 1629#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 1630#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 1631#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 1632#define mmDCP0_REGAMMA_CONTROL 0x1AA0 1633#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 1634#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 1635#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 1636#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 1637#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 1638#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 1639#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 1640#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 1641#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 1642#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 1643#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A 1644#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B 1645#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C 1646#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D 1647#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E 1648#define mmDCP1_CUR_COLOR1 0x1D6C 1649#define mmDCP1_CUR_COLOR2 0x1D6D 1650#define mmDCP1_CUR_CONTROL 0x1D66 1651#define mmDCP1_CUR_HOT_SPOT 0x1D6B 1652#define mmDCP1_CUR_POSITION 0x1D6A 1653#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 1654#define mmDCP1_CUR_SIZE 0x1D68 1655#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 1656#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 1657#define mmDCP1_CUR_UPDATE 0x1D6E 1658#define mmDCP1_DC_LUT_30_COLOR 0x1D7C 1659#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F 1660#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 1661#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 1662#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 1663#define mmDCP1_DC_LUT_CONTROL 0x1D80 1664#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B 1665#define mmDCP1_DC_LUT_RW_INDEX 0x1D79 1666#define mmDCP1_DC_LUT_RW_MODE 0x1D78 1667#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A 1668#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D 1669#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 1670#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 1671#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 1672#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E 1673#define mmDCP1_DCP_CRC_CONTROL 0x1D87 1674#define mmDCP1_DCP_CRC_CURRENT 0x1D89 1675#define mmDCP1_DCP_CRC_LAST 0x1D8B 1676#define mmDCP1_DCP_CRC_MASK 0x1D88 1677#define mmDCP1_DCP_DEBUG 0x1D8D 1678#define mmDCP1_DCP_DEBUG2 0x1D98 1679#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 1680#define mmDCP1_DCP_GSL_CONTROL 0x1D90 1681#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 1682#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 1683#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 1684#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 1685#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 1686#define mmDCP1_DEGAMMA_CONTROL 0x1D58 1687#define mmDCP1_DENORM_CONTROL 0x1D50 1688#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A 1689#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B 1690#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C 1691#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D 1692#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E 1693#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F 1694#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 1695#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A 1696#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 1697#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B 1698#define mmDCP1_GRPH_CONTROL 0x1D01 1699#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 1700#define mmDCP1_GRPH_DFQ_STATUS 0x1D15 1701#define mmDCP1_GRPH_ENABLE 0x1D00 1702#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 1703#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 1704#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 1705#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 1706#define mmDCP1_GRPH_PITCH 0x1D06 1707#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 1708#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 1709#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 1710#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 1711#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 1712#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 1713#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 1714#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 1715#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A 1716#define mmDCP1_GRPH_SWAP_CNTL 0x1D03 1717#define mmDCP1_GRPH_UPDATE 0x1D11 1718#define mmDCP1_GRPH_X_END 0x1D0D 1719#define mmDCP1_GRPH_X_START 0x1D0B 1720#define mmDCP1_GRPH_Y_END 0x1D0E 1721#define mmDCP1_GRPH_Y_START 0x1D0C 1722#define mmDCP1_INPUT_CSC_C11_C12 0x1D36 1723#define mmDCP1_INPUT_CSC_C13_C14 0x1D37 1724#define mmDCP1_INPUT_CSC_C21_C22 0x1D38 1725#define mmDCP1_INPUT_CSC_C23_C24 0x1D39 1726#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A 1727#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B 1728#define mmDCP1_INPUT_CSC_CONTROL 0x1D35 1729#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 1730#define mmDCP1_KEY_CONTROL 0x1D53 1731#define mmDCP1_KEY_RANGE_ALPHA 0x1D54 1732#define mmDCP1_KEY_RANGE_BLUE 0x1D57 1733#define mmDCP1_KEY_RANGE_GREEN 0x1D56 1734#define mmDCP1_KEY_RANGE_RED 0x1D55 1735#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D 1736#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E 1737#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F 1738#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 1739#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 1740#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 1741#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C 1742#define mmDCP1_OUT_ROUND_CONTROL 0x1D51 1743#define mmDCP1_OVL_CONTROL1 0x1D1D 1744#define mmDCP1_OVL_CONTROL2 0x1D1E 1745#define mmDCP1_OVL_DFQ_CONTROL 0x1D29 1746#define mmDCP1_OVL_DFQ_STATUS 0x1D2A 1747#define mmDCP1_OVL_ENABLE 0x1D1C 1748#define mmDCP1_OVL_END 0x1D26 1749#define mmDCP1_OVL_PITCH 0x1D21 1750#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C 1751#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 1752#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 1753#define mmDCP1_OVL_START 0x1D25 1754#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 1755#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 1756#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 1757#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B 1758#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 1759#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 1760#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 1761#define mmDCP1_OVL_SWAP_CNTL 0x1D1F 1762#define mmDCP1_OVL_UPDATE 0x1D27 1763#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D 1764#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 1765#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 1766#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F 1767#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E 1768#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 1769#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 1770#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 1771#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 1772#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 1773#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 1774#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD 1775#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE 1776#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF 1777#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 1778#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA 1779#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB 1780#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC 1781#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 1782#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 1783#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 1784#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 1785#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 1786#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 1787#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA 1788#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB 1789#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 1790#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 1791#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 1792#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 1793#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 1794#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 1795#define mmDCP1_REGAMMA_CONTROL 0x1DA0 1796#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 1797#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 1798#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 1799#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 1800#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 1801#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 1802#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 1803#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 1804#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 1805#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 1806#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A 1807#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B 1808#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C 1809#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D 1810#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E 1811#define mmDCP2_CUR_COLOR1 0x406C 1812#define mmDCP2_CUR_COLOR2 0x406D 1813#define mmDCP2_CUR_CONTROL 0x4066 1814#define mmDCP2_CUR_HOT_SPOT 0x406B 1815#define mmDCP2_CUR_POSITION 0x406A 1816#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 1817#define mmDCP2_CUR_SIZE 0x4068 1818#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 1819#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 1820#define mmDCP2_CUR_UPDATE 0x406E 1821#define mmDCP2_DC_LUT_30_COLOR 0x407C 1822#define mmDCP2_DC_LUT_AUTOFILL 0x407F 1823#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 1824#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 1825#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 1826#define mmDCP2_DC_LUT_CONTROL 0x4080 1827#define mmDCP2_DC_LUT_PWL_DATA 0x407B 1828#define mmDCP2_DC_LUT_RW_INDEX 0x4079 1829#define mmDCP2_DC_LUT_RW_MODE 0x4078 1830#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A 1831#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D 1832#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 1833#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 1834#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 1835#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E 1836#define mmDCP2_DCP_CRC_CONTROL 0x4087 1837#define mmDCP2_DCP_CRC_CURRENT 0x4089 1838#define mmDCP2_DCP_CRC_LAST 0x408B 1839#define mmDCP2_DCP_CRC_MASK 0x4088 1840#define mmDCP2_DCP_DEBUG 0x408D 1841#define mmDCP2_DCP_DEBUG2 0x4098 1842#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 1843#define mmDCP2_DCP_GSL_CONTROL 0x4090 1844#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 1845#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 1846#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 1847#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 1848#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 1849#define mmDCP2_DEGAMMA_CONTROL 0x4058 1850#define mmDCP2_DENORM_CONTROL 0x4050 1851#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A 1852#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B 1853#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C 1854#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D 1855#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E 1856#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F 1857#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 1858#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A 1859#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 1860#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B 1861#define mmDCP2_GRPH_CONTROL 0x4001 1862#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 1863#define mmDCP2_GRPH_DFQ_STATUS 0x4015 1864#define mmDCP2_GRPH_ENABLE 0x4000 1865#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 1866#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 1867#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 1868#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 1869#define mmDCP2_GRPH_PITCH 0x4006 1870#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 1871#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 1872#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 1873#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 1874#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 1875#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 1876#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 1877#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 1878#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A 1879#define mmDCP2_GRPH_SWAP_CNTL 0x4003 1880#define mmDCP2_GRPH_UPDATE 0x4011 1881#define mmDCP2_GRPH_X_END 0x400D 1882#define mmDCP2_GRPH_X_START 0x400B 1883#define mmDCP2_GRPH_Y_END 0x400E 1884#define mmDCP2_GRPH_Y_START 0x400C 1885#define mmDCP2_INPUT_CSC_C11_C12 0x4036 1886#define mmDCP2_INPUT_CSC_C13_C14 0x4037 1887#define mmDCP2_INPUT_CSC_C21_C22 0x4038 1888#define mmDCP2_INPUT_CSC_C23_C24 0x4039 1889#define mmDCP2_INPUT_CSC_C31_C32 0x403A 1890#define mmDCP2_INPUT_CSC_C33_C34 0x403B 1891#define mmDCP2_INPUT_CSC_CONTROL 0x4035 1892#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 1893#define mmDCP2_KEY_CONTROL 0x4053 1894#define mmDCP2_KEY_RANGE_ALPHA 0x4054 1895#define mmDCP2_KEY_RANGE_BLUE 0x4057 1896#define mmDCP2_KEY_RANGE_GREEN 0x4056 1897#define mmDCP2_KEY_RANGE_RED 0x4055 1898#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D 1899#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E 1900#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F 1901#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 1902#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 1903#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 1904#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C 1905#define mmDCP2_OUT_ROUND_CONTROL 0x4051 1906#define mmDCP2_OVL_CONTROL1 0x401D 1907#define mmDCP2_OVL_CONTROL2 0x401E 1908#define mmDCP2_OVL_DFQ_CONTROL 0x4029 1909#define mmDCP2_OVL_DFQ_STATUS 0x402A 1910#define mmDCP2_OVL_ENABLE 0x401C 1911#define mmDCP2_OVL_END 0x4026 1912#define mmDCP2_OVL_PITCH 0x4021 1913#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C 1914#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 1915#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 1916#define mmDCP2_OVL_START 0x4025 1917#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 1918#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 1919#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 1920#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B 1921#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 1922#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 1923#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 1924#define mmDCP2_OVL_SWAP_CNTL 0x401F 1925#define mmDCP2_OVL_UPDATE 0x4027 1926#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D 1927#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 1928#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 1929#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F 1930#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E 1931#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 1932#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 1933#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 1934#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 1935#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 1936#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 1937#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD 1938#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE 1939#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF 1940#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 1941#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA 1942#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB 1943#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC 1944#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 1945#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 1946#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 1947#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 1948#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 1949#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 1950#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA 1951#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB 1952#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 1953#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 1954#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 1955#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 1956#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 1957#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 1958#define mmDCP2_REGAMMA_CONTROL 0x40A0 1959#define mmDCP2_REGAMMA_LUT_DATA 0x40A2 1960#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 1961#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 1962#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 1963#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 1964#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 1965#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 1966#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 1967#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 1968#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 1969#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A 1970#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B 1971#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C 1972#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D 1973#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E 1974#define mmDCP3_CUR_COLOR1 0x436C 1975#define mmDCP3_CUR_COLOR2 0x436D 1976#define mmDCP3_CUR_CONTROL 0x4366 1977#define mmDCP3_CUR_HOT_SPOT 0x436B 1978#define mmDCP3_CUR_POSITION 0x436A 1979#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 1980#define mmDCP3_CUR_SIZE 0x4368 1981#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 1982#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 1983#define mmDCP3_CUR_UPDATE 0x436E 1984#define mmDCP3_DC_LUT_30_COLOR 0x437C 1985#define mmDCP3_DC_LUT_AUTOFILL 0x437F 1986#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 1987#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 1988#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 1989#define mmDCP3_DC_LUT_CONTROL 0x4380 1990#define mmDCP3_DC_LUT_PWL_DATA 0x437B 1991#define mmDCP3_DC_LUT_RW_INDEX 0x4379 1992#define mmDCP3_DC_LUT_RW_MODE 0x4378 1993#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A 1994#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D 1995#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 1996#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 1997#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 1998#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E 1999#define mmDCP3_DCP_CRC_CONTROL 0x4387 2000#define mmDCP3_DCP_CRC_CURRENT 0x4389
2001#define mmDCP3_DCP_CRC_LAST 0x438B 2002#define mmDCP3_DCP_CRC_MASK 0x4388 2003#define mmDCP3_DCP_DEBUG 0x438D 2004#define mmDCP3_DCP_DEBUG2 0x4398 2005#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 2006#define mmDCP3_DCP_GSL_CONTROL 0x4390 2007#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 2008#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 2009#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 2010#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 2011#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 2012#define mmDCP3_DEGAMMA_CONTROL 0x4358 2013#define mmDCP3_DENORM_CONTROL 0x4350 2014#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A 2015#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B 2016#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C 2017#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D 2018#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E 2019#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F 2020#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 2021#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A 2022#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 2023#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B 2024#define mmDCP3_GRPH_CONTROL 0x4301 2025#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 2026#define mmDCP3_GRPH_DFQ_STATUS 0x4315 2027#define mmDCP3_GRPH_ENABLE 0x4300 2028#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 2029#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 2030#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 2031#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 2032#define mmDCP3_GRPH_PITCH 0x4306 2033#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 2034#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 2035#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 2036#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 2037#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 2038#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 2039#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 2040#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 2041#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A 2042#define mmDCP3_GRPH_SWAP_CNTL 0x4303 2043#define mmDCP3_GRPH_UPDATE 0x4311 2044#define mmDCP3_GRPH_X_END 0x430D 2045#define mmDCP3_GRPH_X_START 0x430B 2046#define mmDCP3_GRPH_Y_END 0x430E 2047#define mmDCP3_GRPH_Y_START 0x430C 2048#define mmDCP3_INPUT_CSC_C11_C12 0x4336 2049#define mmDCP3_INPUT_CSC_C13_C14 0x4337 2050#define mmDCP3_INPUT_CSC_C21_C22 0x4338 2051#define mmDCP3_INPUT_CSC_C23_C24 0x4339 2052#define mmDCP3_INPUT_CSC_C31_C32 0x433A 2053#define mmDCP3_INPUT_CSC_C33_C34 0x433B 2054#define mmDCP3_INPUT_CSC_CONTROL 0x4335 2055#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 2056#define mmDCP3_KEY_CONTROL 0x4353 2057#define mmDCP3_KEY_RANGE_ALPHA 0x4354 2058#define mmDCP3_KEY_RANGE_BLUE 0x4357 2059#define mmDCP3_KEY_RANGE_GREEN 0x4356 2060#define mmDCP3_KEY_RANGE_RED 0x4355 2061#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D 2062#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E 2063#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F 2064#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 2065#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 2066#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 2067#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C 2068#define mmDCP3_OUT_ROUND_CONTROL 0x4351 2069#define mmDCP3_OVL_CONTROL1 0x431D 2070#define mmDCP3_OVL_CONTROL2 0x431E 2071#define mmDCP3_OVL_DFQ_CONTROL 0x4329 2072#define mmDCP3_OVL_DFQ_STATUS 0x432A 2073#define mmDCP3_OVL_ENABLE 0x431C 2074#define mmDCP3_OVL_END 0x4326 2075#define mmDCP3_OVL_PITCH 0x4321 2076#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C 2077#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 2078#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 2079#define mmDCP3_OVL_START 0x4325 2080#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 2081#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 2082#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 2083#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B 2084#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 2085#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 2086#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 2087#define mmDCP3_OVL_SWAP_CNTL 0x431F 2088#define mmDCP3_OVL_UPDATE 0x4327 2089#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D 2090#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 2091#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 2092#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F 2093#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E 2094#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 2095#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 2096#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 2097#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 2098#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 2099#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 2100#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD 2101#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE 2102#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF 2103#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 2104#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA 2105#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB 2106#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC 2107#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 2108#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 2109#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 2110#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 2111#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 2112#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 2113#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA 2114#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB 2115#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 2116#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 2117#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 2118#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 2119#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 2120#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 2121#define mmDCP3_REGAMMA_CONTROL 0x43A0 2122#define mmDCP3_REGAMMA_LUT_DATA 0x43A2 2123#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 2124#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 2125#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 2126#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 2127#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 2128#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 2129#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 2130#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 2131#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 2132#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A 2133#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B 2134#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C 2135#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D 2136#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E 2137#define mmDCP4_CUR_COLOR1 0x466C 2138#define mmDCP4_CUR_COLOR2 0x466D 2139#define mmDCP4_CUR_CONTROL 0x4666 2140#define mmDCP4_CUR_HOT_SPOT 0x466B 2141#define mmDCP4_CUR_POSITION 0x466A 2142#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 2143#define mmDCP4_CUR_SIZE 0x4668 2144#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 2145#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 2146#define mmDCP4_CUR_UPDATE 0x466E 2147#define mmDCP4_DC_LUT_30_COLOR 0x467C 2148#define mmDCP4_DC_LUT_AUTOFILL 0x467F 2149#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 2150#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 2151#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 2152#define mmDCP4_DC_LUT_CONTROL 0x4680 2153#define mmDCP4_DC_LUT_PWL_DATA 0x467B 2154#define mmDCP4_DC_LUT_RW_INDEX 0x4679 2155#define mmDCP4_DC_LUT_RW_MODE 0x4678 2156#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A 2157#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D 2158#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 2159#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 2160#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 2161#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E 2162#define mmDCP4_DCP_CRC_CONTROL 0x4687 2163#define mmDCP4_DCP_CRC_CURRENT 0x4689 2164#define mmDCP4_DCP_CRC_LAST 0x468B 2165#define mmDCP4_DCP_CRC_MASK 0x4688 2166#define mmDCP4_DCP_DEBUG 0x468D 2167#define mmDCP4_DCP_DEBUG2 0x4698 2168#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 2169#define mmDCP4_DCP_GSL_CONTROL 0x4690 2170#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 2171#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 2172#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 2173#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 2174#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 2175#define mmDCP4_DEGAMMA_CONTROL 0x4658 2176#define mmDCP4_DENORM_CONTROL 0x4650 2177#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A 2178#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B 2179#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C 2180#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D 2181#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E 2182#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F 2183#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 2184#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A 2185#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 2186#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B 2187#define mmDCP4_GRPH_CONTROL 0x4601 2188#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 2189#define mmDCP4_GRPH_DFQ_STATUS 0x4615 2190#define mmDCP4_GRPH_ENABLE 0x4600 2191#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 2192#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 2193#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 2194#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 2195#define mmDCP4_GRPH_PITCH 0x4606 2196#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 2197#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 2198#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 2199#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 2200#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 2201#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 2202#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 2203#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 2204#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A 2205#define mmDCP4_GRPH_SWAP_CNTL 0x4603 2206#define mmDCP4_GRPH_UPDATE 0x4611 2207#define mmDCP4_GRPH_X_END 0x460D 2208#define mmDCP4_GRPH_X_START 0x460B 2209#define mmDCP4_GRPH_Y_END 0x460E 2210#define mmDCP4_GRPH_Y_START 0x460C 2211#define mmDCP4_INPUT_CSC_C11_C12 0x4636 2212#define mmDCP4_INPUT_CSC_C13_C14 0x4637 2213#define mmDCP4_INPUT_CSC_C21_C22 0x4638 2214#define mmDCP4_INPUT_CSC_C23_C24 0x4639 2215#define mmDCP4_INPUT_CSC_C31_C32 0x463A 2216#define mmDCP4_INPUT_CSC_C33_C34 0x463B 2217#define mmDCP4_INPUT_CSC_CONTROL 0x4635 2218#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 2219#define mmDCP4_KEY_CONTROL 0x4653 2220#define mmDCP4_KEY_RANGE_ALPHA 0x4654 2221#define mmDCP4_KEY_RANGE_BLUE 0x4657 2222#define mmDCP4_KEY_RANGE_GREEN 0x4656 2223#define mmDCP4_KEY_RANGE_RED 0x4655 2224#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D 2225#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E 2226#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F 2227#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 2228#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 2229#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 2230#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C 2231#define mmDCP4_OUT_ROUND_CONTROL 0x4651 2232#define mmDCP4_OVL_CONTROL1 0x461D 2233#define mmDCP4_OVL_CONTROL2 0x461E 2234#define mmDCP4_OVL_DFQ_CONTROL 0x4629 2235#define mmDCP4_OVL_DFQ_STATUS 0x462A 2236#define mmDCP4_OVL_ENABLE 0x461C 2237#define mmDCP4_OVL_END 0x4626 2238#define mmDCP4_OVL_PITCH 0x4621 2239#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C 2240#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 2241#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 2242#define mmDCP4_OVL_START 0x4625 2243#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 2244#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 2245#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 2246#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B 2247#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 2248#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 2249#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 2250#define mmDCP4_OVL_SWAP_CNTL 0x461F 2251#define mmDCP4_OVL_UPDATE 0x4627 2252#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D 2253#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 2254#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 2255#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F 2256#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E 2257#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 2258#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 2259#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 2260#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 2261#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 2262#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 2263#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD 2264#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE 2265#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF 2266#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 2267#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA 2268#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB 2269#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC 2270#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 2271#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 2272#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 2273#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 2274#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 2275#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 2276#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA 2277#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB 2278#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 2279#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 2280#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 2281#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 2282#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 2283#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 2284#define mmDCP4_REGAMMA_CONTROL 0x46A0 2285#define mmDCP4_REGAMMA_LUT_DATA 0x46A2 2286#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 2287#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 2288#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 2289#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 2290#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 2291#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 2292#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 2293#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 2294#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 2295#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A 2296#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B 2297#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C 2298#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D 2299#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E 2300#define mmDCP5_CUR_COLOR1 0x496C 2301#define mmDCP5_CUR_COLOR2 0x496D 2302#define mmDCP5_CUR_CONTROL 0x4966 2303#define mmDCP5_CUR_HOT_SPOT 0x496B 2304#define mmDCP5_CUR_POSITION 0x496A 2305#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 2306#define mmDCP5_CUR_SIZE 0x4968 2307#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 2308#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 2309#define mmDCP5_CUR_UPDATE 0x496E 2310#define mmDCP5_DC_LUT_30_COLOR 0x497C 2311#define mmDCP5_DC_LUT_AUTOFILL 0x497F 2312#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 2313#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 2314#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 2315#define mmDCP5_DC_LUT_CONTROL 0x4980 2316#define mmDCP5_DC_LUT_PWL_DATA 0x497B 2317#define mmDCP5_DC_LUT_RW_INDEX 0x4979 2318#define mmDCP5_DC_LUT_RW_MODE 0x4978 2319#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A 2320#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D 2321#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 2322#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 2323#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 2324#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E 2325#define mmDCP5_DCP_CRC_CONTROL 0x4987 2326#define mmDCP5_DCP_CRC_CURRENT 0x4989 2327#define mmDCP5_DCP_CRC_LAST 0x498B 2328#define mmDCP5_DCP_CRC_MASK 0x4988 2329#define mmDCP5_DCP_DEBUG 0x498D 2330#define mmDCP5_DCP_DEBUG2 0x4998 2331#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 2332#define mmDCP5_DCP_GSL_CONTROL 0x4990 2333#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 2334#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 2335#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 2336#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 2337#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 2338#define mmDCP5_DEGAMMA_CONTROL 0x4958 2339#define mmDCP5_DENORM_CONTROL 0x4950 2340#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A 2341#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B 2342#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C 2343#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D 2344#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E 2345#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F 2346#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 2347#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A 2348#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 2349#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B 2350#define mmDCP5_GRPH_CONTROL 0x4901 2351#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 2352#define mmDCP5_GRPH_DFQ_STATUS 0x4915 2353#define mmDCP5_GRPH_ENABLE 0x4900 2354#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 2355#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 2356#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 2357#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 2358#define mmDCP5_GRPH_PITCH 0x4906 2359#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 2360#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 2361#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 2362#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 2363#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 2364#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 2365#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 2366#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 2367#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A 2368#define mmDCP5_GRPH_SWAP_CNTL 0x4903 2369#define mmDCP5_GRPH_UPDATE 0x4911 2370#define mmDCP5_GRPH_X_END 0x490D 2371#define mmDCP5_GRPH_X_START 0x490B 2372#define mmDCP5_GRPH_Y_END 0x490E 2373#define mmDCP5_GRPH_Y_START 0x490C 2374#define mmDCP5_INPUT_CSC_C11_C12 0x4936 2375#define mmDCP5_INPUT_CSC_C13_C14 0x4937 2376#define mmDCP5_INPUT_CSC_C21_C22 0x4938 2377#define mmDCP5_INPUT_CSC_C23_C24 0x4939 2378#define mmDCP5_INPUT_CSC_C31_C32 0x493A 2379#define mmDCP5_INPUT_CSC_C33_C34 0x493B 2380#define mmDCP5_INPUT_CSC_CONTROL 0x4935 2381#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 2382#define mmDCP5_KEY_CONTROL 0x4953 2383#define mmDCP5_KEY_RANGE_ALPHA 0x4954 2384#define mmDCP5_KEY_RANGE_BLUE 0x4957 2385#define mmDCP5_KEY_RANGE_GREEN 0x4956 2386#define mmDCP5_KEY_RANGE_RED 0x4955 2387#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D 2388#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E 2389#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F 2390#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 2391#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 2392#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 2393#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C 2394#define mmDCP5_OUT_ROUND_CONTROL 0x4951 2395#define mmDCP5_OVL_CONTROL1 0x491D 2396#define mmDCP5_OVL_CONTROL2 0x491E 2397#define mmDCP5_OVL_DFQ_CONTROL 0x4929 2398#define mmDCP5_OVL_DFQ_STATUS 0x492A 2399#define mmDCP5_OVL_ENABLE 0x491C 2400#define mmDCP5_OVL_END 0x4926 2401#define mmDCP5_OVL_PITCH 0x4921 2402#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C 2403#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 2404#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 2405#define mmDCP5_OVL_START 0x4925 2406#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 2407#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 2408#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 2409#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B 2410#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 2411#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 2412#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 2413#define mmDCP5_OVL_SWAP_CNTL 0x491F 2414#define mmDCP5_OVL_UPDATE 0x4927 2415#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D 2416#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 2417#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 2418#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F 2419#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E 2420#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 2421#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 2422#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 2423#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 2424#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 2425#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 2426#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD 2427#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE 2428#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF 2429#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 2430#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA 2431#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB 2432#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC 2433#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 2434#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 2435#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 2436#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 2437#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 2438#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 2439#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA 2440#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB 2441#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 2442#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 2443#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 2444#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 2445#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 2446#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 2447#define mmDCP5_REGAMMA_CONTROL 0x49A0 2448#define mmDCP5_REGAMMA_LUT_DATA 0x49A2 2449#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 2450#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 2451#define mmDC_PAD_EXTERN_SIG 0x1902 2452#define mmDCP_CRC_CONTROL 0x1A87 2453#define mmDCP_CRC_CURRENT 0x1A89 2454#define mmDCP_CRC_LAST 0x1A8B 2455#define mmDCP_CRC_MASK 0x1A88 2456#define mmDCP_DEBUG 0x1A8D 2457#define mmDCP_DEBUG2 0x1A98 2458#define mmDCP_FP_CONVERTED_FIELD 0x1A65 2459#define mmDC_PGCNTL_STATUS_REG 0x177E 2460#define mmDC_PGFSM_CONFIG_REG 0x177C 2461#define mmDC_PGFSM_WRITE_REG 0x177D 2462#define mmDCP_GSL_CONTROL 0x1A90 2463#define mmDCPG_TEST_DEBUG_DATA 0x177B 2464#define mmDCPG_TEST_DEBUG_INDEX 0x1779 2465#define mmDC_PINSTRAPS 0x1917 2466#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 2467#define mmDCP_RANDOM_SEEDS 0x1A61 2468#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 2469#define mmDCP_TEST_DEBUG_DATA 0x1A96 2470#define mmDCP_TEST_DEBUG_INDEX 0x1A95 2471#define mmDC_RBBMIF_RDWR_CNTL1 0x031A 2472#define mmDC_RBBMIF_RDWR_CNTL2 0x031D 2473#define mmDC_REF_CLK_CNTL 0x1903 2474#define mmDC_XDMA_INTERFACE_CNTL 0x0327 2475#define mmDEGAMMA_CONTROL 0x1A58 2476#define mmDENORM_CONTROL 0x1A50 2477#define mmDENTIST_DISPCLK_CNTL 0x0124 2478#define mmDIG0_AFMT_60958_0 0x1C41 2479#define mmDIG0_AFMT_60958_1 0x1C42 2480#define mmDIG0_AFMT_60958_2 0x1C48 2481#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 2482#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 2483#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 2484#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F 2485#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 2486#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B 2487#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 2488#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F 2489#define mmDIG0_AFMT_AVI_INFO0 0x1C21 2490#define mmDIG0_AFMT_AVI_INFO1 0x1C22 2491#define mmDIG0_AFMT_AVI_INFO2 0x1C23 2492#define mmDIG0_AFMT_AVI_INFO3 0x1C24 2493#define mmDIG0_AFMT_GENERIC_0 0x1C28 2494#define mmDIG0_AFMT_GENERIC_1 0x1C29 2495#define mmDIG0_AFMT_GENERIC_2 0x1C2A 2496#define mmDIG0_AFMT_GENERIC_3 0x1C2B 2497#define mmDIG0_AFMT_GENERIC_4 0x1C2C 2498#define mmDIG0_AFMT_GENERIC_5 0x1C2D 2499#define mmDIG0_AFMT_GENERIC_6 0x1C2E 2500#define mmDIG0_AFMT_GENERIC_7 0x1C2F 2501#define mmDIG0_AFMT_GENERIC_HDR 0x1C27 2502#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D 2503#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 2504#define mmDIG0_AFMT_ISRC1_0 0x1C18 2505#define mmDIG0_AFMT_ISRC1_1 0x1C19 2506#define mmDIG0_AFMT_ISRC1_2 0x1C1A 2507#define mmDIG0_AFMT_ISRC1_3 0x1C1B 2508#define mmDIG0_AFMT_ISRC1_4 0x1C1C 2509#define mmDIG0_AFMT_ISRC2_0 0x1C1D 2510#define mmDIG0_AFMT_ISRC2_1 0x1C1E 2511#define mmDIG0_AFMT_ISRC2_2 0x1C1F 2512#define mmDIG0_AFMT_ISRC2_3 0x1C20 2513#define mmDIG0_AFMT_MPEG_INFO0 0x1C25 2514#define mmDIG0_AFMT_MPEG_INFO1 0x1C26 2515#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 2516#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 2517#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 2518#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 2519#define mmDIG0_AFMT_STATUS 0x1C4A 2520#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C 2521#define mmDIG0_DIG_BE_CNTL 0x1C50 2522#define mmDIG0_DIG_BE_EN_CNTL 0x1C51 2523#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 2524#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 2525#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 2526#define mmDIG0_DIG_FE_CNTL 0x1C00 2527#define mmDIG0_DIG_FIFO_STATUS 0x1C0A 2528#define mmDIG0_DIG_LANE_ENABLE 0x1C8D 2529#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 2530#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 2531#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 2532#define mmDIG0_DIG_TEST_PATTERN 0x1C04 2533#define mmDIG0_HDMI_ACR_32_0 0x1C37 2534#define mmDIG0_HDMI_ACR_32_1 0x1C38 2535#define mmDIG0_HDMI_ACR_44_0 0x1C39 2536#define mmDIG0_HDMI_ACR_44_1 0x1C3A 2537#define mmDIG0_HDMI_ACR_48_0 0x1C3B 2538#define mmDIG0_HDMI_ACR_48_1 0x1C3C 2539#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F 2540#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D 2541#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E 2542#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E 2543#define mmDIG0_HDMI_CONTROL 0x1C0C 2544#define mmDIG0_HDMI_GC 0x1C16 2545#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 2546#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 2547#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 2548#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 2549#define mmDIG0_HDMI_STATUS 0x1C0D 2550#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 2551#define mmDIG0_LVDS_DATA_CNTL 0x1C8C 2552#define mmDIG0_TMDS_CNTL 0x1C7C 2553#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E 2554#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D 2555#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 2556#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 2557#define mmDIG0_TMDS_CTL_BITS 0x1C83 2558#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 2559#define mmDIG0_TMDS_DEBUG 0x1C82 2560#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F 2561#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 2562#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 2563#define mmDIG1_AFMT_60958_0 0x1F41 2564#define mmDIG1_AFMT_60958_1 0x1F42 2565#define mmDIG1_AFMT_60958_2 0x1F48 2566#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 2567#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 2568#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 2569#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F 2570#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 2571#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B 2572#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 2573#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F 2574#define mmDIG1_AFMT_AVI_INFO0 0x1F21 2575#define mmDIG1_AFMT_AVI_INFO1 0x1F22 2576#define mmDIG1_AFMT_AVI_INFO2 0x1F23 2577#define mmDIG1_AFMT_AVI_INFO3 0x1F24 2578#define mmDIG1_AFMT_GENERIC_0 0x1F28 2579#define mmDIG1_AFMT_GENERIC_1 0x1F29 2580#define mmDIG1_AFMT_GENERIC_2 0x1F2A 2581#define mmDIG1_AFMT_GENERIC_3 0x1F2B 2582#define mmDIG1_AFMT_GENERIC_4 0x1F2C 2583#define mmDIG1_AFMT_GENERIC_5 0x1F2D 2584#define mmDIG1_AFMT_GENERIC_6 0x1F2E 2585#define mmDIG1_AFMT_GENERIC_7 0x1F2F 2586#define mmDIG1_AFMT_GENERIC_HDR 0x1F27 2587#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D 2588#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 2589#define mmDIG1_AFMT_ISRC1_0 0x1F18 2590#define mmDIG1_AFMT_ISRC1_1 0x1F19 2591#define mmDIG1_AFMT_ISRC1_2 0x1F1A 2592#define mmDIG1_AFMT_ISRC1_3 0x1F1B 2593#define mmDIG1_AFMT_ISRC1_4 0x1F1C 2594#define mmDIG1_AFMT_ISRC2_0 0x1F1D 2595#define mmDIG1_AFMT_ISRC2_1 0x1F1E 2596#define mmDIG1_AFMT_ISRC2_2 0x1F1F 2597#define mmDIG1_AFMT_ISRC2_3 0x1F20 2598#define mmDIG1_AFMT_MPEG_INFO0 0x1F25 2599#define mmDIG1_AFMT_MPEG_INFO1 0x1F26 2600#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 2601#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 2602#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 2603#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 2604#define mmDIG1_AFMT_STATUS 0x1F4A 2605#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C 2606#define mmDIG1_DIG_BE_CNTL 0x1F50 2607#define mmDIG1_DIG_BE_EN_CNTL 0x1F51 2608#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 2609#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 2610#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 2611#define mmDIG1_DIG_FE_CNTL 0x1F00 2612#define mmDIG1_DIG_FIFO_STATUS 0x1F0A 2613#define mmDIG1_DIG_LANE_ENABLE 0x1F8D 2614#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 2615#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 2616#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 2617#define mmDIG1_DIG_TEST_PATTERN 0x1F04 2618#define mmDIG1_HDMI_ACR_32_0 0x1F37 2619#define mmDIG1_HDMI_ACR_32_1 0x1F38 2620#define mmDIG1_HDMI_ACR_44_0 0x1F39 2621#define mmDIG1_HDMI_ACR_44_1 0x1F3A 2622#define mmDIG1_HDMI_ACR_48_0 0x1F3B 2623#define mmDIG1_HDMI_ACR_48_1 0x1F3C 2624#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F 2625#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D 2626#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E 2627#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E 2628#define mmDIG1_HDMI_CONTROL 0x1F0C 2629#define mmDIG1_HDMI_GC 0x1F16 2630#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 2631#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 2632#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 2633#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 2634#define mmDIG1_HDMI_STATUS 0x1F0D 2635#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 2636#define mmDIG1_LVDS_DATA_CNTL 0x1F8C 2637#define mmDIG1_TMDS_CNTL 0x1F7C 2638#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E 2639#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D 2640#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 2641#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 2642#define mmDIG1_TMDS_CTL_BITS 0x1F83 2643#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 2644#define mmDIG1_TMDS_DEBUG 0x1F82 2645#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F 2646#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 2647#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 2648#define mmDIG2_AFMT_60958_0 0x4241 2649#define mmDIG2_AFMT_60958_1 0x4242 2650#define mmDIG2_AFMT_60958_2 0x4248 2651#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 2652#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 2653#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 2654#define mmDIG2_AFMT_AUDIO_INFO0 0x423F 2655#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 2656#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B 2657#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 2658#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F 2659#define mmDIG2_AFMT_AVI_INFO0 0x4221 2660#define mmDIG2_AFMT_AVI_INFO1 0x4222 2661#define mmDIG2_AFMT_AVI_INFO2 0x4223 2662#define mmDIG2_AFMT_AVI_INFO3 0x4224 2663#define mmDIG2_AFMT_GENERIC_0 0x4228 2664#define mmDIG2_AFMT_GENERIC_1 0x4229 2665#define mmDIG2_AFMT_GENERIC_2 0x422A 2666#define mmDIG2_AFMT_GENERIC_3 0x422B 2667#define mmDIG2_AFMT_GENERIC_4 0x422C 2668#define mmDIG2_AFMT_GENERIC_5 0x422D 2669#define mmDIG2_AFMT_GENERIC_6 0x422E 2670#define mmDIG2_AFMT_GENERIC_7 0x422F 2671#define mmDIG2_AFMT_GENERIC_HDR 0x4227 2672#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D 2673#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 2674#define mmDIG2_AFMT_ISRC1_0 0x4218 2675#define mmDIG2_AFMT_ISRC1_1 0x4219 2676#define mmDIG2_AFMT_ISRC1_2 0x421A 2677#define mmDIG2_AFMT_ISRC1_3 0x421B 2678#define mmDIG2_AFMT_ISRC1_4 0x421C 2679#define mmDIG2_AFMT_ISRC2_0 0x421D 2680#define mmDIG2_AFMT_ISRC2_1 0x421E 2681#define mmDIG2_AFMT_ISRC2_2 0x421F 2682#define mmDIG2_AFMT_ISRC2_3 0x4220 2683#define mmDIG2_AFMT_MPEG_INFO0 0x4225 2684#define mmDIG2_AFMT_MPEG_INFO1 0x4226 2685#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 2686#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 2687#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 2688#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 2689#define mmDIG2_AFMT_STATUS 0x424A 2690#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C 2691#define mmDIG2_DIG_BE_CNTL 0x4250 2692#define mmDIG2_DIG_BE_EN_CNTL 0x4251 2693#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 2694#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 2695#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 2696#define mmDIG2_DIG_FE_CNTL 0x4200 2697#define mmDIG2_DIG_FIFO_STATUS 0x420A 2698#define mmDIG2_DIG_LANE_ENABLE 0x428D 2699#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 2700#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 2701#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 2702#define mmDIG2_DIG_TEST_PATTERN 0x4204 2703#define mmDIG2_HDMI_ACR_32_0 0x4237 2704#define mmDIG2_HDMI_ACR_32_1 0x4238 2705#define mmDIG2_HDMI_ACR_44_0 0x4239 2706#define mmDIG2_HDMI_ACR_44_1 0x423A 2707#define mmDIG2_HDMI_ACR_48_0 0x423B 2708#define mmDIG2_HDMI_ACR_48_1 0x423C 2709#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F 2710#define mmDIG2_HDMI_ACR_STATUS_0 0x423D 2711#define mmDIG2_HDMI_ACR_STATUS_1 0x423E 2712#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E 2713#define mmDIG2_HDMI_CONTROL 0x420C 2714#define mmDIG2_HDMI_GC 0x4216 2715#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 2716#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 2717#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 2718#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 2719#define mmDIG2_HDMI_STATUS 0x420D 2720#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 2721#define mmDIG2_LVDS_DATA_CNTL 0x428C 2722#define mmDIG2_TMDS_CNTL 0x427C 2723#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E 2724#define mmDIG2_TMDS_CONTROL_CHAR 0x427D 2725#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 2726#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 2727#define mmDIG2_TMDS_CTL_BITS 0x4283 2728#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 2729#define mmDIG2_TMDS_DEBUG 0x4282 2730#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F 2731#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 2732#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 2733#define mmDIG3_AFMT_60958_0 0x4541 2734#define mmDIG3_AFMT_60958_1 0x4542 2735#define mmDIG3_AFMT_60958_2 0x4548 2736#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 2737#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 2738#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 2739#define mmDIG3_AFMT_AUDIO_INFO0 0x453F 2740#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 2741#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B 2742#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 2743#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F 2744#define mmDIG3_AFMT_AVI_INFO0 0x4521 2745#define mmDIG3_AFMT_AVI_INFO1 0x4522 2746#define mmDIG3_AFMT_AVI_INFO2 0x4523 2747#define mmDIG3_AFMT_AVI_INFO3 0x4524 2748#define mmDIG3_AFMT_GENERIC_0 0x4528 2749#define mmDIG3_AFMT_GENERIC_1 0x4529 2750#define mmDIG3_AFMT_GENERIC_2 0x452A 2751#define mmDIG3_AFMT_GENERIC_3 0x452B 2752#define mmDIG3_AFMT_GENERIC_4 0x452C 2753#define mmDIG3_AFMT_GENERIC_5 0x452D 2754#define mmDIG3_AFMT_GENERIC_6 0x452E 2755#define mmDIG3_AFMT_GENERIC_7 0x452F 2756#define mmDIG3_AFMT_GENERIC_HDR 0x4527 2757#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D 2758#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 2759#define mmDIG3_AFMT_ISRC1_0 0x4518 2760#define mmDIG3_AFMT_ISRC1_1 0x4519 2761#define mmDIG3_AFMT_ISRC1_2 0x451A 2762#define mmDIG3_AFMT_ISRC1_3 0x451B 2763#define mmDIG3_AFMT_ISRC1_4 0x451C 2764#define mmDIG3_AFMT_ISRC2_0 0x451D 2765#define mmDIG3_AFMT_ISRC2_1 0x451E 2766#define mmDIG3_AFMT_ISRC2_2 0x451F 2767#define mmDIG3_AFMT_ISRC2_3 0x4520 2768#define mmDIG3_AFMT_MPEG_INFO0 0x4525 2769#define mmDIG3_AFMT_MPEG_INFO1 0x4526 2770#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 2771#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 2772#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 2773#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 2774#define mmDIG3_AFMT_STATUS 0x454A 2775#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C 2776#define mmDIG3_DIG_BE_CNTL 0x4550 2777#define mmDIG3_DIG_BE_EN_CNTL 0x4551 2778#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 2779#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 2780#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 2781#define mmDIG3_DIG_FE_CNTL 0x4500 2782#define mmDIG3_DIG_FIFO_STATUS 0x450A 2783#define mmDIG3_DIG_LANE_ENABLE 0x458D 2784#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 2785#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 2786#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 2787#define mmDIG3_DIG_TEST_PATTERN 0x4504 2788#define mmDIG3_HDMI_ACR_32_0 0x4537 2789#define mmDIG3_HDMI_ACR_32_1 0x4538 2790#define mmDIG3_HDMI_ACR_44_0 0x4539 2791#define mmDIG3_HDMI_ACR_44_1 0x453A 2792#define mmDIG3_HDMI_ACR_48_0 0x453B 2793#define mmDIG3_HDMI_ACR_48_1 0x453C 2794#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F 2795#define mmDIG3_HDMI_ACR_STATUS_0 0x453D 2796#define mmDIG3_HDMI_ACR_STATUS_1 0x453E 2797#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E 2798#define mmDIG3_HDMI_CONTROL 0x450C 2799#define mmDIG3_HDMI_GC 0x4516 2800#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 2801#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 2802#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 2803#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 2804#define mmDIG3_HDMI_STATUS 0x450D 2805#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 2806#define mmDIG3_LVDS_DATA_CNTL 0x458C 2807#define mmDIG3_TMDS_CNTL 0x457C 2808#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E 2809#define mmDIG3_TMDS_CONTROL_CHAR 0x457D 2810#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 2811#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 2812#define mmDIG3_TMDS_CTL_BITS 0x4583 2813#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 2814#define mmDIG3_TMDS_DEBUG 0x4582 2815#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F 2816#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 2817#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 2818#define mmDIG4_AFMT_60958_0 0x4841 2819#define mmDIG4_AFMT_60958_1 0x4842 2820#define mmDIG4_AFMT_60958_2 0x4848 2821#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 2822#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 2823#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 2824#define mmDIG4_AFMT_AUDIO_INFO0 0x483F 2825#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 2826#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B 2827#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 2828#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F 2829#define mmDIG4_AFMT_AVI_INFO0 0x4821 2830#define mmDIG4_AFMT_AVI_INFO1 0x4822 2831#define mmDIG4_AFMT_AVI_INFO2 0x4823 2832#define mmDIG4_AFMT_AVI_INFO3 0x4824 2833#define mmDIG4_AFMT_GENERIC_0 0x4828 2834#define mmDIG4_AFMT_GENERIC_1 0x4829 2835#define mmDIG4_AFMT_GENERIC_2 0x482A 2836#define mmDIG4_AFMT_GENERIC_3 0x482B 2837#define mmDIG4_AFMT_GENERIC_4 0x482C 2838#define mmDIG4_AFMT_GENERIC_5 0x482D 2839#define mmDIG4_AFMT_GENERIC_6 0x482E 2840#define mmDIG4_AFMT_GENERIC_7 0x482F 2841#define mmDIG4_AFMT_GENERIC_HDR 0x4827 2842#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D 2843#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 2844#define mmDIG4_AFMT_ISRC1_0 0x4818 2845#define mmDIG4_AFMT_ISRC1_1 0x4819 2846#define mmDIG4_AFMT_ISRC1_2 0x481A 2847#define mmDIG4_AFMT_ISRC1_3 0x481B 2848#define mmDIG4_AFMT_ISRC1_4 0x481C 2849#define mmDIG4_AFMT_ISRC2_0 0x481D 2850#define mmDIG4_AFMT_ISRC2_1 0x481E 2851#define mmDIG4_AFMT_ISRC2_2 0x481F 2852#define mmDIG4_AFMT_ISRC2_3 0x4820 2853#define mmDIG4_AFMT_MPEG_INFO0 0x4825 2854#define mmDIG4_AFMT_MPEG_INFO1 0x4826 2855#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 2856#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 2857#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 2858#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 2859#define mmDIG4_AFMT_STATUS 0x484A 2860#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C 2861#define mmDIG4_DIG_BE_CNTL 0x4850 2862#define mmDIG4_DIG_BE_EN_CNTL 0x4851 2863#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 2864#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 2865#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 2866#define mmDIG4_DIG_FE_CNTL 0x4800 2867#define mmDIG4_DIG_FIFO_STATUS 0x480A 2868#define mmDIG4_DIG_LANE_ENABLE 0x488D 2869#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 2870#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 2871#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 2872#define mmDIG4_DIG_TEST_PATTERN 0x4804 2873#define mmDIG4_HDMI_ACR_32_0 0x4837 2874#define mmDIG4_HDMI_ACR_32_1 0x4838 2875#define mmDIG4_HDMI_ACR_44_0 0x4839 2876#define mmDIG4_HDMI_ACR_44_1 0x483A 2877#define mmDIG4_HDMI_ACR_48_0 0x483B 2878#define mmDIG4_HDMI_ACR_48_1 0x483C 2879#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F 2880#define mmDIG4_HDMI_ACR_STATUS_0 0x483D 2881#define mmDIG4_HDMI_ACR_STATUS_1 0x483E 2882#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E 2883#define mmDIG4_HDMI_CONTROL 0x480C 2884#define mmDIG4_HDMI_GC 0x4816 2885#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 2886#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 2887#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 2888#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 2889#define mmDIG4_HDMI_STATUS 0x480D 2890#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 2891#define mmDIG4_LVDS_DATA_CNTL 0x488C 2892#define mmDIG4_TMDS_CNTL 0x487C 2893#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E 2894#define mmDIG4_TMDS_CONTROL_CHAR 0x487D 2895#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 2896#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 2897#define mmDIG4_TMDS_CTL_BITS 0x4883 2898#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 2899#define mmDIG4_TMDS_DEBUG 0x4882 2900#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F 2901#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 2902#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 2903#define mmDIG5_AFMT_60958_0 0x4B41 2904#define mmDIG5_AFMT_60958_1 0x4B42 2905#define mmDIG5_AFMT_60958_2 0x4B48 2906#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 2907#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 2908#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 2909#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F 2910#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 2911#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B 2912#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 2913#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F 2914#define mmDIG5_AFMT_AVI_INFO0 0x4B21 2915#define mmDIG5_AFMT_AVI_INFO1 0x4B22 2916#define mmDIG5_AFMT_AVI_INFO2 0x4B23 2917#define mmDIG5_AFMT_AVI_INFO3 0x4B24 2918#define mmDIG5_AFMT_GENERIC_0 0x4B28 2919#define mmDIG5_AFMT_GENERIC_1 0x4B29 2920#define mmDIG5_AFMT_GENERIC_2 0x4B2A 2921#define mmDIG5_AFMT_GENERIC_3 0x4B2B 2922#define mmDIG5_AFMT_GENERIC_4 0x4B2C 2923#define mmDIG5_AFMT_GENERIC_5 0x4B2D 2924#define mmDIG5_AFMT_GENERIC_6 0x4B2E 2925#define mmDIG5_AFMT_GENERIC_7 0x4B2F 2926#define mmDIG5_AFMT_GENERIC_HDR 0x4B27 2927#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D 2928#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 2929#define mmDIG5_AFMT_ISRC1_0 0x4B18 2930#define mmDIG5_AFMT_ISRC1_1 0x4B19 2931#define mmDIG5_AFMT_ISRC1_2 0x4B1A 2932#define mmDIG5_AFMT_ISRC1_3 0x4B1B 2933#define mmDIG5_AFMT_ISRC1_4 0x4B1C 2934#define mmDIG5_AFMT_ISRC2_0 0x4B1D 2935#define mmDIG5_AFMT_ISRC2_1 0x4B1E 2936#define mmDIG5_AFMT_ISRC2_2 0x4B1F 2937#define mmDIG5_AFMT_ISRC2_3 0x4B20 2938#define mmDIG5_AFMT_MPEG_INFO0 0x4B25 2939#define mmDIG5_AFMT_MPEG_INFO1 0x4B26 2940#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 2941#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 2942#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 2943#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 2944#define mmDIG5_AFMT_STATUS 0x4B4A 2945#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C 2946#define mmDIG5_DIG_BE_CNTL 0x4B50 2947#define mmDIG5_DIG_BE_EN_CNTL 0x4B51 2948#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 2949#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 2950#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 2951#define mmDIG5_DIG_FE_CNTL 0x4B00 2952#define mmDIG5_DIG_FIFO_STATUS 0x4B0A 2953#define mmDIG5_DIG_LANE_ENABLE 0x4B8D 2954#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 2955#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 2956#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 2957#define mmDIG5_DIG_TEST_PATTERN 0x4B04 2958#define mmDIG5_HDMI_ACR_32_0 0x4B37 2959#define mmDIG5_HDMI_ACR_32_1 0x4B38 2960#define mmDIG5_HDMI_ACR_44_0 0x4B39 2961#define mmDIG5_HDMI_ACR_44_1 0x4B3A 2962#define mmDIG5_HDMI_ACR_48_0 0x4B3B 2963#define mmDIG5_HDMI_ACR_48_1 0x4B3C 2964#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F 2965#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D 2966#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E 2967#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E 2968#define mmDIG5_HDMI_CONTROL 0x4B0C 2969#define mmDIG5_HDMI_GC 0x4B16 2970#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 2971#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 2972#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 2973#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 2974#define mmDIG5_HDMI_STATUS 0x4B0D 2975#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 2976#define mmDIG5_LVDS_DATA_CNTL 0x4B8C 2977#define mmDIG5_TMDS_CNTL 0x4B7C 2978#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E 2979#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D 2980#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 2981#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 2982#define mmDIG5_TMDS_CTL_BITS 0x4B83 2983#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 2984#define mmDIG5_TMDS_DEBUG 0x4B82 2985#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F 2986#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 2987#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 2988#define mmDIG_BE_CNTL 0x1C50 2989#define mmDIG_BE_EN_CNTL 0x1C51 2990#define mmDIG_CLOCK_PATTERN 0x1C03 2991#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 2992#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 2993#define mmDIG_FE_CNTL 0x1C00 2994#define mmDIG_FIFO_STATUS 0x1C0A 2995#define mmDIG_LANE_ENABLE 0x1C8D 2996#define mmDIG_OUTPUT_CRC_CNTL 0x1C01 2997#define mmDIG_OUTPUT_CRC_RESULT 0x1C02 2998#define mmDIG_RANDOM_PATTERN_SEED 0x1C05 2999#define mmDIG_SOFT_RESET 0x013D 3000#define mmDIG_TEST_PATTERN 0x1C04
3001#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 3002#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 3003#define mmDISP_INTERRUPT_STATUS 0x183D 3004#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E 3005#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F 3006#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 3007#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 3008#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 3009#define mmDISPOUT_STEREOSYNC_SEL 0x18BF 3010#define mmDISPPLL_BG_CNTL 0x013C 3011#define mmDISP_TIMER_CONTROL 0x1842 3012#define mmDMCU_CTRL 0x1600 3013#define mmDMCU_ERAM_RD_CTRL 0x160B 3014#define mmDMCU_ERAM_RD_DATA 0x160C 3015#define mmDMCU_ERAM_WR_CTRL 0x1609 3016#define mmDMCU_ERAM_WR_DATA 0x160A 3017#define mmDMCU_EVENT_TRIGGER 0x1611 3018#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A 3019#define mmDMCU_FW_CS_HI 0x1606 3020#define mmDMCU_FW_CS_LO 0x1607 3021#define mmDMCU_FW_END_ADDR 0x1604 3022#define mmDMCU_FW_ISR_START_ADDR 0x1605 3023#define mmDMCU_FW_START_ADDR 0x1603 3024#define mmDMCU_INT_CNT 0x1619 3025#define mmDMCU_INTERRUPT_STATUS 0x1614 3026#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 3027#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 3028#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 3029#define mmDMCU_IRAM_RD_CTRL 0x160F 3030#define mmDMCU_IRAM_RD_DATA 0x1610 3031#define mmDMCU_IRAM_WR_CTRL 0x160D 3032#define mmDMCU_IRAM_WR_DATA 0x160E 3033#define mmDMCU_PC_START_ADDR 0x1602 3034#define mmDMCU_RAM_ACCESS_CTRL 0x1608 3035#define mmDMCU_STATUS 0x1601 3036#define mmDMCU_TEST_DEBUG_DATA 0x1627 3037#define mmDMCU_TEST_DEBUG_INDEX 0x1626 3038#define mmDMCU_UC_CLK_GATING_CNTL 0x161B 3039#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 3040#define mmDMIF_ADDR_CALC 0x0300 3041#define mmDMIF_ADDR_CONFIG 0x02F5 3042#define mmDMIF_ARBITRATION_CONTROL 0x02F9 3043#define mmDMIF_CONTROL 0x02F6 3044#define mmDMIF_HW_DEBUG 0x02F8 3045#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 3046#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 3047#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 3048#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 3049#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 3050#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 3051#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 3052#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 3053#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 3054#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 3055#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 3056#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 3057#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 3058#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 3059#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 3060#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 3061#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 3062#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 3063#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 3064#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 3065#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 3066#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 3067#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 3068#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 3069#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 3070#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 3071#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 3072#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 3073#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 3074#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 3075#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 3076#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 3077#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 3078#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 3079#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 3080#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 3081#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 3082#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 3083#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 3084#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 3085#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 3086#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 3087#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 3088#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 3089#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 3090#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 3091#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 3092#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 3093#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 3094#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 3095#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 3096#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 3097#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 3098#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 3099#define mmDMIF_STATUS 0x02F7 3100#define mmDMIF_STATUS2 0x0301 3101#define mmDMIF_TEST_DEBUG_DATA 0x0313 3102#define mmDMIF_TEST_DEBUG_INDEX 0x0312 3103#define mmDOUT_DCE_VCE_CONTROL 0x18FF 3104#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 3105#define mmDOUT_SCRATCH0 0x1844 3106#define mmDOUT_SCRATCH1 0x1845 3107#define mmDOUT_SCRATCH2 0x1846 3108#define mmDOUT_SCRATCH3 0x1847 3109#define mmDOUT_SCRATCH4 0x1848 3110#define mmDOUT_SCRATCH5 0x1849 3111#define mmDOUT_SCRATCH6 0x184A 3112#define mmDOUT_SCRATCH7 0x184B 3113#define mmDOUT_TEST_DEBUG_DATA 0x184E 3114#define mmDOUT_TEST_DEBUG_INDEX 0x184D 3115#define mmDP0_DP_CONFIG 0x1CC2 3116#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 3117#define mmDP0_DP_DPHY_CNTL 0x1CD0 3118#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 3119#define mmDP0_DP_DPHY_CRC_EN 0x1CD6 3120#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 3121#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 3122#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 3123#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 3124#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 3125#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 3126#define mmDP0_DP_DPHY_SYM0 0x1CD2 3127#define mmDP0_DP_DPHY_SYM1 0x1CE0 3128#define mmDP0_DP_DPHY_SYM2 0x1CDF 3129#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 3130#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 3131#define mmDP0_DP_LINK_CNTL 0x1CC0 3132#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC 3133#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA 3134#define mmDP0_DP_MSA_MISC 0x1CC5 3135#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA 3136#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB 3137#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 3138#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB 3139#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 3140#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 3141#define mmDP0_DP_MSE_SAT0 0x1CE4 3142#define mmDP0_DP_MSE_SAT1 0x1CE5 3143#define mmDP0_DP_MSE_SAT2 0x1CE6 3144#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 3145#define mmDP0_DP_PIXEL_FORMAT 0x1CC1 3146#define mmDP0_DP_SEC_AUD_M 0x1CA7 3147#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 3148#define mmDP0_DP_SEC_AUD_N 0x1CA5 3149#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 3150#define mmDP0_DP_SEC_CNTL 0x1CA0 3151#define mmDP0_DP_SEC_CNTL1 0x1CAB 3152#define mmDP0_DP_SEC_FRAMING1 0x1CA1 3153#define mmDP0_DP_SEC_FRAMING2 0x1CA2 3154#define mmDP0_DP_SEC_FRAMING3 0x1CA3 3155#define mmDP0_DP_SEC_FRAMING4 0x1CA4 3156#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA 3157#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 3158#define mmDP0_DP_STEER_FIFO 0x1CC4 3159#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD 3160#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC 3161#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF 3162#define mmDP0_DP_VID_M 0x1CCB 3163#define mmDP0_DP_VID_MSA_VBID 0x1CCD 3164#define mmDP0_DP_VID_N 0x1CCA 3165#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 3166#define mmDP0_DP_VID_TIMING 0x1CC9 3167#define mmDP1_DP_CONFIG 0x1FC2 3168#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 3169#define mmDP1_DP_DPHY_CNTL 0x1FD0 3170#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 3171#define mmDP1_DP_DPHY_CRC_EN 0x1FD6 3172#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 3173#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 3174#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 3175#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 3176#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 3177#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 3178#define mmDP1_DP_DPHY_SYM0 0x1FD2 3179#define mmDP1_DP_DPHY_SYM1 0x1FE0 3180#define mmDP1_DP_DPHY_SYM2 0x1FDF 3181#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 3182#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 3183#define mmDP1_DP_LINK_CNTL 0x1FC0 3184#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC 3185#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA 3186#define mmDP1_DP_MSA_MISC 0x1FC5 3187#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA 3188#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB 3189#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 3190#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB 3191#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 3192#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 3193#define mmDP1_DP_MSE_SAT0 0x1FE4 3194#define mmDP1_DP_MSE_SAT1 0x1FE5 3195#define mmDP1_DP_MSE_SAT2 0x1FE6 3196#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 3197#define mmDP1_DP_PIXEL_FORMAT 0x1FC1 3198#define mmDP1_DP_SEC_AUD_M 0x1FA7 3199#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 3200#define mmDP1_DP_SEC_AUD_N 0x1FA5 3201#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 3202#define mmDP1_DP_SEC_CNTL 0x1FA0 3203#define mmDP1_DP_SEC_CNTL1 0x1FAB 3204#define mmDP1_DP_SEC_FRAMING1 0x1FA1 3205#define mmDP1_DP_SEC_FRAMING2 0x1FA2 3206#define mmDP1_DP_SEC_FRAMING3 0x1FA3 3207#define mmDP1_DP_SEC_FRAMING4 0x1FA4 3208#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA 3209#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 3210#define mmDP1_DP_STEER_FIFO 0x1FC4 3211#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD 3212#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC 3213#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF 3214#define mmDP1_DP_VID_M 0x1FCB 3215#define mmDP1_DP_VID_MSA_VBID 0x1FCD 3216#define mmDP1_DP_VID_N 0x1FCA 3217#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 3218#define mmDP1_DP_VID_TIMING 0x1FC9 3219#define mmDP2_DP_CONFIG 0x42C2 3220#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 3221#define mmDP2_DP_DPHY_CNTL 0x42D0 3222#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 3223#define mmDP2_DP_DPHY_CRC_EN 0x42D6 3224#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 3225#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 3226#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 3227#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 3228#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 3229#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 3230#define mmDP2_DP_DPHY_SYM0 0x42D2 3231#define mmDP2_DP_DPHY_SYM1 0x42E0 3232#define mmDP2_DP_DPHY_SYM2 0x42DF 3233#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 3234#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 3235#define mmDP2_DP_LINK_CNTL 0x42C0 3236#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC 3237#define mmDP2_DP_MSA_COLORIMETRY 0x42DA 3238#define mmDP2_DP_MSA_MISC 0x42C5 3239#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA 3240#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB 3241#define mmDP2_DP_MSE_LINK_TIMING 0x42E8 3242#define mmDP2_DP_MSE_MISC_CNTL 0x42DB 3243#define mmDP2_DP_MSE_RATE_CNTL 0x42E1 3244#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 3245#define mmDP2_DP_MSE_SAT0 0x42E4 3246#define mmDP2_DP_MSE_SAT1 0x42E5 3247#define mmDP2_DP_MSE_SAT2 0x42E6 3248#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 3249#define mmDP2_DP_PIXEL_FORMAT 0x42C1 3250#define mmDP2_DP_SEC_AUD_M 0x42A7 3251#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 3252#define mmDP2_DP_SEC_AUD_N 0x42A5 3253#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 3254#define mmDP2_DP_SEC_CNTL 0x42A0 3255#define mmDP2_DP_SEC_CNTL1 0x42AB 3256#define mmDP2_DP_SEC_FRAMING1 0x42A1 3257#define mmDP2_DP_SEC_FRAMING2 0x42A2 3258#define mmDP2_DP_SEC_FRAMING3 0x42A3 3259#define mmDP2_DP_SEC_FRAMING4 0x42A4 3260#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA 3261#define mmDP2_DP_SEC_TIMESTAMP 0x42A9 3262#define mmDP2_DP_STEER_FIFO 0x42C4 3263#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD 3264#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC 3265#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF 3266#define mmDP2_DP_VID_M 0x42CB 3267#define mmDP2_DP_VID_MSA_VBID 0x42CD 3268#define mmDP2_DP_VID_N 0x42CA 3269#define mmDP2_DP_VID_STREAM_CNTL 0x42C3 3270#define mmDP2_DP_VID_TIMING 0x42C9 3271#define mmDP3_DP_CONFIG 0x45C2 3272#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 3273#define mmDP3_DP_DPHY_CNTL 0x45D0 3274#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 3275#define mmDP3_DP_DPHY_CRC_EN 0x45D6 3276#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 3277#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 3278#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 3279#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 3280#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 3281#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 3282#define mmDP3_DP_DPHY_SYM0 0x45D2 3283#define mmDP3_DP_DPHY_SYM1 0x45E0 3284#define mmDP3_DP_DPHY_SYM2 0x45DF 3285#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 3286#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 3287#define mmDP3_DP_LINK_CNTL 0x45C0 3288#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC 3289#define mmDP3_DP_MSA_COLORIMETRY 0x45DA 3290#define mmDP3_DP_MSA_MISC 0x45C5 3291#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA 3292#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB 3293#define mmDP3_DP_MSE_LINK_TIMING 0x45E8 3294#define mmDP3_DP_MSE_MISC_CNTL 0x45DB 3295#define mmDP3_DP_MSE_RATE_CNTL 0x45E1 3296#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 3297#define mmDP3_DP_MSE_SAT0 0x45E4 3298#define mmDP3_DP_MSE_SAT1 0x45E5 3299#define mmDP3_DP_MSE_SAT2 0x45E6 3300#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 3301#define mmDP3_DP_PIXEL_FORMAT 0x45C1 3302#define mmDP3_DP_SEC_AUD_M 0x45A7 3303#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 3304#define mmDP3_DP_SEC_AUD_N 0x45A5 3305#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 3306#define mmDP3_DP_SEC_CNTL 0x45A0 3307#define mmDP3_DP_SEC_CNTL1 0x45AB 3308#define mmDP3_DP_SEC_FRAMING1 0x45A1 3309#define mmDP3_DP_SEC_FRAMING2 0x45A2 3310#define mmDP3_DP_SEC_FRAMING3 0x45A3 3311#define mmDP3_DP_SEC_FRAMING4 0x45A4 3312#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA 3313#define mmDP3_DP_SEC_TIMESTAMP 0x45A9 3314#define mmDP3_DP_STEER_FIFO 0x45C4 3315#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD 3316#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC 3317#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF 3318#define mmDP3_DP_VID_M 0x45CB 3319#define mmDP3_DP_VID_MSA_VBID 0x45CD 3320#define mmDP3_DP_VID_N 0x45CA 3321#define mmDP3_DP_VID_STREAM_CNTL 0x45C3 3322#define mmDP3_DP_VID_TIMING 0x45C9 3323#define mmDP4_DP_CONFIG 0x48C2 3324#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 3325#define mmDP4_DP_DPHY_CNTL 0x48D0 3326#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 3327#define mmDP4_DP_DPHY_CRC_EN 0x48D6 3328#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 3329#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 3330#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 3331#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 3332#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 3333#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 3334#define mmDP4_DP_DPHY_SYM0 0x48D2 3335#define mmDP4_DP_DPHY_SYM1 0x48E0 3336#define mmDP4_DP_DPHY_SYM2 0x48DF 3337#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 3338#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 3339#define mmDP4_DP_LINK_CNTL 0x48C0 3340#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC 3341#define mmDP4_DP_MSA_COLORIMETRY 0x48DA 3342#define mmDP4_DP_MSA_MISC 0x48C5 3343#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA 3344#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB 3345#define mmDP4_DP_MSE_LINK_TIMING 0x48E8 3346#define mmDP4_DP_MSE_MISC_CNTL 0x48DB 3347#define mmDP4_DP_MSE_RATE_CNTL 0x48E1 3348#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 3349#define mmDP4_DP_MSE_SAT0 0x48E4 3350#define mmDP4_DP_MSE_SAT1 0x48E5 3351#define mmDP4_DP_MSE_SAT2 0x48E6 3352#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 3353#define mmDP4_DP_PIXEL_FORMAT 0x48C1 3354#define mmDP4_DP_SEC_AUD_M 0x48A7 3355#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 3356#define mmDP4_DP_SEC_AUD_N 0x48A5 3357#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 3358#define mmDP4_DP_SEC_CNTL 0x48A0 3359#define mmDP4_DP_SEC_CNTL1 0x48AB 3360#define mmDP4_DP_SEC_FRAMING1 0x48A1 3361#define mmDP4_DP_SEC_FRAMING2 0x48A2 3362#define mmDP4_DP_SEC_FRAMING3 0x48A3 3363#define mmDP4_DP_SEC_FRAMING4 0x48A4 3364#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA 3365#define mmDP4_DP_SEC_TIMESTAMP 0x48A9 3366#define mmDP4_DP_STEER_FIFO 0x48C4 3367#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD 3368#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC 3369#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF 3370#define mmDP4_DP_VID_M 0x48CB 3371#define mmDP4_DP_VID_MSA_VBID 0x48CD 3372#define mmDP4_DP_VID_N 0x48CA 3373#define mmDP4_DP_VID_STREAM_CNTL 0x48C3 3374#define mmDP4_DP_VID_TIMING 0x48C9 3375#define mmDP5_DP_CONFIG 0x4BC2 3376#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 3377#define mmDP5_DP_DPHY_CNTL 0x4BD0 3378#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 3379#define mmDP5_DP_DPHY_CRC_EN 0x4BD6 3380#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 3381#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 3382#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 3383#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 3384#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 3385#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 3386#define mmDP5_DP_DPHY_SYM0 0x4BD2 3387#define mmDP5_DP_DPHY_SYM1 0x4BE0 3388#define mmDP5_DP_DPHY_SYM2 0x4BDF 3389#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 3390#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 3391#define mmDP5_DP_LINK_CNTL 0x4BC0 3392#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC 3393#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA 3394#define mmDP5_DP_MSA_MISC 0x4BC5 3395#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA 3396#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB 3397#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 3398#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB 3399#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 3400#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 3401#define mmDP5_DP_MSE_SAT0 0x4BE4 3402#define mmDP5_DP_MSE_SAT1 0x4BE5 3403#define mmDP5_DP_MSE_SAT2 0x4BE6 3404#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 3405#define mmDP5_DP_PIXEL_FORMAT 0x4BC1 3406#define mmDP5_DP_SEC_AUD_M 0x4BA7 3407#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 3408#define mmDP5_DP_SEC_AUD_N 0x4BA5 3409#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 3410#define mmDP5_DP_SEC_CNTL 0x4BA0 3411#define mmDP5_DP_SEC_CNTL1 0x4BAB 3412#define mmDP5_DP_SEC_FRAMING1 0x4BA1 3413#define mmDP5_DP_SEC_FRAMING2 0x4BA2 3414#define mmDP5_DP_SEC_FRAMING3 0x4BA3 3415#define mmDP5_DP_SEC_FRAMING4 0x4BA4 3416#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA 3417#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 3418#define mmDP5_DP_STEER_FIFO 0x4BC4 3419#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD 3420#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC 3421#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF 3422#define mmDP5_DP_VID_M 0x4BCB 3423#define mmDP5_DP_VID_MSA_VBID 0x4BCD 3424#define mmDP5_DP_VID_N 0x4BCA 3425#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 3426#define mmDP5_DP_VID_TIMING 0x4BC9 3427#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 3428#define mmDP_AUX0_AUX_CONTROL 0x1880 3429#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A 3430#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B 3431#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D 3432#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 3433#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 3434#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C 3435#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E 3436#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 3437#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 3438#define mmDP_AUX0_AUX_LS_DATA 0x1887 3439#define mmDP_AUX0_AUX_LS_STATUS 0x1885 3440#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 3441#define mmDP_AUX0_AUX_SW_DATA 0x1886 3442#define mmDP_AUX0_AUX_SW_STATUS 0x1884 3443#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 3444#define mmDP_AUX1_AUX_CONTROL 0x1894 3445#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E 3446#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F 3447#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 3448#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D 3449#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C 3450#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 3451#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 3452#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 3453#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 3454#define mmDP_AUX1_AUX_LS_DATA 0x189B 3455#define mmDP_AUX1_AUX_LS_STATUS 0x1899 3456#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 3457#define mmDP_AUX1_AUX_SW_DATA 0x189A 3458#define mmDP_AUX1_AUX_SW_STATUS 0x1898 3459#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA 3460#define mmDP_AUX2_AUX_CONTROL 0x18A8 3461#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 3462#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 3463#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 3464#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 3465#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 3466#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 3467#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 3468#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 3469#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB 3470#define mmDP_AUX2_AUX_LS_DATA 0x18AF 3471#define mmDP_AUX2_AUX_LS_STATUS 0x18AD 3472#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 3473#define mmDP_AUX2_AUX_SW_DATA 0x18AE 3474#define mmDP_AUX2_AUX_SW_STATUS 0x18AC 3475#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 3476#define mmDP_AUX3_AUX_CONTROL 0x18C0 3477#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA 3478#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB 3479#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD 3480#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 3481#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 3482#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC 3483#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE 3484#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 3485#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 3486#define mmDP_AUX3_AUX_LS_DATA 0x18C7 3487#define mmDP_AUX3_AUX_LS_STATUS 0x18C5 3488#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 3489#define mmDP_AUX3_AUX_SW_DATA 0x18C6 3490#define mmDP_AUX3_AUX_SW_STATUS 0x18C4 3491#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 3492#define mmDP_AUX4_AUX_CONTROL 0x18D4 3493#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE 3494#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF 3495#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 3496#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD 3497#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC 3498#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 3499#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 3500#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 3501#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 3502#define mmDP_AUX4_AUX_LS_DATA 0x18DB 3503#define mmDP_AUX4_AUX_LS_STATUS 0x18D9 3504#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 3505#define mmDP_AUX4_AUX_SW_DATA 0x18DA 3506#define mmDP_AUX4_AUX_SW_STATUS 0x18D8 3507#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA 3508#define mmDP_AUX5_AUX_CONTROL 0x18E8 3509#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 3510#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 3511#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 3512#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 3513#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 3514#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 3515#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 3516#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 3517#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB 3518#define mmDP_AUX5_AUX_LS_DATA 0x18EF 3519#define mmDP_AUX5_AUX_LS_STATUS 0x18ED 3520#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 3521#define mmDP_AUX5_AUX_SW_DATA 0x18EE 3522#define mmDP_AUX5_AUX_SW_STATUS 0x18EC 3523#define mmDP_CONFIG 0x1CC2 3524#define mmDP_DPHY_8B10B_CNTL 0x1CD3 3525#define mmDP_DPHY_CNTL 0x1CD0 3526#define mmDP_DPHY_CRC_CNTL 0x1CD7 3527#define mmDP_DPHY_CRC_EN 0x1CD6 3528#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 3529#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 3530#define mmDP_DPHY_CRC_RESULT 0x1CD8 3531#define mmDP_DPHY_FAST_TRAINING 0x1CCE 3532#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 3533#define mmDP_DPHY_PRBS_CNTL 0x1CD4 3534#define mmDP_DPHY_SYM0 0x1CD2 3535#define mmDP_DPHY_SYM1 0x1CE0 3536#define mmDP_DPHY_SYM2 0x1CDF 3537#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 3538#define mmDP_DTO0_MODULO 0x0142 3539#define mmDP_DTO0_PHASE 0x0141 3540#define mmDP_DTO1_MODULO 0x0146 3541#define mmDP_DTO1_PHASE 0x0145 3542#define mmDP_DTO2_MODULO 0x014A 3543#define mmDP_DTO2_PHASE 0x0149 3544#define mmDP_DTO3_MODULO 0x014E 3545#define mmDP_DTO3_PHASE 0x014D 3546#define mmDP_DTO4_MODULO 0x0152 3547#define mmDP_DTO4_PHASE 0x0151 3548#define mmDP_DTO5_MODULO 0x0156 3549#define mmDP_DTO5_PHASE 0x0155 3550#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 3551#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 3552#define mmDPG_PIPE_DPM_CONTROL 0x1B34 3553#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 3554#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 3555#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 3556#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 3557#define mmDPG_TEST_DEBUG_DATA 0x1B39 3558#define mmDPG_TEST_DEBUG_INDEX 0x1B38 3559#define mmDP_HBR2_EYE_PATTERN 0x1CC8 3560#define mmDP_LINK_CNTL 0x1CC0 3561#define mmDP_LINK_FRAMING_CNTL 0x1CCC 3562#define mmDP_MSA_COLORIMETRY 0x1CDA 3563#define mmDP_MSA_MISC 0x1CC5 3564#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA 3565#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB 3566#define mmDP_MSE_LINK_TIMING 0x1CE8 3567#define mmDP_MSE_MISC_CNTL 0x1CDB 3568#define mmDP_MSE_RATE_CNTL 0x1CE1 3569#define mmDP_MSE_RATE_UPDATE 0x1CE3 3570#define mmDP_MSE_SAT0 0x1CE4 3571#define mmDP_MSE_SAT1 0x1CE5 3572#define mmDP_MSE_SAT2 0x1CE6 3573#define mmDP_MSE_SAT_UPDATE 0x1CE7 3574#define mmDP_PIXEL_FORMAT 0x1CC1 3575#define mmDP_SEC_AUD_M 0x1CA7 3576#define mmDP_SEC_AUD_M_READBACK 0x1CA8 3577#define mmDP_SEC_AUD_N 0x1CA5 3578#define mmDP_SEC_AUD_N_READBACK 0x1CA6 3579#define mmDP_SEC_CNTL 0x1CA0 3580#define mmDP_SEC_CNTL1 0x1CAB 3581#define mmDP_SEC_FRAMING1 0x1CA1 3582#define mmDP_SEC_FRAMING2 0x1CA2 3583#define mmDP_SEC_FRAMING3 0x1CA3 3584#define mmDP_SEC_FRAMING4 0x1CA4 3585#define mmDP_SEC_PACKET_CNTL 0x1CAA 3586#define mmDP_SEC_TIMESTAMP 0x1CA9 3587#define mmDP_STEER_FIFO 0x1CC4 3588#define mmDP_TEST_DEBUG_DATA 0x1CFD 3589#define mmDP_TEST_DEBUG_INDEX 0x1CFC 3590#define mmDP_VID_INTERRUPT_CNTL 0x1CCF 3591#define mmDP_VID_M 0x1CCB 3592#define mmDP_VID_MSA_VBID 0x1CCD 3593#define mmDP_VID_N 0x1CCA 3594#define mmDP_VID_STREAM_CNTL 0x1CC3 3595#define mmDP_VID_TIMING 0x1CC9 3596#define mmDVOACLKC_CNTL 0x016A 3597#define mmDVOACLKC_MVP_CNTL 0x0169 3598#define mmDVOACLKD_CNTL 0x0168 3599#define mmDVO_CLK_ENABLE 0x0129 3600#define mmDVO_CONTROL 0x185B 3601#define mmDVO_CRC2_SIG_MASK 0x185D 3602#define mmDVO_CRC2_SIG_RESULT 0x185E 3603#define mmDVO_CRC_EN 0x185C 3604#define mmDVO_ENABLE 0x1858 3605#define mmDVO_FIFO_ERROR_STATUS 0x185F 3606#define mmDVO_OUTPUT 0x185A 3607#define mmDVO_SKEW_ADJUST 0x197D 3608#define mmDVO_SOURCE_SELECT 0x1859 3609#define mmDVO_STRENGTH_CONTROL 0x197B 3610#define mmDVO_VREF_CONTROL 0x197C 3611#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E 3612#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F 3613#define mmFBC_CLIENT_REGION_MASK 0x16EB 3614#define mmFBC_CNTL 0x16D0 3615#define mmFBC_COMP_CNTL 0x16D4 3616#define mmFBC_COMP_MODE 0x16D5 3617#define mmFBC_CSM_REGION_OFFSET_01 0x16E9 3618#define mmFBC_CSM_REGION_OFFSET_23 0x16EA 3619#define mmFBC_DEBUG0 0x16D6 3620#define mmFBC_DEBUG1 0x16D7 3621#define mmFBC_DEBUG2 0x16D8 3622#define mmFBC_DEBUG_COMP 0x16EC 3623#define mmFBC_DEBUG_CSR 0x16ED 3624#define mmFBC_DEBUG_CSR_RDATA 0x16EE 3625#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 3626#define mmFBC_DEBUG_CSR_WDATA 0x16EF 3627#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 3628#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 3629#define mmFBC_IDLE_MASK 0x16D1 3630#define mmFBC_IND_LUT0 0x16D9 3631#define mmFBC_IND_LUT10 0x16E3 3632#define mmFBC_IND_LUT1 0x16DA 3633#define mmFBC_IND_LUT11 0x16E4 3634#define mmFBC_IND_LUT12 0x16E5 3635#define mmFBC_IND_LUT13 0x16E6 3636#define mmFBC_IND_LUT14 0x16E7 3637#define mmFBC_IND_LUT15 0x16E8 3638#define mmFBC_IND_LUT2 0x16DB 3639#define mmFBC_IND_LUT3 0x16DC 3640#define mmFBC_IND_LUT4 0x16DD 3641#define mmFBC_IND_LUT5 0x16DE 3642#define mmFBC_IND_LUT6 0x16DF 3643#define mmFBC_IND_LUT7 0x16E0 3644#define mmFBC_IND_LUT8 0x16E1 3645#define mmFBC_IND_LUT9 0x16E2 3646#define mmFBC_MISC 0x16F0 3647#define mmFBC_START_STOP_DELAY 0x16D3 3648#define mmFBC_STATUS 0x16F1 3649#define mmFBC_TEST_DEBUG_DATA 0x16F5 3650#define mmFBC_TEST_DEBUG_INDEX 0x16F4 3651#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 3652#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 3653#define mmFMT0_FMT_CONTROL 0x1BEE 3654#define mmFMT0_FMT_CRC_CNTL 0x1BFA 3655#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE 3656#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC 3657#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD 3658#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB 3659#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF 3660#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 3661#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 3662#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 3663#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED 3664#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 3665#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 3666#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF 3667#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 3668#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 3669#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 3670#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC 3671#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB 3672#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 3673#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 3674#define mmFMT1_FMT_CONTROL 0x1EEE 3675#define mmFMT1_FMT_CRC_CNTL 0x1EFA 3676#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE 3677#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC 3678#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD 3679#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB 3680#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF 3681#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 3682#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 3683#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 3684#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED 3685#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 3686#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 3687#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF 3688#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 3689#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 3690#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 3691#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC 3692#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB 3693#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 3694#define mmFMT2_FMT_CLAMP_CNTL 0x41F9 3695#define mmFMT2_FMT_CONTROL 0x41EE 3696#define mmFMT2_FMT_CRC_CNTL 0x41FA 3697#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE 3698#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC 3699#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD 3700#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB 3701#define mmFMT2_FMT_DEBUG_CNTL 0x41FF 3702#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 3703#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 3704#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 3705#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED 3706#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 3707#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 3708#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF 3709#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 3710#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 3711#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 3712#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC 3713#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB 3714#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 3715#define mmFMT3_FMT_CLAMP_CNTL 0x44F9 3716#define mmFMT3_FMT_CONTROL 0x44EE 3717#define mmFMT3_FMT_CRC_CNTL 0x44FA 3718#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE 3719#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC 3720#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD 3721#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB 3722#define mmFMT3_FMT_DEBUG_CNTL 0x44FF 3723#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 3724#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 3725#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 3726#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED 3727#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 3728#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 3729#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF 3730#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 3731#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 3732#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 3733#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC 3734#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB 3735#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 3736#define mmFMT4_FMT_CLAMP_CNTL 0x47F9 3737#define mmFMT4_FMT_CONTROL 0x47EE 3738#define mmFMT4_FMT_CRC_CNTL 0x47FA 3739#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE 3740#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC 3741#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD 3742#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB 3743#define mmFMT4_FMT_DEBUG_CNTL 0x47FF 3744#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 3745#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 3746#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 3747#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED 3748#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 3749#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 3750#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF 3751#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 3752#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 3753#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 3754#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC 3755#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB 3756#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 3757#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 3758#define mmFMT5_FMT_CONTROL 0x4AEE 3759#define mmFMT5_FMT_CRC_CNTL 0x4AFA 3760#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE 3761#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC 3762#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD 3763#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB 3764#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF 3765#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 3766#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 3767#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 3768#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED 3769#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 3770#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 3771#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF 3772#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 3773#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 3774#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 3775#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC 3776#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB 3777#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 3778#define mmFMT_CLAMP_CNTL 0x1BF9 3779#define mmFMT_CONTROL 0x1BEE 3780#define mmFMT_CRC_CNTL 0x1BFA 3781#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE 3782#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC 3783#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD 3784#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB 3785#define mmFMT_DEBUG_CNTL 0x1BFF 3786#define mmFMT_DITHER_RAND_B_SEED 0x1BF5 3787#define mmFMT_DITHER_RAND_G_SEED 0x1BF4 3788#define mmFMT_DITHER_RAND_R_SEED 0x1BF3 3789#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED 3790#define mmFMT_FORCE_DATA_0_1 0x1BF0 3791#define mmFMT_FORCE_DATA_2_3 0x1BF1 3792#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF 3793#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 3794#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 3795#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 3796#define mmFMT_TEST_DEBUG_DATA 0x1BEC 3797#define mmFMT_TEST_DEBUG_INDEX 0x1BEB 3798#define mmGAMUT_REMAP_C11_C12 0x1A5A 3799#define mmGAMUT_REMAP_C13_C14 0x1A5B 3800#define mmGAMUT_REMAP_C21_C22 0x1A5C 3801#define mmGAMUT_REMAP_C23_C24 0x1A5D 3802#define mmGAMUT_REMAP_C31_C32 0x1A5E 3803#define mmGAMUT_REMAP_C33_C34 0x1A5F 3804#define mmGAMUT_REMAP_CONTROL 0x1A59 3805#define mmGENENB 0x00F0 3806#define mmGENERIC_I2C_CONTROL 0x1834 3807#define mmGENERIC_I2C_DATA 0x183A 3808#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 3809#define mmGENERIC_I2C_PIN_DEBUG 0x183C 3810#define mmGENERIC_I2C_PIN_SELECTION 0x183B 3811#define mmGENERIC_I2C_SETUP 0x1838 3812#define mmGENERIC_I2C_SPEED 0x1837 3813#define mmGENERIC_I2C_STATUS 0x1836 3814#define mmGENERIC_I2C_TRANSACTION 0x1839 3815#define mmGENFC_RD 0x00F2 3816#define mmGENFC_WT 0x00EE 3817#define mmGENMO_RD 0x00F3 3818#define mmGENMO_WT 0x00F0 3819#define mmGENS0 0x00F0 3820#define mmGENS1 0x00EE 3821#define mmGRPH8_DATA 0x00F3 3822#define mmGRPH8_IDX 0x00F3 3823#define mmGRPH_COMPRESS_PITCH 0x1A1A 3824#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 3825#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B 3826#define mmGRPH_CONTROL 0x1A01 3827#define mmGRPH_DFQ_CONTROL 0x1A14 3828#define mmGRPH_DFQ_STATUS 0x1A15 3829#define mmGRPH_ENABLE 0x1A00 3830#define mmGRPH_FLIP_CONTROL 0x1A12 3831#define mmGRPH_INTERRUPT_CONTROL 0x1A17 3832#define mmGRPH_INTERRUPT_STATUS 0x1A16 3833#define mmGRPH_LUT_10BIT_BYPASS 0x1A02 3834#define mmGRPH_PITCH 0x1A06 3835#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 3836#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 3837#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 3838#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 3839#define mmGRPH_STEREOSYNC_FLIP 0x1A97 3840#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 3841#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 3842#define mmGRPH_SURFACE_OFFSET_X 0x1A09 3843#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A 3844#define mmGRPH_SWAP_CNTL 0x1A03 3845#define mmGRPH_UPDATE 0x1A11 3846#define mmGRPH_X_END 0x1A0D 3847#define mmGRPH_X_START 0x1A0B 3848#define mmGRPH_Y_END 0x1A0E 3849#define mmGRPH_Y_START 0x1A0C 3850#define mmHDMI_ACR_32_0 0x1C37 3851#define mmHDMI_ACR_32_1 0x1C38 3852#define mmHDMI_ACR_44_0 0x1C39 3853#define mmHDMI_ACR_44_1 0x1C3A 3854#define mmHDMI_ACR_48_0 0x1C3B 3855#define mmHDMI_ACR_48_1 0x1C3C 3856#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F 3857#define mmHDMI_ACR_STATUS_0 0x1C3D 3858#define mmHDMI_ACR_STATUS_1 0x1C3E 3859#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E 3860#define mmHDMI_CONTROL 0x1C0C 3861#define mmHDMI_GC 0x1C16 3862#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 3863#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 3864#define mmHDMI_INFOFRAME_CONTROL0 0x1C11 3865#define mmHDMI_INFOFRAME_CONTROL1 0x1C12 3866#define mmHDMI_STATUS 0x1C0D 3867#define mmHDMI_VBI_PACKET_CONTROL 0x1C10 3868#define mmINPUT_CSC_C11_C12 0x1A36 3869#define mmINPUT_CSC_C13_C14 0x1A37 3870#define mmINPUT_CSC_C21_C22 0x1A38 3871#define mmINPUT_CSC_C23_C24 0x1A39 3872#define mmINPUT_CSC_C31_C32 0x1A3A 3873#define mmINPUT_CSC_C33_C34 0x1A3B 3874#define mmINPUT_CSC_CONTROL 0x1A35 3875#define mmINPUT_GAMMA_CONTROL 0x1A10 3876#define mmKEY_CONTROL 0x1A53 3877#define mmKEY_RANGE_ALPHA 0x1A54 3878#define mmKEY_RANGE_BLUE 0x1A57 3879#define mmKEY_RANGE_GREEN 0x1A56 3880#define mmKEY_RANGE_RED 0x1A55 3881#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB 3882#define mmLB0_LB_DEBUG 0x1AFC 3883#define mmLB0_LB_DEBUG2 0x1AC9 3884#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 3885#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA 3886#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF 3887#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE 3888#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 3889#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 3890#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA 3891#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB 3892#define mmLB1_LB_DEBUG 0x1DFC 3893#define mmLB1_LB_DEBUG2 0x1DC9 3894#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 3895#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA 3896#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF 3897#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE 3898#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 3899#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 3900#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA 3901#define mmLB2_DC_MVP_LB_CONTROL 0x40DB 3902#define mmLB2_LB_DEBUG 0x40FC 3903#define mmLB2_LB_DEBUG2 0x40C9 3904#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 3905#define mmLB2_LB_SYNC_RESET_SEL 0x40CA 3906#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF 3907#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE 3908#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 3909#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 3910#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA 3911#define mmLB3_DC_MVP_LB_CONTROL 0x43DB 3912#define mmLB3_LB_DEBUG 0x43FC 3913#define mmLB3_LB_DEBUG2 0x43C9 3914#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 3915#define mmLB3_LB_SYNC_RESET_SEL 0x43CA 3916#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF 3917#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE 3918#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 3919#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 3920#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA 3921#define mmLB4_DC_MVP_LB_CONTROL 0x46DB 3922#define mmLB4_LB_DEBUG 0x46FC 3923#define mmLB4_LB_DEBUG2 0x46C9 3924#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 3925#define mmLB4_LB_SYNC_RESET_SEL 0x46CA 3926#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF 3927#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE 3928#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 3929#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 3930#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA 3931#define mmLB5_DC_MVP_LB_CONTROL 0x49DB 3932#define mmLB5_LB_DEBUG 0x49FC 3933#define mmLB5_LB_DEBUG2 0x49C9 3934#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 3935#define mmLB5_LB_SYNC_RESET_SEL 0x49CA 3936#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF 3937#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE 3938#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 3939#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 3940#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA 3941#define mmLB_DEBUG 0x1AFC 3942#define mmLB_DEBUG2 0x1AC9 3943#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 3944#define mmLB_SYNC_RESET_SEL 0x1ACA 3945#define mmLB_TEST_DEBUG_DATA 0x1AFF 3946#define mmLB_TEST_DEBUG_INDEX 0x1AFE 3947#define mmLIGHT_SLEEP_CNTL 0x0132 3948#define mmLOW_POWER_TILING_CONTROL 0x0325 3949#define mmLVDS_DATA_CNTL 0x1C8C 3950#define mmLVTMA_PWRSEQ_CNTL 0x1919 3951#define mmLVTMA_PWRSEQ_DELAY1 0x191C 3952#define mmLVTMA_PWRSEQ_DELAY2 0x191D 3953#define mmLVTMA_PWRSEQ_REF_DIV 0x191B 3954#define mmLVTMA_PWRSEQ_STATE 0x191A 3955#define mmMASTER_COMM_CMD_REG 0x161F 3956#define mmMASTER_COMM_CNTL_REG 0x1620 3957#define mmMASTER_COMM_DATA_REG1 0x161C 3958#define mmMASTER_COMM_DATA_REG2 0x161D 3959#define mmMASTER_COMM_DATA_REG3 0x161E 3960#define mmMASTER_UPDATE_LOCK 0x1BBD 3961#define mmMASTER_UPDATE_MODE 0x1BBE 3962#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C 3963#define mmMCIF_CONTROL 0x0314 3964#define mmMCIF_MEM_CONTROL 0x0319 3965#define mmMCIF_TEST_DEBUG_DATA 0x0317 3966#define mmMCIF_TEST_DEBUG_INDEX 0x0316 3967#define mmMCIF_VMID 0x0318 3968#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 3969#define mmMICROSECOND_TIME_BASE_DIV 0x013B 3970#define mmMILLISECOND_TIME_BASE_DIV 0x0130 3971#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 3972#define mmMVP_AFR_FLIP_MODE 0x1AD8 3973#define mmMVP_BLACK_KEYER 0x1686 3974#define mmMVP_CONTROL1 0x1680 3975#define mmMVP_CONTROL2 0x1681 3976#define mmMVP_CONTROL3 0x168A 3977#define mmMVP_CRC_CNTL 0x1687 3978#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 3979#define mmMVP_CRC_RESULT_RED 0x1689 3980#define mmMVP_DEBUG 0x168F 3981#define mmMVP_FIFO_CONTROL 0x1682 3982#define mmMVP_FIFO_STATUS 0x1683 3983#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA 3984#define mmMVP_INBAND_CNTL_CAP 0x1685 3985#define mmMVP_RECEIVE_CNT_CNTL1 0x168B 3986#define mmMVP_RECEIVE_CNT_CNTL2 0x168C 3987#define mmMVP_SLAVE_STATUS 0x1684 3988#define mmMVP_TEST_DEBUG_DATA 0x168E 3989#define mmMVP_TEST_DEBUG_INDEX 0x168D 3990#define mmOUTPUT_CSC_C11_C12 0x1A3D 3991#define mmOUTPUT_CSC_C13_C14 0x1A3E 3992#define mmOUTPUT_CSC_C21_C22 0x1A3F 3993#define mmOUTPUT_CSC_C23_C24 0x1A40 3994#define mmOUTPUT_CSC_C31_C32 0x1A41 3995#define mmOUTPUT_CSC_C33_C34 0x1A42 3996#define mmOUTPUT_CSC_CONTROL 0x1A3C 3997#define mmOUT_ROUND_CONTROL 0x1A51 3998#define mmOVL_CONTROL1 0x1A1D 3999#define mmOVL_CONTROL2 0x1A1E 4000#define mmOVL_DFQ_CONTROL 0x1A29
4001#define mmOVL_DFQ_STATUS 0x1A2A 4002#define mmOVL_ENABLE 0x1A1C 4003#define mmOVL_END 0x1A26 4004#define mmOVL_PITCH 0x1A21 4005#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C 4006#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 4007#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 4008#define mmOVL_START 0x1A25 4009#define mmOVL_STEREOSYNC_FLIP 0x1A93 4010#define mmOVL_SURFACE_ADDRESS 0x1A20 4011#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 4012#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B 4013#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 4014#define mmOVL_SURFACE_OFFSET_X 0x1A23 4015#define mmOVL_SURFACE_OFFSET_Y 0x1A24 4016#define mmOVL_SWAP_CNTL 0x1A1F 4017#define mmOVL_UPDATE 0x1A27 4018#define mmPHY_AUX_CNTL 0x197F 4019#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA 4020#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 4021#define mmPIPE0_MAX_REQUESTS 0x0302 4022#define mmPIPE0_PG_CONFIG 0x1760 4023#define mmPIPE0_PG_ENABLE 0x1761 4024#define mmPIPE0_PG_STATUS 0x1762 4025#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB 4026#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 4027#define mmPIPE1_MAX_REQUESTS 0x0303 4028#define mmPIPE1_PG_CONFIG 0x1764 4029#define mmPIPE1_PG_ENABLE 0x1765 4030#define mmPIPE1_PG_STATUS 0x1766 4031#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC 4032#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 4033#define mmPIPE2_MAX_REQUESTS 0x0304 4034#define mmPIPE2_PG_CONFIG 0x1768 4035#define mmPIPE2_PG_ENABLE 0x1769 4036#define mmPIPE2_PG_STATUS 0x176A 4037#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD 4038#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 4039#define mmPIPE3_MAX_REQUESTS 0x0305 4040#define mmPIPE3_PG_CONFIG 0x176C 4041#define mmPIPE3_PG_ENABLE 0x176D 4042#define mmPIPE3_PG_STATUS 0x176E 4043#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE 4044#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 4045#define mmPIPE4_MAX_REQUESTS 0x0306 4046#define mmPIPE4_PG_CONFIG 0x1770 4047#define mmPIPE4_PG_ENABLE 0x1771 4048#define mmPIPE4_PG_STATUS 0x1772 4049#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF 4050#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 4051#define mmPIPE5_MAX_REQUESTS 0x0307 4052#define mmPIPE5_PG_CONFIG 0x1774 4053#define mmPIPE5_PG_ENABLE 0x1775 4054#define mmPIPE5_PG_STATUS 0x1776 4055#define mmPIXCLK0_RESYNC_CNTL 0x013A 4056#define mmPIXCLK1_RESYNC_CNTL 0x0138 4057#define mmPIXCLK2_RESYNC_CNTL 0x0139 4058#define mmPLL_ANALOG 0x1708 4059#define mmPLL_CNTL 0x1707 4060#define mmPLL_DEBUG_CNTL 0x170B 4061#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F 4062#define mmPLL_DISPCLK_DTO_CNTL 0x170E 4063#define mmPLL_DS_CNTL 0x1705 4064#define mmPLL_FB_DIV 0x1701 4065#define mmPLL_IDCLK_CNTL 0x1706 4066#define mmPLL_POST_DIV 0x1702 4067#define mmPLL_REF_DIV 0x1700 4068#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 4069#define mmPLL_SS_CNTL 0x1704 4070#define mmPLL_UNLOCK_DETECT_CNTL 0x170A 4071#define mmPLL_UPDATE_CNTL 0x170D 4072#define mmPLL_UPDATE_LOCK 0x170C 4073#define mmPLL_VREG_CNTL 0x1709 4074#define mmPRESCALE_GRPH_CONTROL 0x1A2D 4075#define mmPRESCALE_OVL_CONTROL 0x1A31 4076#define mmPRESCALE_VALUES_GRPH_B 0x1A30 4077#define mmPRESCALE_VALUES_GRPH_G 0x1A2F 4078#define mmPRESCALE_VALUES_GRPH_R 0x1A2E 4079#define mmPRESCALE_VALUES_OVL_CB 0x1A32 4080#define mmPRESCALE_VALUES_OVL_CR 0x1A34 4081#define mmPRESCALE_VALUES_OVL_Y 0x1A33 4082#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 4083#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 4084#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 4085#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD 4086#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE 4087#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF 4088#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 4089#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA 4090#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB 4091#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC 4092#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 4093#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 4094#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 4095#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 4096#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 4097#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 4098#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA 4099#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB 4100#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 4101#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 4102#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 4103#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 4104#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 4105#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 4106#define mmREGAMMA_CONTROL 0x1AA0 4107#define mmREGAMMA_LUT_DATA 0x1AA2 4108#define mmREGAMMA_LUT_INDEX 0x1AA1 4109#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 4110#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E 4111#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F 4112#define mmSCL0_SCL_ALU_CONTROL 0x1B54 4113#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 4114#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 4115#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4116#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 4117#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 4118#define mmSCL0_SCL_CONTROL 0x1B44 4119#define mmSCL0_SCL_DEBUG 0x1B6A 4120#define mmSCL0_SCL_DEBUG2 0x1B69 4121#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 4122#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A 4123#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B 4124#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 4125#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 4126#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 4127#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 4128#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 4129#define mmSCL0_SCL_TAP_CONTROL 0x1B43 4130#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C 4131#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B 4132#define mmSCL0_SCL_UPDATE 0x1B51 4133#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E 4134#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 4135#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 4136#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F 4137#define mmSCL0_VIEWPORT_SIZE 0x1B5D 4138#define mmSCL0_VIEWPORT_START 0x1B5C 4139#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E 4140#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F 4141#define mmSCL1_SCL_ALU_CONTROL 0x1E54 4142#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 4143#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 4144#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 4145#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 4146#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 4147#define mmSCL1_SCL_CONTROL 0x1E44 4148#define mmSCL1_SCL_DEBUG 0x1E6A 4149#define mmSCL1_SCL_DEBUG2 0x1E69 4150#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 4151#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A 4152#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B 4153#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 4154#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 4155#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 4156#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 4157#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 4158#define mmSCL1_SCL_TAP_CONTROL 0x1E43 4159#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C 4160#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B 4161#define mmSCL1_SCL_UPDATE 0x1E51 4162#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E 4163#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 4164#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 4165#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F 4166#define mmSCL1_VIEWPORT_SIZE 0x1E5D 4167#define mmSCL1_VIEWPORT_START 0x1E5C 4168#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E 4169#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F 4170#define mmSCL2_SCL_ALU_CONTROL 0x4154 4171#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 4172#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 4173#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 4174#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 4175#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 4176#define mmSCL2_SCL_CONTROL 0x4144 4177#define mmSCL2_SCL_DEBUG 0x416A 4178#define mmSCL2_SCL_DEBUG2 0x4169 4179#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 4180#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A 4181#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B 4182#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 4183#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 4184#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 4185#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 4186#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 4187#define mmSCL2_SCL_TAP_CONTROL 0x4143 4188#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C 4189#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B 4190#define mmSCL2_SCL_UPDATE 0x4151 4191#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E 4192#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 4193#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 4194#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F 4195#define mmSCL2_VIEWPORT_SIZE 0x415D 4196#define mmSCL2_VIEWPORT_START 0x415C 4197#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E 4198#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F 4199#define mmSCL3_SCL_ALU_CONTROL 0x4454 4200#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 4201#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 4202#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 4203#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 4204#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 4205#define mmSCL3_SCL_CONTROL 0x4444 4206#define mmSCL3_SCL_DEBUG 0x446A 4207#define mmSCL3_SCL_DEBUG2 0x4469 4208#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 4209#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A 4210#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B 4211#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 4212#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 4213#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 4214#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 4215#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 4216#define mmSCL3_SCL_TAP_CONTROL 0x4443 4217#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C 4218#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B 4219#define mmSCL3_SCL_UPDATE 0x4451 4220#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E 4221#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 4222#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 4223#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F 4224#define mmSCL3_VIEWPORT_SIZE 0x445D 4225#define mmSCL3_VIEWPORT_START 0x445C 4226#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E 4227#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F 4228#define mmSCL4_SCL_ALU_CONTROL 0x4754 4229#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 4230#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 4231#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 4232#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 4233#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 4234#define mmSCL4_SCL_CONTROL 0x4744 4235#define mmSCL4_SCL_DEBUG 0x476A 4236#define mmSCL4_SCL_DEBUG2 0x4769 4237#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 4238#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A 4239#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B 4240#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 4241#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 4242#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 4243#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 4244#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 4245#define mmSCL4_SCL_TAP_CONTROL 0x4743 4246#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C 4247#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B 4248#define mmSCL4_SCL_UPDATE 0x4751 4249#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E 4250#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 4251#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 4252#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F 4253#define mmSCL4_VIEWPORT_SIZE 0x475D 4254#define mmSCL4_VIEWPORT_START 0x475C 4255#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E 4256#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F 4257#define mmSCL5_SCL_ALU_CONTROL 0x4A54 4258#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 4259#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 4260#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 4261#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 4262#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 4263#define mmSCL5_SCL_CONTROL 0x4A44 4264#define mmSCL5_SCL_DEBUG 0x4A6A 4265#define mmSCL5_SCL_DEBUG2 0x4A69 4266#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 4267#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A 4268#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B 4269#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 4270#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 4271#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 4272#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 4273#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 4274#define mmSCL5_SCL_TAP_CONTROL 0x4A43 4275#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C 4276#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B 4277#define mmSCL5_SCL_UPDATE 0x4A51 4278#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E 4279#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 4280#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 4281#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F 4282#define mmSCL5_VIEWPORT_SIZE 0x4A5D 4283#define mmSCL5_VIEWPORT_START 0x4A5C 4284#define mmSCL_ALU_CONTROL 0x1B54 4285#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 4286#define mmSCL_BYPASS_CONTROL 0x1B45 4287#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4288#define mmSCL_COEF_RAM_SELECT 0x1B40 4289#define mmSCL_COEF_RAM_TAP_DATA 0x1B41 4290#define mmSCL_CONTROL 0x1B44 4291#define mmSCL_DEBUG 0x1B6A 4292#define mmSCL_DEBUG2 0x1B69 4293#define mmSCL_F_SHARP_CONTROL 0x1B53 4294#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A 4295#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B 4296#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 4297#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 4298#define mmSCL_MODE_CHANGE_DET1 0x1B60 4299#define mmSCL_MODE_CHANGE_DET2 0x1B61 4300#define mmSCL_MODE_CHANGE_DET3 0x1B62 4301#define mmSCL_MODE_CHANGE_MASK 0x1B63 4302#define mmSCL_TAP_CONTROL 0x1B43 4303#define mmSCL_TEST_DEBUG_DATA 0x1B6C 4304#define mmSCL_TEST_DEBUG_INDEX 0x1B6B 4305#define mmSCL_UPDATE 0x1B51 4306#define mmSCL_VERT_FILTER_CONTROL 0x1B4E 4307#define mmSCL_VERT_FILTER_INIT 0x1B50 4308#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 4309#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F 4310#define mmSEQ8_DATA 0x00F1 4311#define mmSEQ8_IDX 0x00F1 4312#define mmSLAVE_COMM_CMD_REG 0x1624 4313#define mmSLAVE_COMM_CNTL_REG 0x1625 4314#define mmSLAVE_COMM_DATA_REG1 0x1621 4315#define mmSLAVE_COMM_DATA_REG2 0x1622 4316#define mmSLAVE_COMM_DATA_REG3 0x1623 4317#define mmSYMCLKA_CLOCK_ENABLE 0x0160 4318#define mmSYMCLKB_CLOCK_ENABLE 0x0161 4319#define mmSYMCLKC_CLOCK_ENABLE 0x0162 4320#define mmSYMCLKD_CLOCK_ENABLE 0x0163 4321#define mmSYMCLKE_CLOCK_ENABLE 0x0164 4322#define mmSYMCLKF_CLOCK_ENABLE 0x0165 4323#define mmTMDS_CNTL 0x1C7C 4324#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E 4325#define mmTMDS_CONTROL_CHAR 0x1C7D 4326#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 4327#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 4328#define mmTMDS_CTL_BITS 0x1C83 4329#define mmTMDS_DCBALANCER_CONTROL 0x1C84 4330#define mmTMDS_DEBUG 0x1C82 4331#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F 4332#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 4333#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 4334#define mmUNIPHYAB_TPG_CONTROL 0x1931 4335#define mmUNIPHYAB_TPG_SEED 0x1932 4336#define mmUNIPHY_ANG_BIST_CNTL 0x198C 4337#define mmUNIPHYCD_TPG_CONTROL 0x1933 4338#define mmUNIPHYCD_TPG_SEED 0x1934 4339#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E 4340#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A 4341#define mmUNIPHYEF_TPG_CONTROL 0x1935 4342#define mmUNIPHYEF_TPG_SEED 0x1936 4343#define mmUNIPHY_IMPCAL_LINKA 0x1908 4344#define mmUNIPHY_IMPCAL_LINKB 0x1909 4345#define mmUNIPHY_IMPCAL_LINKC 0x190F 4346#define mmUNIPHY_IMPCAL_LINKD 0x1910 4347#define mmUNIPHY_IMPCAL_LINKE 0x1913 4348#define mmUNIPHY_IMPCAL_LINKF 0x1914 4349#define mmUNIPHY_IMPCAL_PERIOD 0x190A 4350#define mmUNIPHY_IMPCAL_PSW_AB 0x190E 4351#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 4352#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 4353#define mmUNIPHY_LINK_CNTL 0x198D 4354#define mmUNIPHY_PLL_CONTROL1 0x1986 4355#define mmUNIPHY_PLL_CONTROL2 0x1987 4356#define mmUNIPHY_PLL_FBDIV 0x1985 4357#define mmUNIPHY_PLL_SS_CNTL 0x1989 4358#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 4359#define mmUNIPHY_POWER_CONTROL 0x1984 4360#define mmUNIPHY_REG_TEST_OUTPUT 0x198B 4361#define mmUNIPHY_SOFT_RESET 0x0166 4362#define mmUNIPHY_TX_CONTROL1 0x1980 4363#define mmUNIPHY_TX_CONTROL2 0x1981 4364#define mmUNIPHY_TX_CONTROL3 0x1982 4365#define mmUNIPHY_TX_CONTROL4 0x1983 4366#define mmVGA25_PPLL_ANALOG 0x00E4 4367#define mmVGA25_PPLL_FB_DIV 0x00DC 4368#define mmVGA25_PPLL_POST_DIV 0x00E0 4369#define mmVGA25_PPLL_REF_DIV 0x00D8 4370#define mmVGA28_PPLL_ANALOG 0x00E5 4371#define mmVGA28_PPLL_FB_DIV 0x00DD 4372#define mmVGA28_PPLL_POST_DIV 0x00E1 4373#define mmVGA28_PPLL_REF_DIV 0x00D9 4374#define mmVGA41_PPLL_ANALOG 0x00E6 4375#define mmVGA41_PPLL_FB_DIV 0x00DE 4376#define mmVGA41_PPLL_POST_DIV 0x00E2 4377#define mmVGA41_PPLL_REF_DIV 0x00DA 4378#define mmVGA_CACHE_CONTROL 0x00CB 4379#define mmVGA_DEBUG_READBACK_DATA 0x00D7 4380#define mmVGA_DEBUG_READBACK_INDEX 0x00D6 4381#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 4382#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 4383#define mmVGA_HDP_CONTROL 0x00CA 4384#define mmVGA_HW_DEBUG 0x00CF 4385#define mmVGA_INTERRUPT_CONTROL 0x00D1 4386#define mmVGA_INTERRUPT_STATUS 0x00D3 4387#define mmVGA_MAIN_CONTROL 0x00D4 4388#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 4389#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 4390#define mmVGA_MEM_READ_PAGE_ADDR 0x0013 4391#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 4392#define mmVGA_MODE_CONTROL 0x00C2 4393#define mmVGA_RENDER_CONTROL 0x00C0 4394#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 4395#define mmVGA_SOURCE_SELECT 0x00FC 4396#define mmVGA_STATUS 0x00D0 4397#define mmVGA_STATUS_CLEAR 0x00D2 4398#define mmVGA_SURFACE_PITCH_SELECT 0x00C3 4399#define mmVGA_TEST_CONTROL 0x00D5 4400#define mmVGA_TEST_DEBUG_DATA 0x00C7 4401#define mmVGA_TEST_DEBUG_INDEX 0x00C5 4402#define mmVIEWPORT_SIZE 0x1B5D 4403#define mmVIEWPORT_START 0x1B5C 4404#define mmXDMA_CLOCK_GATING_CNTL 0x0409 4405#define mmXDMA_IF_BIF_STATUS 0x0418 4406#define mmXDMA_INTERRUPT 0x0406 4407#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 4408#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 4409#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 4410#define mmXDMA_MEM_POWER_CNTL 0x040B 4411#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 4412#define mmXDMA_MSTR_CNTL 0x03E0 4413#define mmXDMA_MSTR_HEIGHT 0x03E3 4414#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 4415#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 4416#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 4417#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA 4418#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D 4419#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 4420#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C 4421#define mmXDMA_MSTR_READ_COMMAND 0x03E1 4422#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 4423#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 4424#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 4425#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 4426#define mmXDMA_MSTR_STATUS 0x03E8 4427#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A 4428#define mmXDMA_SLV_CNTL 0x03FB 4429#define mmXDMA_SLV_FLIP_PENDING 0x0407 4430#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD 4431#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F 4432#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E 4433#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 4434#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 4435#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 4436#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF 4437#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 4438#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 4439#define mmXDMA_SLV_SLS_PITCH 0x03FE 4440#define mmXDMA_SLV_WB_RATE_CNTL 0x0401 4441#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 4442#define mmXDMA_TEST_DEBUG_DATA 0x041D 4443#define mmXDMA_TEST_DEBUG_INDEX 0x041C 4444 4445/* Registers that spilled out of sid.h */ 4446#define mmDATA_FORMAT 0x1AC0 4447#define mmDESKTOP_HEIGHT 0x1AC1 4448#define mmDC_LB_MEMORY_SPLIT 0x1AC3 4449#define mmPRIORITY_A_CNT 0x1AC6 4450#define mmPRIORITY_B_CNT 0x1AC7 4451#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 4452#define mmINT_MASK 0x1AD0 4453#define mmVLINE_STATUS 0x1AEE 4454#define mmVBLANK_STATUS 0x1AEF 4455 4456 4457#endif 4458