1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _gc_9_0_OFFSET_HEADER 22#define _gc_9_0_OFFSET_HEADER 23 24 25 26// addressBlock: gc_grbmdec 27// base address: 0x8000 28#define mmGRBM_CNTL 0x0000 29#define mmGRBM_CNTL_BASE_IDX 0 30#define mmGRBM_SKEW_CNTL 0x0001 31#define mmGRBM_SKEW_CNTL_BASE_IDX 0 32#define mmGRBM_STATUS2 0x0002 33#define mmGRBM_STATUS2_BASE_IDX 0 34#define mmGRBM_PWR_CNTL 0x0003 35#define mmGRBM_PWR_CNTL_BASE_IDX 0 36#define mmGRBM_STATUS 0x0004 37#define mmGRBM_STATUS_BASE_IDX 0 38#define mmGRBM_STATUS_SE0 0x0005 39#define mmGRBM_STATUS_SE0_BASE_IDX 0 40#define mmGRBM_STATUS_SE1 0x0006 41#define mmGRBM_STATUS_SE1_BASE_IDX 0 42#define mmGRBM_SOFT_RESET 0x0008 43#define mmGRBM_SOFT_RESET_BASE_IDX 0 44#define mmGRBM_CGTT_CLK_CNTL 0x000b 45#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0 46#define mmGRBM_GFX_CLKEN_CNTL 0x000c 47#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 48#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d 49#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 50#define mmGRBM_STATUS_SE2 0x000e 51#define mmGRBM_STATUS_SE2_BASE_IDX 0 52#define mmGRBM_STATUS_SE3 0x000f 53#define mmGRBM_STATUS_SE3_BASE_IDX 0 54#define mmGRBM_READ_ERROR 0x0016 55#define mmGRBM_READ_ERROR_BASE_IDX 0 56#define mmGRBM_READ_ERROR2 0x0017 57#define mmGRBM_READ_ERROR2_BASE_IDX 0 58#define mmGRBM_INT_CNTL 0x0018 59#define mmGRBM_INT_CNTL_BASE_IDX 0 60#define mmGRBM_TRAP_OP 0x0019 61#define mmGRBM_TRAP_OP_BASE_IDX 0 62#define mmGRBM_TRAP_ADDR 0x001a 63#define mmGRBM_TRAP_ADDR_BASE_IDX 0 64#define mmGRBM_TRAP_ADDR_MSK 0x001b 65#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 66#define mmGRBM_TRAP_WD 0x001c 67#define mmGRBM_TRAP_WD_BASE_IDX 0 68#define mmGRBM_TRAP_WD_MSK 0x001d 69#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 70#define mmGRBM_DSM_BYPASS 0x001e 71#define mmGRBM_DSM_BYPASS_BASE_IDX 0 72#define mmGRBM_WRITE_ERROR 0x001f 73#define mmGRBM_WRITE_ERROR_BASE_IDX 0 74#define mmGRBM_IOV_ERROR 0x0020 75#define mmGRBM_IOV_ERROR_BASE_IDX 0 76#define mmGRBM_CHIP_REVISION 0x0021 77#define mmGRBM_CHIP_REVISION_BASE_IDX 0 78#define mmGRBM_GFX_CNTL 0x0022 79#define mmGRBM_GFX_CNTL_BASE_IDX 0 80#define mmGRBM_RSMU_CFG 0x0023 81#define mmGRBM_RSMU_CFG_BASE_IDX 0 82#define mmGRBM_IH_CREDIT 0x0024 83#define mmGRBM_IH_CREDIT_BASE_IDX 0 84#define mmGRBM_PWR_CNTL2 0x0025 85#define mmGRBM_PWR_CNTL2_BASE_IDX 0 86#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 87#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 88#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 89#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 90#define mmGRBM_RSMU_READ_ERROR 0x0028 91#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 92#define mmGRBM_CHICKEN_BITS 0x0029 93#define mmGRBM_CHICKEN_BITS_BASE_IDX 0 94#define mmGRBM_NOWHERE 0x003f 95#define mmGRBM_NOWHERE_BASE_IDX 0 96#define mmGRBM_SCRATCH_REG0 0x0040 97#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 98#define mmGRBM_SCRATCH_REG1 0x0041 99#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 100#define mmGRBM_SCRATCH_REG2 0x0042 101#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 102#define mmGRBM_SCRATCH_REG3 0x0043 103#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 104#define mmGRBM_SCRATCH_REG4 0x0044 105#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 106#define mmGRBM_SCRATCH_REG5 0x0045 107#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 108#define mmGRBM_SCRATCH_REG6 0x0046 109#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 110#define mmGRBM_SCRATCH_REG7 0x0047 111#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 112 113 114// addressBlock: gc_cpdec 115// base address: 0x8200 116#define mmCP_CPC_STATUS 0x0084 117#define mmCP_CPC_STATUS_BASE_IDX 0 118#define mmCP_CPC_BUSY_STAT 0x0085 119#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 120#define mmCP_CPC_STALLED_STAT1 0x0086 121#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 122#define mmCP_CPF_STATUS 0x0087 123#define mmCP_CPF_STATUS_BASE_IDX 0 124#define mmCP_CPF_BUSY_STAT 0x0088 125#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 126#define mmCP_CPF_STALLED_STAT1 0x0089 127#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 128#define mmCP_CPC_GRBM_FREE_COUNT 0x008b 129#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 130#define mmCP_MEC_CNTL 0x008d 131#define mmCP_MEC_CNTL_BASE_IDX 0 132#define mmCP_MEC_ME1_HEADER_DUMP 0x008e 133#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 134#define mmCP_MEC_ME2_HEADER_DUMP 0x008f 135#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 136#define mmCP_CPC_SCRATCH_INDEX 0x0090 137#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 138#define mmCP_CPC_SCRATCH_DATA 0x0091 139#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 140#define mmCP_CPF_GRBM_FREE_COUNT 0x0092 141#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 142#define mmCP_CPC_HALT_HYST_COUNT 0x00a7 143#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 144#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad 145#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0 146#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae 147#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0 148#define mmCP_PRT_LOD_STATS_CNTL2 0x00af 149#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0 150#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0 151#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0 152#define mmCP_CE_COMPARE_COUNT 0x00c0 153#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 154#define mmCP_CE_DE_COUNT 0x00c1 155#define mmCP_CE_DE_COUNT_BASE_IDX 0 156#define mmCP_DE_CE_COUNT 0x00c2 157#define mmCP_DE_CE_COUNT_BASE_IDX 0 158#define mmCP_DE_LAST_INVAL_COUNT 0x00c3 159#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 160#define mmCP_DE_DE_COUNT 0x00c4 161#define mmCP_DE_DE_COUNT_BASE_IDX 0 162#define mmCP_STALLED_STAT3 0x019c 163#define mmCP_STALLED_STAT3_BASE_IDX 0 164#define mmCP_STALLED_STAT1 0x019d 165#define mmCP_STALLED_STAT1_BASE_IDX 0 166#define mmCP_STALLED_STAT2 0x019e 167#define mmCP_STALLED_STAT2_BASE_IDX 0 168#define mmCP_BUSY_STAT 0x019f 169#define mmCP_BUSY_STAT_BASE_IDX 0 170#define mmCP_STAT 0x01a0 171#define mmCP_STAT_BASE_IDX 0 172#define mmCP_ME_HEADER_DUMP 0x01a1 173#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 174#define mmCP_PFP_HEADER_DUMP 0x01a2 175#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 176#define mmCP_GRBM_FREE_COUNT 0x01a3 177#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 178#define mmCP_CE_HEADER_DUMP 0x01a4 179#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 180#define mmCP_PFP_INSTR_PNTR 0x01a5 181#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 182#define mmCP_ME_INSTR_PNTR 0x01a6 183#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 184#define mmCP_CE_INSTR_PNTR 0x01a7 185#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 186#define mmCP_MEC1_INSTR_PNTR 0x01a8 187#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 188#define mmCP_MEC2_INSTR_PNTR 0x01a9 189#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 190#define mmCP_CSF_STAT 0x01b4 191#define mmCP_CSF_STAT_BASE_IDX 0 192#define mmCP_ME_CNTL 0x01b6 193#define mmCP_ME_CNTL_BASE_IDX 0 194#define mmCP_CNTX_STAT 0x01b8 195#define mmCP_CNTX_STAT_BASE_IDX 0 196#define mmCP_ME_PREEMPTION 0x01b9 197#define mmCP_ME_PREEMPTION_BASE_IDX 0 198#define mmCP_ROQ_THRESHOLDS 0x01bc 199#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 200#define mmCP_MEQ_STQ_THRESHOLD 0x01bd 201#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 202#define mmCP_RB2_RPTR 0x01be 203#define mmCP_RB2_RPTR_BASE_IDX 0 204#define mmCP_RB1_RPTR 0x01bf 205#define mmCP_RB1_RPTR_BASE_IDX 0 206#define mmCP_RB0_RPTR 0x01c0 207#define mmCP_RB0_RPTR_BASE_IDX 0 208#define mmCP_RB_RPTR 0x01c0 209#define mmCP_RB_RPTR_BASE_IDX 0 210#define mmCP_RB_WPTR_DELAY 0x01c1 211#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 212#define mmCP_RB_WPTR_POLL_CNTL 0x01c2 213#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 214#define mmCP_ROQ1_THRESHOLDS 0x01d5 215#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 216#define mmCP_ROQ2_THRESHOLDS 0x01d6 217#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 218#define mmCP_STQ_THRESHOLDS 0x01d7 219#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 220#define mmCP_QUEUE_THRESHOLDS 0x01d8 221#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 222#define mmCP_MEQ_THRESHOLDS 0x01d9 223#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 224#define mmCP_ROQ_AVAIL 0x01da 225#define mmCP_ROQ_AVAIL_BASE_IDX 0 226#define mmCP_STQ_AVAIL 0x01db 227#define mmCP_STQ_AVAIL_BASE_IDX 0 228#define mmCP_ROQ2_AVAIL 0x01dc 229#define mmCP_ROQ2_AVAIL_BASE_IDX 0 230#define mmCP_MEQ_AVAIL 0x01dd 231#define mmCP_MEQ_AVAIL_BASE_IDX 0 232#define mmCP_CMD_INDEX 0x01de 233#define mmCP_CMD_INDEX_BASE_IDX 0 234#define mmCP_CMD_DATA 0x01df 235#define mmCP_CMD_DATA_BASE_IDX 0 236#define mmCP_ROQ_RB_STAT 0x01e0 237#define mmCP_ROQ_RB_STAT_BASE_IDX 0 238#define mmCP_ROQ_IB1_STAT 0x01e1 239#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 240#define mmCP_ROQ_IB2_STAT 0x01e2 241#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 242#define mmCP_STQ_STAT 0x01e3 243#define mmCP_STQ_STAT_BASE_IDX 0 244#define mmCP_STQ_WR_STAT 0x01e4 245#define mmCP_STQ_WR_STAT_BASE_IDX 0 246#define mmCP_MEQ_STAT 0x01e5 247#define mmCP_MEQ_STAT_BASE_IDX 0 248#define mmCP_CEQ1_AVAIL 0x01e6 249#define mmCP_CEQ1_AVAIL_BASE_IDX 0 250#define mmCP_CEQ2_AVAIL 0x01e7 251#define mmCP_CEQ2_AVAIL_BASE_IDX 0 252#define mmCP_CE_ROQ_RB_STAT 0x01e8 253#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 254#define mmCP_CE_ROQ_IB1_STAT 0x01e9 255#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 256#define mmCP_CE_ROQ_IB2_STAT 0x01ea 257#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 258#define mmCP_INT_STAT_DEBUG 0x01f7 259#define mmCP_INT_STAT_DEBUG_BASE_IDX 0 260 261 262// addressBlock: gc_padec 263// base address: 0x8800 264#define mmVGT_VTX_VECT_EJECT_REG 0x022c 265#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 266#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d 267#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 268#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e 269#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 270#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f 271#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 272#define mmVGT_LAST_COPY_STATE 0x0230 273#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 274#define mmVGT_CACHE_INVALIDATION 0x0231 275#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 276#define mmVGT_RESET_DEBUG 0x0232 277#define mmVGT_RESET_DEBUG_BASE_IDX 0 278#define mmVGT_STRMOUT_DELAY 0x0233 279#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 280#define mmVGT_FIFO_DEPTHS 0x0234 281#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 282#define mmVGT_GS_VERTEX_REUSE 0x0235 283#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 284#define mmVGT_MC_LAT_CNTL 0x0236 285#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 286#define mmIA_CNTL_STATUS 0x0237 287#define mmIA_CNTL_STATUS_BASE_IDX 0 288#define mmVGT_CNTL_STATUS 0x023c 289#define mmVGT_CNTL_STATUS_BASE_IDX 0 290#define mmWD_CNTL_STATUS 0x023f 291#define mmWD_CNTL_STATUS_BASE_IDX 0 292#define mmCC_GC_PRIM_CONFIG 0x0240 293#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 294#define mmGC_USER_PRIM_CONFIG 0x0241 295#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 296#define mmWD_QOS 0x0242 297#define mmWD_QOS_BASE_IDX 0 298#define mmWD_UTCL1_CNTL 0x0243 299#define mmWD_UTCL1_CNTL_BASE_IDX 0 300#define mmWD_UTCL1_STATUS 0x0244 301#define mmWD_UTCL1_STATUS_BASE_IDX 0 302#define mmIA_UTCL1_CNTL 0x0246 303#define mmIA_UTCL1_CNTL_BASE_IDX 0 304#define mmIA_UTCL1_STATUS 0x0247 305#define mmIA_UTCL1_STATUS_BASE_IDX 0 306#define mmVGT_SYS_CONFIG 0x0263 307#define mmVGT_SYS_CONFIG_BASE_IDX 0 308#define mmVGT_VS_MAX_WAVE_ID 0x0268 309#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 310#define mmVGT_GS_MAX_WAVE_ID 0x0269 311#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 312#define mmGFX_PIPE_CONTROL 0x026d 313#define mmGFX_PIPE_CONTROL_BASE_IDX 0 314#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f 315#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 316#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270 317#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 318#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271 319#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 320#define mmVGT_DMA_CONTROL 0x0272 321#define mmVGT_DMA_CONTROL_BASE_IDX 0 322#define mmVGT_DMA_LS_HS_CONFIG 0x0273 323#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 324#define mmWD_BUF_RESOURCE_1 0x0276 325#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 326#define mmWD_BUF_RESOURCE_2 0x0277 327#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 328#define mmPA_CL_CNTL_STATUS 0x0284 329#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 330#define mmPA_CL_ENHANCE 0x0285 331#define mmPA_CL_ENHANCE_BASE_IDX 0 332#define mmPA_CL_RESET_DEBUG 0x0286 333#define mmPA_CL_RESET_DEBUG_BASE_IDX 0 334#define mmPA_SU_CNTL_STATUS 0x0294 335#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 336#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295 337#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 338#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 339#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 340#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 341#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 342#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 343#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 344#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 345#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 346#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc 347#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 348#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd 349#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 350#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce 351#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 352#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf 353#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 354#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 355#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 356#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1 357#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 358#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2 359#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 360#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3 361#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 362#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4 363#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 364#define mmPA_SC_FIFO_SIZE 0x02f3 365#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 366#define mmPA_SC_IF_FIFO_SIZE 0x02f5 367#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 368#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 369#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 370#define mmPA_UTCL1_CNTL1 0x02f9 371#define mmPA_UTCL1_CNTL1_BASE_IDX 0 372#define mmPA_UTCL1_CNTL2 0x02fa 373#define mmPA_UTCL1_CNTL2_BASE_IDX 0 374#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb 375#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 376#define mmPA_SC_ENHANCE 0x02fc 377#define mmPA_SC_ENHANCE_BASE_IDX 0 378#define mmPA_SC_ENHANCE_1 0x02fd 379#define mmPA_SC_ENHANCE_1_BASE_IDX 0 380#define mmPA_SC_DSM_CNTL 0x02fe 381#define mmPA_SC_DSM_CNTL_BASE_IDX 0 382#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff 383#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 384 385 386// addressBlock: gc_sqdec 387// base address: 0x8c00 388#define mmSQ_CONFIG 0x0300 389#define mmSQ_CONFIG_BASE_IDX 0 390#define mmSQC_CONFIG 0x0301 391#define mmSQC_CONFIG_BASE_IDX 0 392#define mmLDS_CONFIG 0x0302 393#define mmLDS_CONFIG_BASE_IDX 0 394#define mmSQ_RANDOM_WAVE_PRI 0x0303 395#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 396#define mmSQ_REG_CREDITS 0x0304 397#define mmSQ_REG_CREDITS_BASE_IDX 0 398#define mmSQ_FIFO_SIZES 0x0305 399#define mmSQ_FIFO_SIZES_BASE_IDX 0 400#define mmSQ_DSM_CNTL 0x0306 401#define mmSQ_DSM_CNTL_BASE_IDX 0 402#define mmSQ_DSM_CNTL2 0x0307 403#define mmSQ_DSM_CNTL2_BASE_IDX 0 404#define mmSQ_RUNTIME_CONFIG 0x0308 405#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 406#define mmSH_MEM_BASES 0x030a 407#define mmSH_MEM_BASES_BASE_IDX 0 408#define mmSH_MEM_CONFIG 0x030d 409#define mmSH_MEM_CONFIG_BASE_IDX 0 410#define mmCC_GC_SHADER_RATE_CONFIG 0x0312 411#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 412#define mmGC_USER_SHADER_RATE_CONFIG 0x0313 413#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 414#define mmSQ_INTERRUPT_AUTO_MASK 0x0314 415#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 416#define mmSQ_INTERRUPT_MSG_CTRL 0x0315 417#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 418#define mmSQ_UTCL1_CNTL1 0x0317 419#define mmSQ_UTCL1_CNTL1_BASE_IDX 0 420#define mmSQ_UTCL1_CNTL2 0x0318 421#define mmSQ_UTCL1_CNTL2_BASE_IDX 0 422#define mmSQ_UTCL1_STATUS 0x0319 423#define mmSQ_UTCL1_STATUS_BASE_IDX 0 424#define mmSQ_SHADER_TBA_LO 0x031c 425#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 426#define mmSQ_SHADER_TBA_HI 0x031d 427#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 428#define mmSQ_SHADER_TMA_LO 0x031e 429#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 430#define mmSQ_SHADER_TMA_HI 0x031f 431#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 432#define mmSQC_DSM_CNTL 0x0320 433#define mmSQC_DSM_CNTL_BASE_IDX 0 434#define mmSQC_DSM_CNTLA 0x0321 435#define mmSQC_DSM_CNTLA_BASE_IDX 0 436#define mmSQC_DSM_CNTLB 0x0322 437#define mmSQC_DSM_CNTLB_BASE_IDX 0 438#define mmSQC_DSM_CNTL2 0x0325 439#define mmSQC_DSM_CNTL2_BASE_IDX 0 440#define mmSQC_DSM_CNTL2A 0x0326 441#define mmSQC_DSM_CNTL2A_BASE_IDX 0 442#define mmSQC_DSM_CNTL2B 0x0327 443#define mmSQC_DSM_CNTL2B_BASE_IDX 0 444#define mmSQC_EDC_FUE_CNTL 0x032b 445#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0 446#define mmSQC_EDC_CNT2 0x032c 447#define mmSQC_EDC_CNT2_BASE_IDX 0 448#define mmSQC_EDC_CNT3 0x032d 449#define mmSQC_EDC_CNT3_BASE_IDX 0 450#define mmSQ_REG_TIMESTAMP 0x0374 451#define mmSQ_REG_TIMESTAMP_BASE_IDX 0 452#define mmSQ_CMD_TIMESTAMP 0x0375 453#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0 454#define mmSQ_IND_INDEX 0x0378 455#define mmSQ_IND_INDEX_BASE_IDX 0 456#define mmSQ_IND_DATA 0x0379 457#define mmSQ_IND_DATA_BASE_IDX 0 458#define mmSQ_CMD 0x037b 459#define mmSQ_CMD_BASE_IDX 0 460#define mmSQ_TIME_HI 0x037c 461#define mmSQ_TIME_HI_BASE_IDX 0 462#define mmSQ_TIME_LO 0x037d 463#define mmSQ_TIME_LO_BASE_IDX 0 464#define mmSQ_DS_0 0x037f 465#define mmSQ_DS_0_BASE_IDX 0 466#define mmSQ_DS_1 0x037f 467#define mmSQ_DS_1_BASE_IDX 0 468#define mmSQ_EXP_0 0x037f 469#define mmSQ_EXP_0_BASE_IDX 0 470#define mmSQ_EXP_1 0x037f 471#define mmSQ_EXP_1_BASE_IDX 0 472#define mmSQ_FLAT_0 0x037f 473#define mmSQ_FLAT_0_BASE_IDX 0 474#define mmSQ_FLAT_1 0x037f 475#define mmSQ_FLAT_1_BASE_IDX 0 476#define mmSQ_GLBL_0 0x037f 477#define mmSQ_GLBL_0_BASE_IDX 0 478#define mmSQ_GLBL_1 0x037f 479#define mmSQ_GLBL_1_BASE_IDX 0 480#define mmSQ_INST 0x037f 481#define mmSQ_INST_BASE_IDX 0 482#define mmSQ_MIMG_0 0x037f 483#define mmSQ_MIMG_0_BASE_IDX 0 484#define mmSQ_MIMG_1 0x037f 485#define mmSQ_MIMG_1_BASE_IDX 0 486#define mmSQ_MTBUF_0 0x037f 487#define mmSQ_MTBUF_0_BASE_IDX 0 488#define mmSQ_MTBUF_1 0x037f 489#define mmSQ_MTBUF_1_BASE_IDX 0 490#define mmSQ_MUBUF_0 0x037f 491#define mmSQ_MUBUF_0_BASE_IDX 0 492#define mmSQ_MUBUF_1 0x037f 493#define mmSQ_MUBUF_1_BASE_IDX 0 494#define mmSQ_SCRATCH_0 0x037f 495#define mmSQ_SCRATCH_0_BASE_IDX 0 496#define mmSQ_SCRATCH_1 0x037f 497#define mmSQ_SCRATCH_1_BASE_IDX 0 498#define mmSQ_SMEM_0 0x037f 499#define mmSQ_SMEM_0_BASE_IDX 0 500#define mmSQ_SMEM_1 0x037f 501#define mmSQ_SMEM_1_BASE_IDX 0 502#define mmSQ_SOP1 0x037f 503#define mmSQ_SOP1_BASE_IDX 0 504#define mmSQ_SOP2 0x037f 505#define mmSQ_SOP2_BASE_IDX 0 506#define mmSQ_SOPC 0x037f 507#define mmSQ_SOPC_BASE_IDX 0 508#define mmSQ_SOPK 0x037f 509#define mmSQ_SOPK_BASE_IDX 0 510#define mmSQ_SOPP 0x037f 511#define mmSQ_SOPP_BASE_IDX 0 512#define mmSQ_VINTRP 0x037f 513#define mmSQ_VINTRP_BASE_IDX 0 514#define mmSQ_VOP1 0x037f 515#define mmSQ_VOP1_BASE_IDX 0 516#define mmSQ_VOP2 0x037f 517#define mmSQ_VOP2_BASE_IDX 0 518#define mmSQ_VOP3P_0 0x037f 519#define mmSQ_VOP3P_0_BASE_IDX 0 520#define mmSQ_VOP3P_1 0x037f 521#define mmSQ_VOP3P_1_BASE_IDX 0 522#define mmSQ_VOP3_0 0x037f 523#define mmSQ_VOP3_0_BASE_IDX 0 524#define mmSQ_VOP3_0_SDST_ENC 0x037f 525#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0 526#define mmSQ_VOP3_1 0x037f 527#define mmSQ_VOP3_1_BASE_IDX 0 528#define mmSQ_VOPC 0x037f 529#define mmSQ_VOPC_BASE_IDX 0 530#define mmSQ_VOP_DPP 0x037f 531#define mmSQ_VOP_DPP_BASE_IDX 0 532#define mmSQ_VOP_SDWA 0x037f 533#define mmSQ_VOP_SDWA_BASE_IDX 0 534#define mmSQ_VOP_SDWA_SDST_ENC 0x037f 535#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 536#define mmSQ_LB_CTR_CTRL 0x0398 537#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 538#define mmSQ_LB_DATA0 0x0399 539#define mmSQ_LB_DATA0_BASE_IDX 0 540#define mmSQ_LB_DATA1 0x039a 541#define mmSQ_LB_DATA1_BASE_IDX 0 542#define mmSQ_LB_DATA2 0x039b 543#define mmSQ_LB_DATA2_BASE_IDX 0 544#define mmSQ_LB_DATA3 0x039c 545#define mmSQ_LB_DATA3_BASE_IDX 0 546#define mmSQ_LB_CTR_SEL 0x039d 547#define mmSQ_LB_CTR_SEL_BASE_IDX 0 548#define mmSQ_LB_CTR0_CU 0x039e 549#define mmSQ_LB_CTR0_CU_BASE_IDX 0 550#define mmSQ_LB_CTR1_CU 0x039f 551#define mmSQ_LB_CTR1_CU_BASE_IDX 0 552#define mmSQ_LB_CTR2_CU 0x03a0 553#define mmSQ_LB_CTR2_CU_BASE_IDX 0 554#define mmSQ_LB_CTR3_CU 0x03a1 555#define mmSQ_LB_CTR3_CU_BASE_IDX 0 556#define mmSQC_EDC_CNT 0x03a2 557#define mmSQC_EDC_CNT_BASE_IDX 0 558#define mmSQ_EDC_SEC_CNT 0x03a3 559#define mmSQ_EDC_SEC_CNT_BASE_IDX 0 560#define mmSQ_EDC_DED_CNT 0x03a4 561#define mmSQ_EDC_DED_CNT_BASE_IDX 0 562#define mmSQ_EDC_INFO 0x03a5 563#define mmSQ_EDC_INFO_BASE_IDX 0 564#define mmSQ_EDC_CNT 0x03a6 565#define mmSQ_EDC_CNT_BASE_IDX 0 566#define mmSQ_EDC_FUE_CNTL 0x03a7 567#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0 568#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0 569#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 570#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0 571#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 572#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0 573#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 574#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 575#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 576#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 577#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 578#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 579#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 580#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0 581#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 582#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 583#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 584#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 585#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 586#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 587#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 588#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 589#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 590#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 591#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 592#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 593#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 594#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0 595#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 596#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 597#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 598#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 599#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 600#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 601#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 602#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 603#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 604#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 605#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 606#define mmSQ_WREXEC_EXEC_HI 0x03b1 607#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 608#define mmSQ_WREXEC_EXEC_LO 0x03b1 609#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 610#define mmSQ_BUF_RSRC_WORD0 0x03c0 611#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0 612#define mmSQ_BUF_RSRC_WORD1 0x03c1 613#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0 614#define mmSQ_BUF_RSRC_WORD2 0x03c2 615#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0 616#define mmSQ_BUF_RSRC_WORD3 0x03c3 617#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0 618#define mmSQ_IMG_RSRC_WORD0 0x03c4 619#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0 620#define mmSQ_IMG_RSRC_WORD1 0x03c5 621#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0 622#define mmSQ_IMG_RSRC_WORD2 0x03c6 623#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0 624#define mmSQ_IMG_RSRC_WORD3 0x03c7 625#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0 626#define mmSQ_IMG_RSRC_WORD4 0x03c8 627#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0 628#define mmSQ_IMG_RSRC_WORD5 0x03c9 629#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0 630#define mmSQ_IMG_RSRC_WORD6 0x03ca 631#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0 632#define mmSQ_IMG_RSRC_WORD7 0x03cb 633#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0 634#define mmSQ_IMG_SAMP_WORD0 0x03cc 635#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0 636#define mmSQ_IMG_SAMP_WORD1 0x03cd 637#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0 638#define mmSQ_IMG_SAMP_WORD2 0x03ce 639#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0 640#define mmSQ_IMG_SAMP_WORD3 0x03cf 641#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0 642#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0 643#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 644#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1 645#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 646#define mmSQ_M0_GPR_IDX_WORD 0x03d2 647#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0 648#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3 649#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 650#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4 651#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 652#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5 653#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 654#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6 655#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 656#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7 657#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 658#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8 659#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 660 661 662// addressBlock: gc_shsdec 663// base address: 0x9000 664#define mmSX_DEBUG_BUSY 0x0414 665#define mmSX_DEBUG_BUSY_BASE_IDX 0 666#define mmSX_DEBUG_BUSY_2 0x0415 667#define mmSX_DEBUG_BUSY_2_BASE_IDX 0 668#define mmSX_DEBUG_BUSY_3 0x0416 669#define mmSX_DEBUG_BUSY_3_BASE_IDX 0 670#define mmSX_DEBUG_BUSY_4 0x0417 671#define mmSX_DEBUG_BUSY_4_BASE_IDX 0 672#define mmSX_DEBUG_BUSY_5 0x0418 673#define mmSX_DEBUG_BUSY_5_BASE_IDX 0 674#define mmSX_DEBUG_1 0x0419 675#define mmSX_DEBUG_1_BASE_IDX 0 676#define mmSPI_PS_MAX_WAVE_ID 0x043a 677#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 678#define mmSPI_START_PHASE 0x043b 679#define mmSPI_START_PHASE_BASE_IDX 0 680#define mmSPI_GFX_CNTL 0x043c 681#define mmSPI_GFX_CNTL_BASE_IDX 0 682#define mmSPI_DEBUG_READ 0x0442 683#define mmSPI_DEBUG_READ_BASE_IDX 0 684#define mmSPI_DSM_CNTL 0x0443 685#define mmSPI_DSM_CNTL_BASE_IDX 0 686#define mmSPI_DSM_CNTL2 0x0444 687#define mmSPI_DSM_CNTL2_BASE_IDX 0 688#define mmSPI_EDC_CNT 0x0445 689#define mmSPI_EDC_CNT_BASE_IDX 0 690#define mmSPI_DEBUG_BUSY 0x0450 691#define mmSPI_DEBUG_BUSY_BASE_IDX 0 692#define mmSPI_CONFIG_PS_CU_EN 0x0452 693#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 694#define mmSPI_WF_LIFETIME_CNTL 0x04aa 695#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 696#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab 697#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 698#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac 699#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 700#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad 701#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 702#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae 703#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 704#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af 705#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 706#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0 707#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 708#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1 709#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 710#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2 711#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 712#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3 713#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 714#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4 715#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 716#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5 717#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 718#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6 719#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 720#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7 721#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 722#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8 723#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 724#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9 725#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 726#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba 727#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 728#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb 729#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 730#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc 731#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 732#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd 733#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 734#define mmSPI_WF_LIFETIME_STATUS_9 0x04be 735#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 736#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf 737#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 738#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0 739#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 740#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1 741#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 742#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2 743#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 744#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3 745#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 746#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4 747#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 748#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5 749#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 750#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6 751#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 752#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7 753#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 754#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8 755#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 756#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9 757#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 758#define mmSPI_WF_LIFETIME_DEBUG 0x04ca 759#define mmSPI_WF_LIFETIME_DEBUG_BASE_IDX 0 760#define mmSPI_LB_CTR_CTRL 0x04d4 761#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 762#define mmSPI_LB_CU_MASK 0x04d5 763#define mmSPI_LB_CU_MASK_BASE_IDX 0 764#define mmSPI_LB_DATA_REG 0x04d6 765#define mmSPI_LB_DATA_REG_BASE_IDX 0 766#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 767#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 768#define mmSPI_GDS_CREDITS 0x04d8 769#define mmSPI_GDS_CREDITS_BASE_IDX 0 770#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 771#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 772#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da 773#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 774#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db 775#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 776#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc 777#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 778#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd 779#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 780#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de 781#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 782#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df 783#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 784#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 785#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 786#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 787#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 788#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 789#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 790#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 791#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 792#define mmSPI_LB_DATA_WAVES 0x04e4 793#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 794#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 795#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 796#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 797#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 798#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 799#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 800#define mmSPIS_DEBUG_READ 0x04ea 801#define mmSPIS_DEBUG_READ_BASE_IDX 0 802#define mmBCI_DEBUG_READ 0x04eb 803#define mmBCI_DEBUG_READ_BASE_IDX 0 804#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec 805#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 806#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed 807#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 808#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee 809#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 810#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef 811#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 812#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 813#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 814#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 815#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 816#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 817#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 818#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 819#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 820#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 821#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 822#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 823#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 824 825 826// addressBlock: gc_tpdec 827// base address: 0x9400 828#define mmTD_CNTL 0x0525 829#define mmTD_CNTL_BASE_IDX 0 830#define mmTD_STATUS 0x0526 831#define mmTD_STATUS_BASE_IDX 0 832#define mmTD_EDC_CNT 0x052e 833#define mmTD_EDC_CNT_BASE_IDX 0 834#define mmTD_DSM_CNTL 0x052f 835#define mmTD_DSM_CNTL_BASE_IDX 0 836#define mmTD_DSM_CNTL2 0x0530 837#define mmTD_DSM_CNTL2_BASE_IDX 0 838#define mmTD_SCRATCH 0x0533 839#define mmTD_SCRATCH_BASE_IDX 0 840#define mmTA_CNTL 0x0541 841#define mmTA_CNTL_BASE_IDX 0 842#define mmTA_CNTL_AUX 0x0542 843#define mmTA_CNTL_AUX_BASE_IDX 0 844#define mmTA_RESERVED_010C 0x0543 845#define mmTA_RESERVED_010C_BASE_IDX 0 846#define mmTA_STATUS 0x0548 847#define mmTA_STATUS_BASE_IDX 0 848#define mmTA_SCRATCH 0x0564 849#define mmTA_SCRATCH_BASE_IDX 0 850#define mmTA_EDC_CNT 0x0586 851#define mmTA_EDC_CNT_BASE_IDX 0 852 853 854// addressBlock: gc_gdsdec 855// base address: 0x9700 856#define mmGDS_CONFIG 0x05c0 857#define mmGDS_CONFIG_BASE_IDX 0 858#define mmGDS_CNTL_STATUS 0x05c1 859#define mmGDS_CNTL_STATUS_BASE_IDX 0 860#define mmGDS_ENHANCE2 0x05c2 861#define mmGDS_ENHANCE2_BASE_IDX 0 862#define mmGDS_PROTECTION_FAULT 0x05c3 863#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 864#define mmGDS_VM_PROTECTION_FAULT 0x05c4 865#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 866#define mmGDS_EDC_CNT 0x05c5 867#define mmGDS_EDC_CNT_BASE_IDX 0 868#define mmGDS_EDC_GRBM_CNT 0x05c6 869#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 870#define mmGDS_EDC_OA_DED 0x05c7 871#define mmGDS_EDC_OA_DED_BASE_IDX 0 872#define mmGDS_DSM_CNTL 0x05ca 873#define mmGDS_DSM_CNTL_BASE_IDX 0 874#define mmGDS_EDC_OA_PHY_CNT 0x05cb 875#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 876#define mmGDS_EDC_OA_PIPE_CNT 0x05cc 877#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 878#define mmGDS_DSM_CNTL2 0x05cd 879#define mmGDS_DSM_CNTL2_BASE_IDX 0 880#define mmGDS_WD_GDS_CSB 0x05ce 881#define mmGDS_WD_GDS_CSB_BASE_IDX 0 882 883 884// addressBlock: gc_rbdec 885// base address: 0x9800 886#define mmDB_DEBUG 0x060c 887#define mmDB_DEBUG_BASE_IDX 0 888#define mmDB_DEBUG2 0x060d 889#define mmDB_DEBUG2_BASE_IDX 0 890#define mmDB_DEBUG3 0x060e 891#define mmDB_DEBUG3_BASE_IDX 0 892#define mmDB_DEBUG4 0x060f 893#define mmDB_DEBUG4_BASE_IDX 0 894#define mmDB_CREDIT_LIMIT 0x0614 895#define mmDB_CREDIT_LIMIT_BASE_IDX 0 896#define mmDB_WATERMARKS 0x0615 897#define mmDB_WATERMARKS_BASE_IDX 0 898#define mmDB_SUBTILE_CONTROL 0x0616 899#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 900#define mmDB_FREE_CACHELINES 0x0617 901#define mmDB_FREE_CACHELINES_BASE_IDX 0 902#define mmDB_FIFO_DEPTH1 0x0618 903#define mmDB_FIFO_DEPTH1_BASE_IDX 0 904#define mmDB_FIFO_DEPTH2 0x0619 905#define mmDB_FIFO_DEPTH2_BASE_IDX 0 906#define mmDB_EXCEPTION_CONTROL 0x061a 907#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 908#define mmDB_RING_CONTROL 0x061b 909#define mmDB_RING_CONTROL_BASE_IDX 0 910#define mmDB_MEM_ARB_WATERMARKS 0x061c 911#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 912#define mmDB_RMI_CACHE_POLICY 0x061e 913#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0 914#define mmDB_DFSM_CONFIG 0x0630 915#define mmDB_DFSM_CONFIG_BASE_IDX 0 916#define mmDB_DFSM_WATERMARK 0x0631 917#define mmDB_DFSM_WATERMARK_BASE_IDX 0 918#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632 919#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 920#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633 921#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 922#define mmDB_DFSM_WATCHDOG 0x0634 923#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 924#define mmDB_DFSM_FLUSH_ENABLE 0x0635 925#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 926#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636 927#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 928#define mmCC_RB_REDUNDANCY 0x063c 929#define mmCC_RB_REDUNDANCY_BASE_IDX 0 930#define mmCC_RB_BACKEND_DISABLE 0x063d 931#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 932#define mmGB_ADDR_CONFIG 0x063e 933#define mmGB_ADDR_CONFIG_BASE_IDX 0 934#define mmGB_BACKEND_MAP 0x063f 935#define mmGB_BACKEND_MAP_BASE_IDX 0 936#define mmGB_GPU_ID 0x0640 937#define mmGB_GPU_ID_BASE_IDX 0 938#define mmCC_RB_DAISY_CHAIN 0x0641 939#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 940#define mmGB_ADDR_CONFIG_READ 0x0642 941#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 942#define mmGB_TILE_MODE0 0x0644 943#define mmGB_TILE_MODE0_BASE_IDX 0 944#define mmGB_TILE_MODE1 0x0645 945#define mmGB_TILE_MODE1_BASE_IDX 0 946#define mmGB_TILE_MODE2 0x0646 947#define mmGB_TILE_MODE2_BASE_IDX 0 948#define mmGB_TILE_MODE3 0x0647 949#define mmGB_TILE_MODE3_BASE_IDX 0 950#define mmGB_TILE_MODE4 0x0648 951#define mmGB_TILE_MODE4_BASE_IDX 0 952#define mmGB_TILE_MODE5 0x0649 953#define mmGB_TILE_MODE5_BASE_IDX 0 954#define mmGB_TILE_MODE6 0x064a 955#define mmGB_TILE_MODE6_BASE_IDX 0 956#define mmGB_TILE_MODE7 0x064b 957#define mmGB_TILE_MODE7_BASE_IDX 0 958#define mmGB_TILE_MODE8 0x064c 959#define mmGB_TILE_MODE8_BASE_IDX 0 960#define mmGB_TILE_MODE9 0x064d 961#define mmGB_TILE_MODE9_BASE_IDX 0 962#define mmGB_TILE_MODE10 0x064e 963#define mmGB_TILE_MODE10_BASE_IDX 0 964#define mmGB_TILE_MODE11 0x064f 965#define mmGB_TILE_MODE11_BASE_IDX 0 966#define mmGB_TILE_MODE12 0x0650 967#define mmGB_TILE_MODE12_BASE_IDX 0 968#define mmGB_TILE_MODE13 0x0651 969#define mmGB_TILE_MODE13_BASE_IDX 0 970#define mmGB_TILE_MODE14 0x0652 971#define mmGB_TILE_MODE14_BASE_IDX 0 972#define mmGB_TILE_MODE15 0x0653 973#define mmGB_TILE_MODE15_BASE_IDX 0 974#define mmGB_TILE_MODE16 0x0654 975#define mmGB_TILE_MODE16_BASE_IDX 0 976#define mmGB_TILE_MODE17 0x0655 977#define mmGB_TILE_MODE17_BASE_IDX 0 978#define mmGB_TILE_MODE18 0x0656 979#define mmGB_TILE_MODE18_BASE_IDX 0 980#define mmGB_TILE_MODE19 0x0657 981#define mmGB_TILE_MODE19_BASE_IDX 0 982#define mmGB_TILE_MODE20 0x0658 983#define mmGB_TILE_MODE20_BASE_IDX 0 984#define mmGB_TILE_MODE21 0x0659 985#define mmGB_TILE_MODE21_BASE_IDX 0 986#define mmGB_TILE_MODE22 0x065a 987#define mmGB_TILE_MODE22_BASE_IDX 0 988#define mmGB_TILE_MODE23 0x065b 989#define mmGB_TILE_MODE23_BASE_IDX 0 990#define mmGB_TILE_MODE24 0x065c 991#define mmGB_TILE_MODE24_BASE_IDX 0 992#define mmGB_TILE_MODE25 0x065d 993#define mmGB_TILE_MODE25_BASE_IDX 0 994#define mmGB_TILE_MODE26 0x065e 995#define mmGB_TILE_MODE26_BASE_IDX 0 996#define mmGB_TILE_MODE27 0x065f 997#define mmGB_TILE_MODE27_BASE_IDX 0 998#define mmGB_TILE_MODE28 0x0660 999#define mmGB_TILE_MODE28_BASE_IDX 0 1000#define mmGB_TILE_MODE29 0x0661
1001#define mmGB_TILE_MODE29_BASE_IDX 0 1002#define mmGB_TILE_MODE30 0x0662 1003#define mmGB_TILE_MODE30_BASE_IDX 0 1004#define mmGB_TILE_MODE31 0x0663 1005#define mmGB_TILE_MODE31_BASE_IDX 0 1006#define mmGB_MACROTILE_MODE0 0x0664 1007#define mmGB_MACROTILE_MODE0_BASE_IDX 0 1008#define mmGB_MACROTILE_MODE1 0x0665 1009#define mmGB_MACROTILE_MODE1_BASE_IDX 0 1010#define mmGB_MACROTILE_MODE2 0x0666 1011#define mmGB_MACROTILE_MODE2_BASE_IDX 0 1012#define mmGB_MACROTILE_MODE3 0x0667 1013#define mmGB_MACROTILE_MODE3_BASE_IDX 0 1014#define mmGB_MACROTILE_MODE4 0x0668 1015#define mmGB_MACROTILE_MODE4_BASE_IDX 0 1016#define mmGB_MACROTILE_MODE5 0x0669 1017#define mmGB_MACROTILE_MODE5_BASE_IDX 0 1018#define mmGB_MACROTILE_MODE6 0x066a 1019#define mmGB_MACROTILE_MODE6_BASE_IDX 0 1020#define mmGB_MACROTILE_MODE7 0x066b 1021#define mmGB_MACROTILE_MODE7_BASE_IDX 0 1022#define mmGB_MACROTILE_MODE8 0x066c 1023#define mmGB_MACROTILE_MODE8_BASE_IDX 0 1024#define mmGB_MACROTILE_MODE9 0x066d 1025#define mmGB_MACROTILE_MODE9_BASE_IDX 0 1026#define mmGB_MACROTILE_MODE10 0x066e 1027#define mmGB_MACROTILE_MODE10_BASE_IDX 0 1028#define mmGB_MACROTILE_MODE11 0x066f 1029#define mmGB_MACROTILE_MODE11_BASE_IDX 0 1030#define mmGB_MACROTILE_MODE12 0x0670 1031#define mmGB_MACROTILE_MODE12_BASE_IDX 0 1032#define mmGB_MACROTILE_MODE13 0x0671 1033#define mmGB_MACROTILE_MODE13_BASE_IDX 0 1034#define mmGB_MACROTILE_MODE14 0x0672 1035#define mmGB_MACROTILE_MODE14_BASE_IDX 0 1036#define mmGB_MACROTILE_MODE15 0x0673 1037#define mmGB_MACROTILE_MODE15_BASE_IDX 0 1038#define mmCB_HW_CONTROL 0x0680 1039#define mmCB_HW_CONTROL_BASE_IDX 0 1040#define mmCB_HW_CONTROL_1 0x0681 1041#define mmCB_HW_CONTROL_1_BASE_IDX 0 1042#define mmCB_HW_CONTROL_2 0x0682 1043#define mmCB_HW_CONTROL_2_BASE_IDX 0 1044#define mmCB_HW_CONTROL_3 0x0683 1045#define mmCB_HW_CONTROL_3_BASE_IDX 0 1046#define mmCB_HW_MEM_ARBITER_RD 0x0686 1047#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 1048#define mmCB_HW_MEM_ARBITER_WR 0x0687 1049#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 1050#define mmCB_DCC_CONFIG 0x0688 1051#define mmCB_DCC_CONFIG_BASE_IDX 0 1052#define mmGC_USER_RB_REDUNDANCY 0x06de 1053#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 1054#define mmGC_USER_RB_BACKEND_DISABLE 0x06df 1055#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 1056 1057 1058// addressBlock: gc_ea_gceadec2 1059// base address: 0x9c00 1060#define mmGCEA_EDC_CNT 0x0706 1061#define mmGCEA_EDC_CNT_BASE_IDX 0 1062#define mmGCEA_EDC_CNT2 0x0707 1063#define mmGCEA_EDC_CNT2_BASE_IDX 0 1064 1065// addressBlock: gc_rmi_rmidec 1066// base address: 0x9e00 1067#define mmRMI_GENERAL_CNTL 0x0780 1068#define mmRMI_GENERAL_CNTL_BASE_IDX 0 1069#define mmRMI_GENERAL_CNTL1 0x0781 1070#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 1071#define mmRMI_GENERAL_STATUS 0x0782 1072#define mmRMI_GENERAL_STATUS_BASE_IDX 0 1073#define mmRMI_SUBBLOCK_STATUS0 0x0783 1074#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 1075#define mmRMI_SUBBLOCK_STATUS1 0x0784 1076#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 1077#define mmRMI_SUBBLOCK_STATUS2 0x0785 1078#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 1079#define mmRMI_SUBBLOCK_STATUS3 0x0786 1080#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 1081#define mmRMI_XBAR_CONFIG 0x0787 1082#define mmRMI_XBAR_CONFIG_BASE_IDX 0 1083#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788 1084#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 1085#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789 1086#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 1087#define mmRMI_DEMUX_CNTL 0x078a 1088#define mmRMI_DEMUX_CNTL_BASE_IDX 0 1089#define mmRMI_UTCL1_CNTL1 0x078b 1090#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 1091#define mmRMI_UTCL1_CNTL2 0x078c 1092#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 1093#define mmRMI_UTC_UNIT_CONFIG 0x078d 1094#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 1095#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e 1096#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 1097#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f 1098#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 1099#define mmRMI_SCOREBOARD_CNTL 0x0790 1100#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 1101#define mmRMI_SCOREBOARD_STATUS0 0x0791 1102#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 1103#define mmRMI_SCOREBOARD_STATUS1 0x0792 1104#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 1105#define mmRMI_SCOREBOARD_STATUS2 0x0793 1106#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 1107#define mmRMI_XBAR_ARBITER_CONFIG 0x0794 1108#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 1109#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795 1110#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 1111#define mmRMI_CLOCK_CNTRL 0x0796 1112#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 1113#define mmRMI_UTCL1_STATUS 0x0797 1114#define mmRMI_UTCL1_STATUS_BASE_IDX 0 1115#define mmRMI_XNACK_DEBUG 0x079d 1116#define mmRMI_XNACK_DEBUG_BASE_IDX 0 1117#define mmRMI_SPARE 0x079e 1118#define mmRMI_SPARE_BASE_IDX 0 1119#define mmRMI_SPARE_1 0x079f 1120#define mmRMI_SPARE_1_BASE_IDX 0 1121#define mmRMI_SPARE_2 0x07a0 1122#define mmRMI_SPARE_2_BASE_IDX 0 1123 1124 1125// addressBlock: gc_utcl2_atcl2dec 1126// base address: 0xa000 1127#define mmATC_L2_CNTL 0x0800 1128#define mmATC_L2_CNTL_BASE_IDX 0 1129#define mmATC_L2_CNTL2 0x0801 1130#define mmATC_L2_CNTL2_BASE_IDX 0 1131#define mmATC_L2_CACHE_DATA0 0x0804 1132#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 1133#define mmATC_L2_CACHE_DATA1 0x0805 1134#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 1135#define mmATC_L2_CACHE_DATA2 0x0806 1136#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 1137#define mmATC_L2_CNTL3 0x0807 1138#define mmATC_L2_CNTL3_BASE_IDX 0 1139#define mmATC_L2_STATUS 0x0808 1140#define mmATC_L2_STATUS_BASE_IDX 0 1141#define mmATC_L2_STATUS2 0x0809 1142#define mmATC_L2_STATUS2_BASE_IDX 0 1143#define mmATC_L2_MISC_CG 0x080a 1144#define mmATC_L2_MISC_CG_BASE_IDX 0 1145#define mmATC_L2_MEM_POWER_LS 0x080b 1146#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 1147#define mmATC_L2_CGTT_CLK_CTRL 0x080c 1148#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1149 1150 1151// addressBlock: gc_utcl2_vml2pfdec 1152// base address: 0xa100 1153#define mmVM_L2_CNTL 0x0840 1154#define mmVM_L2_CNTL_BASE_IDX 0 1155#define mmVM_L2_CNTL2 0x0841 1156#define mmVM_L2_CNTL2_BASE_IDX 0 1157#define mmVM_L2_CNTL3 0x0842 1158#define mmVM_L2_CNTL3_BASE_IDX 0 1159#define mmVM_L2_STATUS 0x0843 1160#define mmVM_L2_STATUS_BASE_IDX 0 1161#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844 1162#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1163#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 1164#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1165#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 1166#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1167#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847 1168#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1169#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848 1170#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1171#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 1172#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1173#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a 1174#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1175#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b 1176#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1177#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c 1178#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1179#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d 1180#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1181#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e 1182#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1183#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f 1184#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1185#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 1186#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1187#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 1188#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1189#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 1190#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1191#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 1192#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1193#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 1194#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1195#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 1196#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1197#define mmVM_L2_CNTL4 0x0857 1198#define mmVM_L2_CNTL4_BASE_IDX 0 1199#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858 1200#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1201#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859 1202#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1203#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a 1204#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1205#define mmVM_L2_CACHE_PARITY_CNTL 0x085b 1206#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1207#define mmVM_L2_CGTT_CLK_CTRL 0x085e 1208#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1209 1210 1211// addressBlock: gc_utcl2_vml2vcdec 1212// base address: 0xa200 1213#define mmVM_CONTEXT0_CNTL 0x0880 1214#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 1215#define mmVM_CONTEXT1_CNTL 0x0881 1216#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 1217#define mmVM_CONTEXT2_CNTL 0x0882 1218#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 1219#define mmVM_CONTEXT3_CNTL 0x0883 1220#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 1221#define mmVM_CONTEXT4_CNTL 0x0884 1222#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 1223#define mmVM_CONTEXT5_CNTL 0x0885 1224#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 1225#define mmVM_CONTEXT6_CNTL 0x0886 1226#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 1227#define mmVM_CONTEXT7_CNTL 0x0887 1228#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 1229#define mmVM_CONTEXT8_CNTL 0x0888 1230#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 1231#define mmVM_CONTEXT9_CNTL 0x0889 1232#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 1233#define mmVM_CONTEXT10_CNTL 0x088a 1234#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 1235#define mmVM_CONTEXT11_CNTL 0x088b 1236#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 1237#define mmVM_CONTEXT12_CNTL 0x088c 1238#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 1239#define mmVM_CONTEXT13_CNTL 0x088d 1240#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 1241#define mmVM_CONTEXT14_CNTL 0x088e 1242#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 1243#define mmVM_CONTEXT15_CNTL 0x088f 1244#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 1245#define mmVM_CONTEXTS_DISABLE 0x0890 1246#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 1247#define mmVM_INVALIDATE_ENG0_SEM 0x0891 1248#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1249#define mmVM_INVALIDATE_ENG1_SEM 0x0892 1250#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1251#define mmVM_INVALIDATE_ENG2_SEM 0x0893 1252#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1253#define mmVM_INVALIDATE_ENG3_SEM 0x0894 1254#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1255#define mmVM_INVALIDATE_ENG4_SEM 0x0895 1256#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1257#define mmVM_INVALIDATE_ENG5_SEM 0x0896 1258#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1259#define mmVM_INVALIDATE_ENG6_SEM 0x0897 1260#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1261#define mmVM_INVALIDATE_ENG7_SEM 0x0898 1262#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1263#define mmVM_INVALIDATE_ENG8_SEM 0x0899 1264#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1265#define mmVM_INVALIDATE_ENG9_SEM 0x089a 1266#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1267#define mmVM_INVALIDATE_ENG10_SEM 0x089b 1268#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1269#define mmVM_INVALIDATE_ENG11_SEM 0x089c 1270#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1271#define mmVM_INVALIDATE_ENG12_SEM 0x089d 1272#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1273#define mmVM_INVALIDATE_ENG13_SEM 0x089e 1274#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1275#define mmVM_INVALIDATE_ENG14_SEM 0x089f 1276#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1277#define mmVM_INVALIDATE_ENG15_SEM 0x08a0 1278#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1279#define mmVM_INVALIDATE_ENG16_SEM 0x08a1 1280#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1281#define mmVM_INVALIDATE_ENG17_SEM 0x08a2 1282#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1283#define mmVM_INVALIDATE_ENG0_REQ 0x08a3 1284#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1285#define mmVM_INVALIDATE_ENG1_REQ 0x08a4 1286#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1287#define mmVM_INVALIDATE_ENG2_REQ 0x08a5 1288#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1289#define mmVM_INVALIDATE_ENG3_REQ 0x08a6 1290#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1291#define mmVM_INVALIDATE_ENG4_REQ 0x08a7 1292#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1293#define mmVM_INVALIDATE_ENG5_REQ 0x08a8 1294#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1295#define mmVM_INVALIDATE_ENG6_REQ 0x08a9 1296#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1297#define mmVM_INVALIDATE_ENG7_REQ 0x08aa 1298#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1299#define mmVM_INVALIDATE_ENG8_REQ 0x08ab 1300#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1301#define mmVM_INVALIDATE_ENG9_REQ 0x08ac 1302#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1303#define mmVM_INVALIDATE_ENG10_REQ 0x08ad 1304#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1305#define mmVM_INVALIDATE_ENG11_REQ 0x08ae 1306#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1307#define mmVM_INVALIDATE_ENG12_REQ 0x08af 1308#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1309#define mmVM_INVALIDATE_ENG13_REQ 0x08b0 1310#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1311#define mmVM_INVALIDATE_ENG14_REQ 0x08b1 1312#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1313#define mmVM_INVALIDATE_ENG15_REQ 0x08b2 1314#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1315#define mmVM_INVALIDATE_ENG16_REQ 0x08b3 1316#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1317#define mmVM_INVALIDATE_ENG17_REQ 0x08b4 1318#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1319#define mmVM_INVALIDATE_ENG0_ACK 0x08b5 1320#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1321#define mmVM_INVALIDATE_ENG1_ACK 0x08b6 1322#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1323#define mmVM_INVALIDATE_ENG2_ACK 0x08b7 1324#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1325#define mmVM_INVALIDATE_ENG3_ACK 0x08b8 1326#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1327#define mmVM_INVALIDATE_ENG4_ACK 0x08b9 1328#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1329#define mmVM_INVALIDATE_ENG5_ACK 0x08ba 1330#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1331#define mmVM_INVALIDATE_ENG6_ACK 0x08bb 1332#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1333#define mmVM_INVALIDATE_ENG7_ACK 0x08bc 1334#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1335#define mmVM_INVALIDATE_ENG8_ACK 0x08bd 1336#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1337#define mmVM_INVALIDATE_ENG9_ACK 0x08be 1338#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1339#define mmVM_INVALIDATE_ENG10_ACK 0x08bf 1340#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1341#define mmVM_INVALIDATE_ENG11_ACK 0x08c0 1342#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1343#define mmVM_INVALIDATE_ENG12_ACK 0x08c1 1344#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1345#define mmVM_INVALIDATE_ENG13_ACK 0x08c2 1346#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1347#define mmVM_INVALIDATE_ENG14_ACK 0x08c3 1348#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1349#define mmVM_INVALIDATE_ENG15_ACK 0x08c4 1350#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1351#define mmVM_INVALIDATE_ENG16_ACK 0x08c5 1352#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1353#define mmVM_INVALIDATE_ENG17_ACK 0x08c6 1354#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1355#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 1356#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1357#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 1358#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1359#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 1360#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1361#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca 1362#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1363#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb 1364#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1365#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc 1366#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1367#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd 1368#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1369#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce 1370#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1371#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf 1372#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1373#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 1374#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1375#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 1376#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1377#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 1378#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1379#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 1380#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1381#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 1382#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1383#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 1384#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1385#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 1386#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1387#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 1388#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1389#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 1390#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1391#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 1392#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1393#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da 1394#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1395#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db 1396#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1397#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc 1398#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1399#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd 1400#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1401#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de 1402#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1403#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df 1404#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1405#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 1406#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1407#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 1408#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1409#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 1410#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1411#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 1412#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1413#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 1414#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1415#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 1416#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1417#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 1418#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1419#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 1420#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1421#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 1422#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1423#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 1424#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1425#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea 1426#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1427#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb 1428#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1429#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec 1430#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1431#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed 1432#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1433#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee 1434#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1435#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef 1436#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1437#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 1438#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1439#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 1440#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1441#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 1442#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1443#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 1444#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1445#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 1446#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1447#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 1448#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1449#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 1450#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1451#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 1452#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1453#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 1454#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1455#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 1456#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1457#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa 1458#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1459#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb 1460#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1461#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc 1462#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1463#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd 1464#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1465#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe 1466#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1467#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff 1468#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1469#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 1470#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1471#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 1472#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1473#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 1474#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1475#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 1476#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1477#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 1478#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1479#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 1480#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1481#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 1482#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1483#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 1484#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1485#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 1486#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1487#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 1488#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1489#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a 1490#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1491#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b 1492#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1493#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c 1494#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1495#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d 1496#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1497#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e 1498#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1499#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f 1500#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1501#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 1502#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1503#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 1504#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1505#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 1506#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1507#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 1508#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1509#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 1510#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1511#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 1512#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1513#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 1514#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1515#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 1516#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1517#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 1518#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1519#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 1520#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1521#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a 1522#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1523#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b 1524#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1525#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c 1526#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1527#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d 1528#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1529#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e 1530#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1531#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f 1532#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1533#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 1534#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1535#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 1536#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1537#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 1538#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1539#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 1540#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1541#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 1542#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1543#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 1544#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1545#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 1546#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1547#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 1548#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1549#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 1550#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1551#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 1552#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1553#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a 1554#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1555#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b 1556#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1557#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c 1558#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1559#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d 1560#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1561#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e 1562#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1563#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f 1564#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1565#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 1566#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1567#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 1568#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1569#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 1570#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1571#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 1572#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1573#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 1574#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1575#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 1576#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1577#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 1578#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1579#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 1580#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1581#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 1582#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1583#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 1584#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1585#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a 1586#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1587#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b 1588#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1589#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c 1590#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1591#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d 1592#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1593#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e 1594#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1595#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f 1596#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1597#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 1598#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1599#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 1600#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1601#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 1602#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1603#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 1604#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1605#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 1606#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1607#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 1608#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1609#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 1610#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1611#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 1612#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1613#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 1614#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1615#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 1616#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1617#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a 1618#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1619 1620 1621// addressBlock: gc_utcl2_vmsharedpfdec 1622// base address: 0xa590 1623#define mmMC_VM_NB_MMIOBASE 0x0964 1624#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 1625#define mmMC_VM_NB_MMIOLIMIT 0x0965 1626#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1627#define mmMC_VM_NB_PCI_CTRL 0x0966 1628#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 1629#define mmMC_VM_NB_PCI_ARB 0x0967 1630#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 1631#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968 1632#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1633#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969 1634#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1635#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a 1636#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1637#define mmMC_VM_FB_OFFSET 0x096b 1638#define mmMC_VM_FB_OFFSET_BASE_IDX 0 1639#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c 1640#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1641#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d 1642#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1643#define mmMC_VM_STEERING 0x096e 1644#define mmMC_VM_STEERING_BASE_IDX 0 1645#define mmMC_SHARED_VIRT_RESET_REQ 0x096f 1646#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1647#define mmMC_MEM_POWER_LS 0x0970 1648#define mmMC_MEM_POWER_LS_BASE_IDX 0 1649#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 1650#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1651#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 1652#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1653#define mmMC_VM_APT_CNTL 0x0973 1654#define mmMC_VM_APT_CNTL_BASE_IDX 0 1655#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 1656#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1657#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 1658#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1659#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 1660#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1661 1662 1663// addressBlock: gc_utcl2_vmsharedvcdec 1664// base address: 0xa600 1665#define mmMC_VM_FB_LOCATION_BASE 0x0980 1666#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1667#define mmMC_VM_FB_LOCATION_TOP 0x0981 1668#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1669#define mmMC_VM_AGP_TOP 0x0982 1670#define mmMC_VM_AGP_TOP_BASE_IDX 0 1671#define mmMC_VM_AGP_BOT 0x0983 1672#define mmMC_VM_AGP_BOT_BASE_IDX 0 1673#define mmMC_VM_AGP_BASE 0x0984 1674#define mmMC_VM_AGP_BASE_BASE_IDX 0 1675#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 1676#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1677#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 1678#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1679#define mmMC_VM_MX_L1_TLB_CNTL 0x0987 1680#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1681 1682 1683// addressBlock: gc_tcdec 1684// base address: 0xac00 1685#define mmTCP_INVALIDATE 0x0b00 1686#define mmTCP_INVALIDATE_BASE_IDX 0 1687#define mmTCP_STATUS 0x0b01 1688#define mmTCP_STATUS_BASE_IDX 0 1689#define mmTCP_CNTL 0x0b02 1690#define mmTCP_CNTL_BASE_IDX 0 1691#define mmTCP_CHAN_STEER_LO 0x0b03 1692#define mmTCP_CHAN_STEER_LO_BASE_IDX 0 1693#define mmTCP_CHAN_STEER_HI 0x0b04 1694#define mmTCP_CHAN_STEER_HI_BASE_IDX 0 1695#define mmTCP_ADDR_CONFIG 0x0b05 1696#define mmTCP_ADDR_CONFIG_BASE_IDX 0 1697#define mmTCP_CREDIT 0x0b06 1698#define mmTCP_CREDIT_BASE_IDX 0 1699#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 1700#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 1701#define mmTCP_EDC_CNT 0x0b17 1702#define mmTCP_EDC_CNT_BASE_IDX 0 1703#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a 1704#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 1705#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b 1706#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 1707#define mmTC_CFG_L1_STORE_POLICY 0x0b1c 1708#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0 1709#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d 1710#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 1711#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e 1712#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 1713#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f 1714#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 1715#define mmTC_CFG_L2_STORE_POLICY1 0x0b20 1716#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 1717#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21 1718#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 1719#define mmTC_CFG_L1_VOLATILE 0x0b22 1720#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0 1721#define mmTC_CFG_L2_VOLATILE 0x0b23 1722#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0 1723#define mmTCI_EDC_CNT 0x0b60 1724#define mmTCI_EDC_CNT_BASE_IDX 0 1725#define mmTCI_STATUS 0x0b61 1726#define mmTCI_STATUS_BASE_IDX 0 1727#define mmTCI_CNTL_1 0x0b62 1728#define mmTCI_CNTL_1_BASE_IDX 0 1729#define mmTCI_CNTL_2 0x0b63 1730#define mmTCI_CNTL_2_BASE_IDX 0 1731#define mmTCC_CTRL 0x0b80 1732#define mmTCC_CTRL_BASE_IDX 0 1733#define mmTCC_CTRL2 0x0b81 1734#define mmTCC_CTRL2_BASE_IDX 0 1735#define mmTCC_EDC_CNT 0x0b82 1736#define mmTCC_EDC_CNT_BASE_IDX 0 1737#define mmTCC_EDC_CNT2 0x0b83 1738#define mmTCC_EDC_CNT2_BASE_IDX 0 1739#define mmTCC_REDUNDANCY 0x0b84 1740#define mmTCC_REDUNDANCY_BASE_IDX 0 1741#define mmTCC_EXE_DISABLE 0x0b85 1742#define mmTCC_EXE_DISABLE_BASE_IDX 0 1743#define mmTCC_DSM_CNTL 0x0b86 1744#define mmTCC_DSM_CNTL_BASE_IDX 0 1745#define mmTCC_DSM_CNTLA 0x0b87 1746#define mmTCC_DSM_CNTLA_BASE_IDX 0 1747#define mmTCC_DSM_CNTL2 0x0b88 1748#define mmTCC_DSM_CNTL2_BASE_IDX 0 1749#define mmTCC_DSM_CNTL2A 0x0b89 1750#define mmTCC_DSM_CNTL2A_BASE_IDX 0 1751#define mmTCC_DSM_CNTL2B 0x0b8a 1752#define mmTCC_DSM_CNTL2B_BASE_IDX 0 1753#define mmTCC_WBINVL2 0x0b8b 1754#define mmTCC_WBINVL2_BASE_IDX 0 1755#define mmTCC_SOFT_RESET 0x0b8c 1756#define mmTCC_SOFT_RESET_BASE_IDX 0 1757#define mmTCA_CTRL 0x0bc0 1758#define mmTCA_CTRL_BASE_IDX 0 1759#define mmTCA_BURST_MASK 0x0bc1 1760#define mmTCA_BURST_MASK_BASE_IDX 0 1761#define mmTCA_BURST_CTRL 0x0bc2 1762#define mmTCA_BURST_CTRL_BASE_IDX 0 1763#define mmTCA_DSM_CNTL 0x0bc3 1764#define mmTCA_DSM_CNTL_BASE_IDX 0 1765#define mmTCA_DSM_CNTL2 0x0bc4 1766#define mmTCA_DSM_CNTL2_BASE_IDX 0 1767#define mmTCA_EDC_CNT 0x0bc5 1768#define mmTCA_EDC_CNT_BASE_IDX 0 1769 1770 1771// addressBlock: gc_shdec 1772// base address: 0xb000 1773#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07 1774#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 1775#define mmSPI_SHADER_PGM_LO_PS 0x0c08 1776#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 1777#define mmSPI_SHADER_PGM_HI_PS 0x0c09 1778#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 1779#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a 1780#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 1781#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b 1782#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 1783#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c 1784#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 1785#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d 1786#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 1787#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e 1788#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 1789#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f 1790#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 1791#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10 1792#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 1793#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11 1794#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 1795#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12 1796#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 1797#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13 1798#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 1799#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14 1800#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 1801#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15 1802#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 1803#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16 1804#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 1805#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17 1806#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 1807#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18 1808#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 1809#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19 1810#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 1811#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a 1812#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 1813#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b 1814#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 1815#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c 1816#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 1817#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d 1818#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 1819#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e 1820#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 1821#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f 1822#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 1823#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20 1824#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 1825#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21 1826#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 1827#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22 1828#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 1829#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23 1830#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 1831#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24 1832#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 1833#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25 1834#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 1835#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26 1836#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 1837#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27 1838#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 1839#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28 1840#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 1841#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29 1842#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 1843#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a 1844#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 1845#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b 1846#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 1847#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46 1848#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 1849#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47 1850#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 1851#define mmSPI_SHADER_PGM_LO_VS 0x0c48 1852#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 1853#define mmSPI_SHADER_PGM_HI_VS 0x0c49 1854#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 1855#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a 1856#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 1857#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b 1858#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 1859#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c 1860#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 1861#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d 1862#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 1863#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e 1864#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 1865#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f 1866#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 1867#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50 1868#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 1869#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51 1870#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 1871#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52 1872#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 1873#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53 1874#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 1875#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54 1876#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 1877#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55 1878#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 1879#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56 1880#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 1881#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57 1882#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 1883#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58 1884#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 1885#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59 1886#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 1887#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a 1888#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 1889#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b 1890#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 1891#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c 1892#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 1893#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d 1894#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 1895#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e 1896#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 1897#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f 1898#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 1899#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60 1900#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 1901#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61 1902#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 1903#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62 1904#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 1905#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63 1906#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 1907#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64 1908#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 1909#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65 1910#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 1911#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66 1912#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 1913#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67 1914#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 1915#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68 1916#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 1917#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69 1918#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 1919#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a 1920#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 1921#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b 1922#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 1923#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c 1924#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 1925#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81 1926#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 1927#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 1928#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 1929#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 1930#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 1931#define mmSPI_SHADER_PGM_LO_ES 0x0c84 1932#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 1933#define mmSPI_SHADER_PGM_HI_ES 0x0c85 1934#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 1935#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87 1936#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 1937#define mmSPI_SHADER_PGM_LO_GS 0x0c88 1938#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 1939#define mmSPI_SHADER_PGM_HI_GS 0x0c89 1940#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 1941#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a 1942#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 1943#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b 1944#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 1945#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc 1946#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 1947#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd 1948#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 1949#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce 1950#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 1951#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf 1952#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 1953#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0 1954#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 1955#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1 1956#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 1957#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2 1958#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 1959#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3 1960#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 1961#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4 1962#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 1963#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5 1964#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 1965#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6 1966#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 1967#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7 1968#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 1969#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8 1970#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 1971#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9 1972#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 1973#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda 1974#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 1975#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb 1976#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 1977#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc 1978#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 1979#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd 1980#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 1981#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde 1982#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 1983#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf 1984#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 1985#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0 1986#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 1987#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1 1988#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 1989#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2 1990#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 1991#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3 1992#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 1993#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4 1994#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 1995#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5 1996#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 1997#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6 1998#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 1999#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7 2000#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0
2001#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8 2002#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 2003#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9 2004#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 2005#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea 2006#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 2007#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb 2008#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 2009#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01 2010#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 2011#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 2012#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 2013#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 2014#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 2015#define mmSPI_SHADER_PGM_LO_LS 0x0d04 2016#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 2017#define mmSPI_SHADER_PGM_HI_LS 0x0d05 2018#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 2019#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07 2020#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 2021#define mmSPI_SHADER_PGM_LO_HS 0x0d08 2022#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 2023#define mmSPI_SHADER_PGM_HI_HS 0x0d09 2024#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 2025#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a 2026#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 2027#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b 2028#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 2029#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c 2030#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 2031#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d 2032#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 2033#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e 2034#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 2035#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f 2036#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 2037#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10 2038#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 2039#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11 2040#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 2041#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12 2042#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 2043#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13 2044#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 2045#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14 2046#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 2047#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15 2048#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 2049#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16 2050#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 2051#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17 2052#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 2053#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18 2054#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 2055#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19 2056#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 2057#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a 2058#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 2059#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b 2060#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 2061#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c 2062#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 2063#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d 2064#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 2065#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e 2066#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 2067#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f 2068#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 2069#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20 2070#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 2071#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21 2072#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 2073#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22 2074#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 2075#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23 2076#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 2077#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24 2078#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 2079#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25 2080#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 2081#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26 2082#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 2083#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27 2084#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 2085#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28 2086#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 2087#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29 2088#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 2089#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a 2090#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 2091#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b 2092#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 2093#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c 2094#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 2095#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d 2096#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 2097#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e 2098#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 2099#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f 2100#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 2101#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50 2102#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 2103#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51 2104#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 2105#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52 2106#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 2107#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53 2108#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 2109#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54 2110#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 2111#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55 2112#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 2113#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56 2114#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 2115#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57 2116#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 2117#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58 2118#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 2119#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59 2120#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 2121#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a 2122#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 2123#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b 2124#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 2125#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c 2126#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 2127#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d 2128#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 2129#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e 2130#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 2131#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f 2132#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 2133#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60 2134#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 2135#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61 2136#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 2137#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62 2138#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 2139#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63 2140#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 2141#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64 2142#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 2143#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65 2144#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 2145#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66 2146#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 2147#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67 2148#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 2149#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68 2150#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 2151#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69 2152#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 2153#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a 2154#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 2155#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b 2156#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 2157#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00 2158#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 2159#define mmCOMPUTE_DIM_X 0x0e01 2160#define mmCOMPUTE_DIM_X_BASE_IDX 0 2161#define mmCOMPUTE_DIM_Y 0x0e02 2162#define mmCOMPUTE_DIM_Y_BASE_IDX 0 2163#define mmCOMPUTE_DIM_Z 0x0e03 2164#define mmCOMPUTE_DIM_Z_BASE_IDX 0 2165#define mmCOMPUTE_START_X 0x0e04 2166#define mmCOMPUTE_START_X_BASE_IDX 0 2167#define mmCOMPUTE_START_Y 0x0e05 2168#define mmCOMPUTE_START_Y_BASE_IDX 0 2169#define mmCOMPUTE_START_Z 0x0e06 2170#define mmCOMPUTE_START_Z_BASE_IDX 0 2171#define mmCOMPUTE_NUM_THREAD_X 0x0e07 2172#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 2173#define mmCOMPUTE_NUM_THREAD_Y 0x0e08 2174#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 2175#define mmCOMPUTE_NUM_THREAD_Z 0x0e09 2176#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 2177#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a 2178#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 2179#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b 2180#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 2181#define mmCOMPUTE_PGM_LO 0x0e0c 2182#define mmCOMPUTE_PGM_LO_BASE_IDX 0 2183#define mmCOMPUTE_PGM_HI 0x0e0d 2184#define mmCOMPUTE_PGM_HI_BASE_IDX 0 2185#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e 2186#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 2187#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f 2188#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 2189#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 2190#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 2191#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 2192#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 2193#define mmCOMPUTE_PGM_RSRC1 0x0e12 2194#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 2195#define mmCOMPUTE_PGM_RSRC2 0x0e13 2196#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 2197#define mmCOMPUTE_VMID 0x0e14 2198#define mmCOMPUTE_VMID_BASE_IDX 0 2199#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15 2200#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 2201#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 2202#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 2203#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 2204#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 2205#define mmCOMPUTE_TMPRING_SIZE 0x0e18 2206#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 2207#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 2208#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 2209#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a 2210#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 2211#define mmCOMPUTE_RESTART_X 0x0e1b 2212#define mmCOMPUTE_RESTART_X_BASE_IDX 0 2213#define mmCOMPUTE_RESTART_Y 0x0e1c 2214#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 2215#define mmCOMPUTE_RESTART_Z 0x0e1d 2216#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 2217#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e 2218#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 2219#define mmCOMPUTE_MISC_RESERVED 0x0e1f 2220#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 2221#define mmCOMPUTE_DISPATCH_ID 0x0e20 2222#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 2223#define mmCOMPUTE_THREADGROUP_ID 0x0e21 2224#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 2225#define mmCOMPUTE_RELAUNCH 0x0e22 2226#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 2227#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 2228#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 2229#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 2230#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 2231#define mmCOMPUTE_USER_DATA_0 0x0e40 2232#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 2233#define mmCOMPUTE_USER_DATA_1 0x0e41 2234#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 2235#define mmCOMPUTE_USER_DATA_2 0x0e42 2236#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 2237#define mmCOMPUTE_USER_DATA_3 0x0e43 2238#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 2239#define mmCOMPUTE_USER_DATA_4 0x0e44 2240#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 2241#define mmCOMPUTE_USER_DATA_5 0x0e45 2242#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 2243#define mmCOMPUTE_USER_DATA_6 0x0e46 2244#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 2245#define mmCOMPUTE_USER_DATA_7 0x0e47 2246#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 2247#define mmCOMPUTE_USER_DATA_8 0x0e48 2248#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 2249#define mmCOMPUTE_USER_DATA_9 0x0e49 2250#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 2251#define mmCOMPUTE_USER_DATA_10 0x0e4a 2252#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 2253#define mmCOMPUTE_USER_DATA_11 0x0e4b 2254#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 2255#define mmCOMPUTE_USER_DATA_12 0x0e4c 2256#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 2257#define mmCOMPUTE_USER_DATA_13 0x0e4d 2258#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 2259#define mmCOMPUTE_USER_DATA_14 0x0e4e 2260#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 2261#define mmCOMPUTE_USER_DATA_15 0x0e4f 2262#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 2263#define mmCOMPUTE_NOWHERE 0x0e7f 2264#define mmCOMPUTE_NOWHERE_BASE_IDX 0 2265 2266 2267// addressBlock: gc_cppdec 2268// base address: 0xc080 2269#define mmCP_DFY_CNTL 0x1020 2270#define mmCP_DFY_CNTL_BASE_IDX 0 2271#define mmCP_DFY_STAT 0x1021 2272#define mmCP_DFY_STAT_BASE_IDX 0 2273#define mmCP_DFY_ADDR_HI 0x1022 2274#define mmCP_DFY_ADDR_HI_BASE_IDX 0 2275#define mmCP_DFY_ADDR_LO 0x1023 2276#define mmCP_DFY_ADDR_LO_BASE_IDX 0 2277#define mmCP_DFY_DATA_0 0x1024 2278#define mmCP_DFY_DATA_0_BASE_IDX 0 2279#define mmCP_DFY_DATA_1 0x1025 2280#define mmCP_DFY_DATA_1_BASE_IDX 0 2281#define mmCP_DFY_DATA_2 0x1026 2282#define mmCP_DFY_DATA_2_BASE_IDX 0 2283#define mmCP_DFY_DATA_3 0x1027 2284#define mmCP_DFY_DATA_3_BASE_IDX 0 2285#define mmCP_DFY_DATA_4 0x1028 2286#define mmCP_DFY_DATA_4_BASE_IDX 0 2287#define mmCP_DFY_DATA_5 0x1029 2288#define mmCP_DFY_DATA_5_BASE_IDX 0 2289#define mmCP_DFY_DATA_6 0x102a 2290#define mmCP_DFY_DATA_6_BASE_IDX 0 2291#define mmCP_DFY_DATA_7 0x102b 2292#define mmCP_DFY_DATA_7_BASE_IDX 0 2293#define mmCP_DFY_DATA_8 0x102c 2294#define mmCP_DFY_DATA_8_BASE_IDX 0 2295#define mmCP_DFY_DATA_9 0x102d 2296#define mmCP_DFY_DATA_9_BASE_IDX 0 2297#define mmCP_DFY_DATA_10 0x102e 2298#define mmCP_DFY_DATA_10_BASE_IDX 0 2299#define mmCP_DFY_DATA_11 0x102f 2300#define mmCP_DFY_DATA_11_BASE_IDX 0 2301#define mmCP_DFY_DATA_12 0x1030 2302#define mmCP_DFY_DATA_12_BASE_IDX 0 2303#define mmCP_DFY_DATA_13 0x1031 2304#define mmCP_DFY_DATA_13_BASE_IDX 0 2305#define mmCP_DFY_DATA_14 0x1032 2306#define mmCP_DFY_DATA_14_BASE_IDX 0 2307#define mmCP_DFY_DATA_15 0x1033 2308#define mmCP_DFY_DATA_15_BASE_IDX 0 2309#define mmCP_DFY_CMD 0x1034 2310#define mmCP_DFY_CMD_BASE_IDX 0 2311#define mmCP_EOPQ_WAIT_TIME 0x1035 2312#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 2313#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036 2314#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 2315#define mmCPC_INT_INFO 0x1037 2316#define mmCPC_INT_INFO_BASE_IDX 0 2317#define mmCP_VIRT_STATUS 0x1038 2318#define mmCP_VIRT_STATUS_BASE_IDX 0 2319#define mmCPC_INT_ADDR 0x1039 2320#define mmCPC_INT_ADDR_BASE_IDX 0 2321#define mmCPC_INT_PASID 0x103a 2322#define mmCPC_INT_PASID_BASE_IDX 0 2323#define mmCP_GFX_ERROR 0x103b 2324#define mmCP_GFX_ERROR_BASE_IDX 0 2325#define mmCPG_UTCL1_CNTL 0x103c 2326#define mmCPG_UTCL1_CNTL_BASE_IDX 0 2327#define mmCPC_UTCL1_CNTL 0x103d 2328#define mmCPC_UTCL1_CNTL_BASE_IDX 0 2329#define mmCPF_UTCL1_CNTL 0x103e 2330#define mmCPF_UTCL1_CNTL_BASE_IDX 0 2331#define mmCP_AQL_SMM_STATUS 0x103f 2332#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 2333#define mmCP_RB0_BASE 0x1040 2334#define mmCP_RB0_BASE_BASE_IDX 0 2335#define mmCP_RB_BASE 0x1040 2336#define mmCP_RB_BASE_BASE_IDX 0 2337#define mmCP_RB0_CNTL 0x1041 2338#define mmCP_RB0_CNTL_BASE_IDX 0 2339#define mmCP_RB_CNTL 0x1041 2340#define mmCP_RB_CNTL_BASE_IDX 0 2341#define mmCP_RB_RPTR_WR 0x1042 2342#define mmCP_RB_RPTR_WR_BASE_IDX 0 2343#define mmCP_RB0_RPTR_ADDR 0x1043 2344#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 2345#define mmCP_RB_RPTR_ADDR 0x1043 2346#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 2347#define mmCP_RB0_RPTR_ADDR_HI 0x1044 2348#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 2349#define mmCP_RB_RPTR_ADDR_HI 0x1044 2350#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 2351#define mmCP_RB0_BUFSZ_MASK 0x1045 2352#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 2353#define mmCP_RB_BUFSZ_MASK 0x1045 2354#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 2355#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 2356#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 2357#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 2358#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 2359#define mmGC_PRIV_MODE 0x1048 2360#define mmGC_PRIV_MODE_BASE_IDX 0 2361#define mmCP_INT_CNTL 0x1049 2362#define mmCP_INT_CNTL_BASE_IDX 0 2363#define mmCP_INT_STATUS 0x104a 2364#define mmCP_INT_STATUS_BASE_IDX 0 2365#define mmCP_DEVICE_ID 0x104b 2366#define mmCP_DEVICE_ID_BASE_IDX 0 2367#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c 2368#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 2369#define mmCP_RING_PRIORITY_CNTS 0x104c 2370#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 2371#define mmCP_ME0_PIPE0_PRIORITY 0x104d 2372#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 2373#define mmCP_RING0_PRIORITY 0x104d 2374#define mmCP_RING0_PRIORITY_BASE_IDX 0 2375#define mmCP_ME0_PIPE1_PRIORITY 0x104e 2376#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 2377#define mmCP_RING1_PRIORITY 0x104e 2378#define mmCP_RING1_PRIORITY_BASE_IDX 0 2379#define mmCP_ME0_PIPE2_PRIORITY 0x104f 2380#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 2381#define mmCP_RING2_PRIORITY 0x104f 2382#define mmCP_RING2_PRIORITY_BASE_IDX 0 2383#define mmCP_FATAL_ERROR 0x1050 2384#define mmCP_FATAL_ERROR_BASE_IDX 0 2385#define mmCP_RB_VMID 0x1051 2386#define mmCP_RB_VMID_BASE_IDX 0 2387#define mmCP_ME0_PIPE0_VMID 0x1052 2388#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 2389#define mmCP_ME0_PIPE1_VMID 0x1053 2390#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 2391#define mmCP_RB0_WPTR 0x1054 2392#define mmCP_RB0_WPTR_BASE_IDX 0 2393#define mmCP_RB_WPTR 0x1054 2394#define mmCP_RB_WPTR_BASE_IDX 0 2395#define mmCP_RB0_WPTR_HI 0x1055 2396#define mmCP_RB0_WPTR_HI_BASE_IDX 0 2397#define mmCP_RB_WPTR_HI 0x1055 2398#define mmCP_RB_WPTR_HI_BASE_IDX 0 2399#define mmCP_RB1_WPTR 0x1056 2400#define mmCP_RB1_WPTR_BASE_IDX 0 2401#define mmCP_RB1_WPTR_HI 0x1057 2402#define mmCP_RB1_WPTR_HI_BASE_IDX 0 2403#define mmCP_RB2_WPTR 0x1058 2404#define mmCP_RB2_WPTR_BASE_IDX 0 2405#define mmCP_RB_DOORBELL_CONTROL 0x1059 2406#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 2407#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a 2408#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 2409#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b 2410#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 2411#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c 2412#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 2413#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d 2414#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 2415#define mmCPG_UTCL1_ERROR 0x105e 2416#define mmCPG_UTCL1_ERROR_BASE_IDX 0 2417#define mmCPC_UTCL1_ERROR 0x105f 2418#define mmCPC_UTCL1_ERROR_BASE_IDX 0 2419#define mmCP_RB1_BASE 0x1060 2420#define mmCP_RB1_BASE_BASE_IDX 0 2421#define mmCP_RB1_CNTL 0x1061 2422#define mmCP_RB1_CNTL_BASE_IDX 0 2423#define mmCP_RB1_RPTR_ADDR 0x1062 2424#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 2425#define mmCP_RB1_RPTR_ADDR_HI 0x1063 2426#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 2427#define mmCP_RB2_BASE 0x1065 2428#define mmCP_RB2_BASE_BASE_IDX 0 2429#define mmCP_RB2_CNTL 0x1066 2430#define mmCP_RB2_CNTL_BASE_IDX 0 2431#define mmCP_RB2_RPTR_ADDR 0x1067 2432#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 2433#define mmCP_RB2_RPTR_ADDR_HI 0x1068 2434#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 2435#define mmCP_RB0_ACTIVE 0x1069 2436#define mmCP_RB0_ACTIVE_BASE_IDX 0 2437#define mmCP_RB_ACTIVE 0x1069 2438#define mmCP_RB_ACTIVE_BASE_IDX 0 2439#define mmCP_INT_CNTL_RING0 0x106a 2440#define mmCP_INT_CNTL_RING0_BASE_IDX 0 2441#define mmCP_INT_CNTL_RING1 0x106b 2442#define mmCP_INT_CNTL_RING1_BASE_IDX 0 2443#define mmCP_INT_CNTL_RING2 0x106c 2444#define mmCP_INT_CNTL_RING2_BASE_IDX 0 2445#define mmCP_INT_STATUS_RING0 0x106d 2446#define mmCP_INT_STATUS_RING0_BASE_IDX 0 2447#define mmCP_INT_STATUS_RING1 0x106e 2448#define mmCP_INT_STATUS_RING1_BASE_IDX 0 2449#define mmCP_INT_STATUS_RING2 0x106f 2450#define mmCP_INT_STATUS_RING2_BASE_IDX 0 2451#define mmCP_PWR_CNTL 0x1078 2452#define mmCP_PWR_CNTL_BASE_IDX 0 2453#define mmCP_MEM_SLP_CNTL 0x1079 2454#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 2455#define mmCP_ECC_FIRSTOCCURRENCE 0x107a 2456#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 2457#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b 2458#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 2459#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c 2460#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 2461#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d 2462#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 2463#define mmGB_EDC_MODE 0x107e 2464#define mmGB_EDC_MODE_BASE_IDX 0 2465#define mmCP_DEBUG 0x107f 2466#define mmCP_DEBUG_BASE_IDX 0 2467#define mmCP_CPF_DEBUG 0x1080 2468#define mmCP_PQ_WPTR_POLL_CNTL 0x1083 2469#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 2470#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084 2471#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 2472#define mmCP_ME1_PIPE0_INT_CNTL 0x1085 2473#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 2474#define mmCP_ME1_PIPE1_INT_CNTL 0x1086 2475#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 2476#define mmCP_ME1_PIPE2_INT_CNTL 0x1087 2477#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 2478#define mmCP_ME1_PIPE3_INT_CNTL 0x1088 2479#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 2480#define mmCP_ME2_PIPE0_INT_CNTL 0x1089 2481#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 2482#define mmCP_ME2_PIPE1_INT_CNTL 0x108a 2483#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 2484#define mmCP_ME2_PIPE2_INT_CNTL 0x108b 2485#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 2486#define mmCP_ME2_PIPE3_INT_CNTL 0x108c 2487#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 2488#define mmCP_ME1_PIPE0_INT_STATUS 0x108d 2489#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 2490#define mmCP_ME1_PIPE1_INT_STATUS 0x108e 2491#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 2492#define mmCP_ME1_PIPE2_INT_STATUS 0x108f 2493#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 2494#define mmCP_ME1_PIPE3_INT_STATUS 0x1090 2495#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 2496#define mmCP_ME2_PIPE0_INT_STATUS 0x1091 2497#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 2498#define mmCP_ME2_PIPE1_INT_STATUS 0x1092 2499#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 2500#define mmCP_ME2_PIPE2_INT_STATUS 0x1093 2501#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 2502#define mmCP_ME2_PIPE3_INT_STATUS 0x1094 2503#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 2504#define mmCP_ME1_INT_STAT_DEBUG 0x1095 2505#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 2506#define mmCP_ME2_INT_STAT_DEBUG 0x1096 2507#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX 0 2508#define mmCC_GC_EDC_CONFIG 0x1098 2509#define mmCC_GC_EDC_CONFIG_BASE_IDX 0 2510#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099 2511#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 2512#define mmCP_ME1_PIPE0_PRIORITY 0x109a 2513#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 2514#define mmCP_ME1_PIPE1_PRIORITY 0x109b 2515#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 2516#define mmCP_ME1_PIPE2_PRIORITY 0x109c 2517#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 2518#define mmCP_ME1_PIPE3_PRIORITY 0x109d 2519#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 2520#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e 2521#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 2522#define mmCP_ME2_PIPE0_PRIORITY 0x109f 2523#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 2524#define mmCP_ME2_PIPE1_PRIORITY 0x10a0 2525#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 2526#define mmCP_ME2_PIPE2_PRIORITY 0x10a1 2527#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 2528#define mmCP_ME2_PIPE3_PRIORITY 0x10a2 2529#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 2530#define mmCP_CE_PRGRM_CNTR_START 0x10a3 2531#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 2532#define mmCP_PFP_PRGRM_CNTR_START 0x10a4 2533#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 2534#define mmCP_ME_PRGRM_CNTR_START 0x10a5 2535#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 2536#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6 2537#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 2538#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7 2539#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 2540#define mmCP_CE_INTR_ROUTINE_START 0x10a8 2541#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 2542#define mmCP_PFP_INTR_ROUTINE_START 0x10a9 2543#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 2544#define mmCP_ME_INTR_ROUTINE_START 0x10aa 2545#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 2546#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab 2547#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 2548#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac 2549#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 2550#define mmCP_CONTEXT_CNTL 0x10ad 2551#define mmCP_CONTEXT_CNTL_BASE_IDX 0 2552#define mmCP_MAX_CONTEXT 0x10ae 2553#define mmCP_MAX_CONTEXT_BASE_IDX 0 2554#define mmCP_IQ_WAIT_TIME1 0x10af 2555#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 2556#define mmCP_IQ_WAIT_TIME2 0x10b0 2557#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 2558#define mmCP_RB0_BASE_HI 0x10b1 2559#define mmCP_RB0_BASE_HI_BASE_IDX 0 2560#define mmCP_RB1_BASE_HI 0x10b2 2561#define mmCP_RB1_BASE_HI_BASE_IDX 0 2562#define mmCP_VMID_RESET 0x10b3 2563#define mmCP_VMID_RESET_BASE_IDX 0 2564#define mmCPC_INT_CNTL 0x10b4 2565#define mmCPC_INT_CNTL_BASE_IDX 0 2566#define mmCPC_INT_STATUS 0x10b5 2567#define mmCPC_INT_STATUS_BASE_IDX 0 2568#define mmCP_VMID_PREEMPT 0x10b6 2569#define mmCP_VMID_PREEMPT_BASE_IDX 0 2570#define mmCPC_INT_CNTX_ID 0x10b7 2571#define mmCPC_INT_CNTX_ID_BASE_IDX 0 2572#define mmCP_PQ_STATUS 0x10b8 2573#define mmCP_PQ_STATUS_BASE_IDX 0 2574#define mmCP_CPC_IC_BASE_LO 0x10b9 2575#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0 2576#define mmCP_CPC_IC_BASE_HI 0x10ba 2577#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0 2578#define mmCP_CPC_IC_BASE_CNTL 0x10bb 2579#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0 2580#define mmCP_CPC_IC_OP_CNTL 0x10bc 2581#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0 2582#define mmCP_MEC1_F32_INT_DIS 0x10bd 2583#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 2584#define mmCP_MEC2_F32_INT_DIS 0x10be 2585#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 2586#define mmCP_VMID_STATUS 0x10bf 2587#define mmCP_VMID_STATUS_BASE_IDX 0 2588 2589 2590// addressBlock: gc_cppdec2 2591// base address: 0xc600 2592#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 2593#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 2594#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 2595#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 2596#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 2597#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 2598#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 2599#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 2600#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 2601#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 2602#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 2603#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 2604#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 2605#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 2606#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 2607#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 2608#define mmCP_RB_DOORBELL_CLEAR 0x1188 2609#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 2610#define mmCPF_EDC_TAG_CNT 0x1189 2611#define mmCPF_EDC_TAG_CNT_BASE_IDX 0 2612#define mmCPF_EDC_ROQ_CNT 0x118a 2613#define mmCPF_EDC_ROQ_CNT_BASE_IDX 0 2614#define mmCPG_EDC_TAG_CNT 0x118b 2615#define mmCPG_EDC_TAG_CNT_BASE_IDX 0 2616#define mmCPG_EDC_DMA_CNT 0x118d 2617#define mmCPG_EDC_DMA_CNT_BASE_IDX 0 2618#define mmCPC_EDC_SCRATCH_CNT 0x118e 2619#define mmCPC_EDC_SCRATCH_CNT_BASE_IDX 0 2620#define mmCPC_EDC_UCODE_CNT 0x118f 2621#define mmCPC_EDC_UCODE_CNT_BASE_IDX 0 2622#define mmDC_EDC_STATE_CNT 0x1191 2623#define mmDC_EDC_STATE_CNT_BASE_IDX 0 2624#define mmDC_EDC_CSINVOC_CNT 0x1192 2625#define mmDC_EDC_CSINVOC_CNT_BASE_IDX 0 2626#define mmDC_EDC_RESTORE_CNT 0x1193 2627#define mmDC_EDC_RESTORE_CNT_BASE_IDX 0 2628#define mmCP_GFX_MQD_CONTROL 0x11a0 2629#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 2630#define mmCP_GFX_MQD_BASE_ADDR 0x11a1 2631#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 2632#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2 2633#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 2634#define mmCP_RB_STATUS 0x11a3 2635#define mmCP_RB_STATUS_BASE_IDX 0 2636#define mmCPG_UTCL1_STATUS 0x11b4 2637#define mmCPG_UTCL1_STATUS_BASE_IDX 0 2638#define mmCPC_UTCL1_STATUS 0x11b5 2639#define mmCPC_UTCL1_STATUS_BASE_IDX 0 2640#define mmCPF_UTCL1_STATUS 0x11b6 2641#define mmCPF_UTCL1_STATUS_BASE_IDX 0 2642#define mmCP_SD_CNTL 0x11b7 2643#define mmCP_SD_CNTL_BASE_IDX 0 2644#define mmCP_SOFT_RESET_CNTL 0x11b9 2645#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 2646#define mmCP_CPC_GFX_CNTL 0x11ba 2647#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 2648 2649 2650// addressBlock: gc_spipdec 2651// base address: 0xc700 2652#define mmSPI_ARB_PRIORITY 0x11c0 2653#define mmSPI_ARB_PRIORITY_BASE_IDX 0 2654#define mmSPI_ARB_CYCLES_0 0x11c1 2655#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 2656#define mmSPI_ARB_CYCLES_1 0x11c2 2657#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 2658#define mmSPI_CDBG_SYS_GFX 0x11c3 2659#define mmSPI_CDBG_SYS_GFX_BASE_IDX 0 2660#define mmSPI_CDBG_SYS_HP3D 0x11c4 2661#define mmSPI_CDBG_SYS_HP3D_BASE_IDX 0 2662#define mmSPI_CDBG_SYS_CS0 0x11c5 2663#define mmSPI_CDBG_SYS_CS0_BASE_IDX 0 2664#define mmSPI_CDBG_SYS_CS1 0x11c6 2665#define mmSPI_CDBG_SYS_CS1_BASE_IDX 0 2666#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7 2667#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 2668#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 2669#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 2670#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9 2671#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 2672#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca 2673#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 2674#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb 2675#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 2676#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc 2677#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 2678#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd 2679#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 2680#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce 2681#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 2682#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf 2683#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 2684#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0 2685#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 2686#define mmSPI_GDBG_WAVE_CNTL 0x11d1 2687#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 2688#define mmSPI_GDBG_TRAP_CONFIG 0x11d2 2689#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 2690#define mmSPI_GDBG_TRAP_MASK 0x11d3 2691#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 2692#define mmSPI_GDBG_WAVE_CNTL2 0x11d4 2693#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 2694#define mmSPI_GDBG_WAVE_CNTL3 0x11d5 2695#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 2696#define mmSPI_GDBG_TRAP_DATA0 0x11d8 2697#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 2698#define mmSPI_GDBG_TRAP_DATA1 0x11d9 2699#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 2700#define mmSPI_RESET_DEBUG 0x11da 2701#define mmSPI_RESET_DEBUG_BASE_IDX 0 2702#define mmSPI_COMPUTE_QUEUE_RESET 0x11db 2703#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 2704#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc 2705#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 2706#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd 2707#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 2708#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de 2709#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 2710#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df 2711#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 2712#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0 2713#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 2714#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1 2715#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 2716#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2 2717#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 2718#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3 2719#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 2720#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4 2721#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 2722#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5 2723#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 2724#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 2725#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 2726#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 2727#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 2728#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 2729#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 2730#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 2731#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 2732#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea 2733#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 2734#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb 2735#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 2736#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec 2737#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 2738#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed 2739#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 2740#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee 2741#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 2742#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef 2743#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 2744#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0 2745#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 2746#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1 2747#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 2748#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 2749#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 2750#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 2751#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 2752#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4 2753#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 2754#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5 2755#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 2756#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6 2757#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 2758#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7 2759#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 2760#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 2761#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 2762#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 2763#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 2764#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa 2765#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 2766#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb 2767#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 2768#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc 2769#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 2770#define mmSPI_ARB_CNTL_0 0x11fd 2771#define mmSPI_ARB_CNTL_0_BASE_IDX 0 2772 2773 2774// addressBlock: gc_cpphqddec 2775// base address: 0xc800 2776#define mmCP_HQD_GFX_CONTROL 0x123e 2777#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 2778#define mmCP_HQD_GFX_STATUS 0x123f 2779#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 2780#define mmCP_HPD_ROQ_OFFSETS 0x1240 2781#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 2782#define mmCP_HPD_STATUS0 0x1241 2783#define mmCP_HPD_STATUS0_BASE_IDX 0 2784#define mmCP_HPD_UTCL1_CNTL 0x1242 2785#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 2786#define mmCP_HPD_UTCL1_ERROR 0x1243 2787#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 2788#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244 2789#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 2790#define mmCP_MQD_BASE_ADDR 0x1245 2791#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 2792#define mmCP_MQD_BASE_ADDR_HI 0x1246 2793#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 2794#define mmCP_HQD_ACTIVE 0x1247 2795#define mmCP_HQD_ACTIVE_BASE_IDX 0 2796#define mmCP_HQD_VMID 0x1248 2797#define mmCP_HQD_VMID_BASE_IDX 0 2798#define mmCP_HQD_PERSISTENT_STATE 0x1249 2799#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 2800#define mmCP_HQD_PIPE_PRIORITY 0x124a 2801#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 2802#define mmCP_HQD_QUEUE_PRIORITY 0x124b 2803#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 2804#define mmCP_HQD_QUANTUM 0x124c 2805#define mmCP_HQD_QUANTUM_BASE_IDX 0 2806#define mmCP_HQD_PQ_BASE 0x124d 2807#define mmCP_HQD_PQ_BASE_BASE_IDX 0 2808#define mmCP_HQD_PQ_BASE_HI 0x124e 2809#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 2810#define mmCP_HQD_PQ_RPTR 0x124f 2811#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 2812#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 2813#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 2814#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 2815#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 2816#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 2817#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 2818#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 2819#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 2820#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 2821#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 2822#define mmCP_HQD_PQ_CONTROL 0x1256 2823#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 2824#define mmCP_HQD_IB_BASE_ADDR 0x1257 2825#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 2826#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258 2827#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 2828#define mmCP_HQD_IB_RPTR 0x1259 2829#define mmCP_HQD_IB_RPTR_BASE_IDX 0 2830#define mmCP_HQD_IB_CONTROL 0x125a 2831#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 2832#define mmCP_HQD_IQ_TIMER 0x125b 2833#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 2834#define mmCP_HQD_IQ_RPTR 0x125c 2835#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 2836#define mmCP_HQD_DEQUEUE_REQUEST 0x125d 2837#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 2838#define mmCP_HQD_DMA_OFFLOAD 0x125e 2839#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 2840#define mmCP_HQD_OFFLOAD 0x125e 2841#define mmCP_HQD_OFFLOAD_BASE_IDX 0 2842#define mmCP_HQD_SEMA_CMD 0x125f 2843#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 2844#define mmCP_HQD_MSG_TYPE 0x1260 2845#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 2846#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261 2847#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 2848#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262 2849#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 2850#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263 2851#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 2852#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264 2853#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 2854#define mmCP_HQD_HQ_SCHEDULER0 0x1265 2855#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 2856#define mmCP_HQD_HQ_STATUS0 0x1265 2857#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 2858#define mmCP_HQD_HQ_CONTROL0 0x1266 2859#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 2860#define mmCP_HQD_HQ_SCHEDULER1 0x1266 2861#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 2862#define mmCP_MQD_CONTROL 0x1267 2863#define mmCP_MQD_CONTROL_BASE_IDX 0 2864#define mmCP_HQD_HQ_STATUS1 0x1268 2865#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 2866#define mmCP_HQD_HQ_CONTROL1 0x1269 2867#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 2868#define mmCP_HQD_EOP_BASE_ADDR 0x126a 2869#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 2870#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b 2871#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 2872#define mmCP_HQD_EOP_CONTROL 0x126c 2873#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 2874#define mmCP_HQD_EOP_RPTR 0x126d 2875#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 2876#define mmCP_HQD_EOP_WPTR 0x126e 2877#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 2878#define mmCP_HQD_EOP_EVENTS 0x126f 2879#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 2880#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 2881#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 2882#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 2883#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 2884#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272 2885#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 2886#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273 2887#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 2888#define mmCP_HQD_CNTL_STACK_SIZE 0x1274 2889#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 2890#define mmCP_HQD_WG_STATE_OFFSET 0x1275 2891#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 2892#define mmCP_HQD_CTX_SAVE_SIZE 0x1276 2893#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 2894#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277 2895#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 2896#define mmCP_HQD_ERROR 0x1278 2897#define mmCP_HQD_ERROR_BASE_IDX 0 2898#define mmCP_HQD_EOP_WPTR_MEM 0x1279 2899#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 2900#define mmCP_HQD_AQL_CONTROL 0x127a 2901#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 2902#define mmCP_HQD_PQ_WPTR_LO 0x127b 2903#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 2904#define mmCP_HQD_PQ_WPTR_HI 0x127c 2905#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 2906 2907 2908// addressBlock: gc_didtdec 2909// base address: 0xca00 2910#define mmDIDT_IND_INDEX 0x1280 2911#define mmDIDT_IND_INDEX_BASE_IDX 0 2912#define mmDIDT_IND_DATA 0x1281 2913#define mmDIDT_IND_DATA_BASE_IDX 0 2914 2915 2916// addressBlock: gc_gccacdec 2917// base address: 0xca10 2918#define mmGC_CAC_CTRL_1 0x1284 2919#define mmGC_CAC_CTRL_1_BASE_IDX 0 2920#define mmGC_CAC_CTRL_2 0x1285 2921#define mmGC_CAC_CTRL_2_BASE_IDX 0 2922#define mmGC_CAC_CGTT_CLK_CTRL 0x1286 2923#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0 2924#define mmGC_CAC_AGGR_LOWER 0x1287 2925#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 2926#define mmGC_CAC_AGGR_UPPER 0x1288 2927#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 2928#define mmGC_CAC_SOFT_CTRL 0x128d 2929#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 2930#define mmGC_DIDT_CTRL0 0x128e 2931#define mmGC_DIDT_CTRL0_BASE_IDX 0 2932#define mmGC_DIDT_CTRL1 0x128f 2933#define mmGC_DIDT_CTRL1_BASE_IDX 0 2934#define mmGC_DIDT_CTRL2 0x1290 2935#define mmGC_DIDT_CTRL2_BASE_IDX 0 2936#define mmGC_DIDT_WEIGHT 0x1291 2937#define mmGC_DIDT_WEIGHT_BASE_IDX 0 2938#define mmGC_DIDT_WEIGHT_1 0x1292 2939#define mmGC_DIDT_WEIGHT_1_BASE_IDX 0 2940#define mmGC_EDC_CTRL 0x1293 2941#define mmGC_EDC_CTRL_BASE_IDX 0 2942#define mmGC_EDC_THRESHOLD 0x1294 2943#define mmGC_EDC_THRESHOLD_BASE_IDX 0 2944#define mmGC_EDC_STATUS 0x1295 2945#define mmGC_EDC_STATUS_BASE_IDX 0 2946#define mmGC_EDC_OVERFLOW 0x1296 2947#define mmGC_EDC_OVERFLOW_BASE_IDX 0 2948#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297 2949#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 2950#define mmGC_DIDT_DROOP_CTRL 0x1298 2951#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0 2952#define mmGC_EDC_DROOP_CTRL 0x1299 2953#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0 2954#define mmGC_CAC_IND_INDEX 0x129a 2955#define mmGC_CAC_IND_INDEX_BASE_IDX 0 2956#define mmGC_CAC_IND_DATA 0x129b 2957#define mmGC_CAC_IND_DATA_BASE_IDX 0 2958#define mmSE_CAC_CGTT_CLK_CTRL 0x129c 2959#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0 2960#define mmSE_CAC_IND_INDEX 0x129d 2961#define mmSE_CAC_IND_INDEX_BASE_IDX 0 2962#define mmSE_CAC_IND_DATA 0x129e 2963#define mmSE_CAC_IND_DATA_BASE_IDX 0 2964 2965 2966// addressBlock: gc_tcpdec 2967// base address: 0xca80 2968#define mmTCP_WATCH0_ADDR_H 0x12a0 2969#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 2970#define mmTCP_WATCH0_ADDR_L 0x12a1 2971#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 2972#define mmTCP_WATCH0_CNTL 0x12a2 2973#define mmTCP_WATCH0_CNTL_BASE_IDX 0 2974#define mmTCP_WATCH1_ADDR_H 0x12a3 2975#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 2976#define mmTCP_WATCH1_ADDR_L 0x12a4 2977#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 2978#define mmTCP_WATCH1_CNTL 0x12a5 2979#define mmTCP_WATCH1_CNTL_BASE_IDX 0 2980#define mmTCP_WATCH2_ADDR_H 0x12a6 2981#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 2982#define mmTCP_WATCH2_ADDR_L 0x12a7 2983#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 2984#define mmTCP_WATCH2_CNTL 0x12a8 2985#define mmTCP_WATCH2_CNTL_BASE_IDX 0 2986#define mmTCP_WATCH3_ADDR_H 0x12a9 2987#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 2988#define mmTCP_WATCH3_ADDR_L 0x12aa 2989#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 2990#define mmTCP_WATCH3_CNTL 0x12ab 2991#define mmTCP_WATCH3_CNTL_BASE_IDX 0 2992#define mmTCP_GATCL1_CNTL 0x12b0 2993#define mmTCP_GATCL1_CNTL_BASE_IDX 0 2994#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1 2995#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 2996#define mmTCP_GATCL1_DSM_CNTL 0x12b2 2997#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0 2998#define mmTCP_CNTL2 0x12b4 2999#define mmTCP_CNTL2_BASE_IDX 0 3000#define mmTCP_UTCL1_CNTL1 0x12b5
3001#define mmTCP_UTCL1_CNTL1_BASE_IDX 0 3002#define mmTCP_UTCL1_CNTL2 0x12b6 3003#define mmTCP_UTCL1_CNTL2_BASE_IDX 0 3004#define mmTCP_UTCL1_STATUS 0x12b7 3005#define mmTCP_UTCL1_STATUS_BASE_IDX 0 3006#define mmTCP_PERFCOUNTER_FILTER 0x12b9 3007#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 3008#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba 3009#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 3010 3011 3012// addressBlock: gc_gdspdec 3013// base address: 0xcc00 3014#define mmGDS_VMID0_BASE 0x1300 3015#define mmGDS_VMID0_BASE_BASE_IDX 0 3016#define mmGDS_VMID0_SIZE 0x1301 3017#define mmGDS_VMID0_SIZE_BASE_IDX 0 3018#define mmGDS_VMID1_BASE 0x1302 3019#define mmGDS_VMID1_BASE_BASE_IDX 0 3020#define mmGDS_VMID1_SIZE 0x1303 3021#define mmGDS_VMID1_SIZE_BASE_IDX 0 3022#define mmGDS_VMID2_BASE 0x1304 3023#define mmGDS_VMID2_BASE_BASE_IDX 0 3024#define mmGDS_VMID2_SIZE 0x1305 3025#define mmGDS_VMID2_SIZE_BASE_IDX 0 3026#define mmGDS_VMID3_BASE 0x1306 3027#define mmGDS_VMID3_BASE_BASE_IDX 0 3028#define mmGDS_VMID3_SIZE 0x1307 3029#define mmGDS_VMID3_SIZE_BASE_IDX 0 3030#define mmGDS_VMID4_BASE 0x1308 3031#define mmGDS_VMID4_BASE_BASE_IDX 0 3032#define mmGDS_VMID4_SIZE 0x1309 3033#define mmGDS_VMID4_SIZE_BASE_IDX 0 3034#define mmGDS_VMID5_BASE 0x130a 3035#define mmGDS_VMID5_BASE_BASE_IDX 0 3036#define mmGDS_VMID5_SIZE 0x130b 3037#define mmGDS_VMID5_SIZE_BASE_IDX 0 3038#define mmGDS_VMID6_BASE 0x130c 3039#define mmGDS_VMID6_BASE_BASE_IDX 0 3040#define mmGDS_VMID6_SIZE 0x130d 3041#define mmGDS_VMID6_SIZE_BASE_IDX 0 3042#define mmGDS_VMID7_BASE 0x130e 3043#define mmGDS_VMID7_BASE_BASE_IDX 0 3044#define mmGDS_VMID7_SIZE 0x130f 3045#define mmGDS_VMID7_SIZE_BASE_IDX 0 3046#define mmGDS_VMID8_BASE 0x1310 3047#define mmGDS_VMID8_BASE_BASE_IDX 0 3048#define mmGDS_VMID8_SIZE 0x1311 3049#define mmGDS_VMID8_SIZE_BASE_IDX 0 3050#define mmGDS_VMID9_BASE 0x1312 3051#define mmGDS_VMID9_BASE_BASE_IDX 0 3052#define mmGDS_VMID9_SIZE 0x1313 3053#define mmGDS_VMID9_SIZE_BASE_IDX 0 3054#define mmGDS_VMID10_BASE 0x1314 3055#define mmGDS_VMID10_BASE_BASE_IDX 0 3056#define mmGDS_VMID10_SIZE 0x1315 3057#define mmGDS_VMID10_SIZE_BASE_IDX 0 3058#define mmGDS_VMID11_BASE 0x1316 3059#define mmGDS_VMID11_BASE_BASE_IDX 0 3060#define mmGDS_VMID11_SIZE 0x1317 3061#define mmGDS_VMID11_SIZE_BASE_IDX 0 3062#define mmGDS_VMID12_BASE 0x1318 3063#define mmGDS_VMID12_BASE_BASE_IDX 0 3064#define mmGDS_VMID12_SIZE 0x1319 3065#define mmGDS_VMID12_SIZE_BASE_IDX 0 3066#define mmGDS_VMID13_BASE 0x131a 3067#define mmGDS_VMID13_BASE_BASE_IDX 0 3068#define mmGDS_VMID13_SIZE 0x131b 3069#define mmGDS_VMID13_SIZE_BASE_IDX 0 3070#define mmGDS_VMID14_BASE 0x131c 3071#define mmGDS_VMID14_BASE_BASE_IDX 0 3072#define mmGDS_VMID14_SIZE 0x131d 3073#define mmGDS_VMID14_SIZE_BASE_IDX 0 3074#define mmGDS_VMID15_BASE 0x131e 3075#define mmGDS_VMID15_BASE_BASE_IDX 0 3076#define mmGDS_VMID15_SIZE 0x131f 3077#define mmGDS_VMID15_SIZE_BASE_IDX 0 3078#define mmGDS_GWS_VMID0 0x1320 3079#define mmGDS_GWS_VMID0_BASE_IDX 0 3080#define mmGDS_GWS_VMID1 0x1321 3081#define mmGDS_GWS_VMID1_BASE_IDX 0 3082#define mmGDS_GWS_VMID2 0x1322 3083#define mmGDS_GWS_VMID2_BASE_IDX 0 3084#define mmGDS_GWS_VMID3 0x1323 3085#define mmGDS_GWS_VMID3_BASE_IDX 0 3086#define mmGDS_GWS_VMID4 0x1324 3087#define mmGDS_GWS_VMID4_BASE_IDX 0 3088#define mmGDS_GWS_VMID5 0x1325 3089#define mmGDS_GWS_VMID5_BASE_IDX 0 3090#define mmGDS_GWS_VMID6 0x1326 3091#define mmGDS_GWS_VMID6_BASE_IDX 0 3092#define mmGDS_GWS_VMID7 0x1327 3093#define mmGDS_GWS_VMID7_BASE_IDX 0 3094#define mmGDS_GWS_VMID8 0x1328 3095#define mmGDS_GWS_VMID8_BASE_IDX 0 3096#define mmGDS_GWS_VMID9 0x1329 3097#define mmGDS_GWS_VMID9_BASE_IDX 0 3098#define mmGDS_GWS_VMID10 0x132a 3099#define mmGDS_GWS_VMID10_BASE_IDX 0 3100#define mmGDS_GWS_VMID11 0x132b 3101#define mmGDS_GWS_VMID11_BASE_IDX 0 3102#define mmGDS_GWS_VMID12 0x132c 3103#define mmGDS_GWS_VMID12_BASE_IDX 0 3104#define mmGDS_GWS_VMID13 0x132d 3105#define mmGDS_GWS_VMID13_BASE_IDX 0 3106#define mmGDS_GWS_VMID14 0x132e 3107#define mmGDS_GWS_VMID14_BASE_IDX 0 3108#define mmGDS_GWS_VMID15 0x132f 3109#define mmGDS_GWS_VMID15_BASE_IDX 0 3110#define mmGDS_OA_VMID0 0x1330 3111#define mmGDS_OA_VMID0_BASE_IDX 0 3112#define mmGDS_OA_VMID1 0x1331 3113#define mmGDS_OA_VMID1_BASE_IDX 0 3114#define mmGDS_OA_VMID2 0x1332 3115#define mmGDS_OA_VMID2_BASE_IDX 0 3116#define mmGDS_OA_VMID3 0x1333 3117#define mmGDS_OA_VMID3_BASE_IDX 0 3118#define mmGDS_OA_VMID4 0x1334 3119#define mmGDS_OA_VMID4_BASE_IDX 0 3120#define mmGDS_OA_VMID5 0x1335 3121#define mmGDS_OA_VMID5_BASE_IDX 0 3122#define mmGDS_OA_VMID6 0x1336 3123#define mmGDS_OA_VMID6_BASE_IDX 0 3124#define mmGDS_OA_VMID7 0x1337 3125#define mmGDS_OA_VMID7_BASE_IDX 0 3126#define mmGDS_OA_VMID8 0x1338 3127#define mmGDS_OA_VMID8_BASE_IDX 0 3128#define mmGDS_OA_VMID9 0x1339 3129#define mmGDS_OA_VMID9_BASE_IDX 0 3130#define mmGDS_OA_VMID10 0x133a 3131#define mmGDS_OA_VMID10_BASE_IDX 0 3132#define mmGDS_OA_VMID11 0x133b 3133#define mmGDS_OA_VMID11_BASE_IDX 0 3134#define mmGDS_OA_VMID12 0x133c 3135#define mmGDS_OA_VMID12_BASE_IDX 0 3136#define mmGDS_OA_VMID13 0x133d 3137#define mmGDS_OA_VMID13_BASE_IDX 0 3138#define mmGDS_OA_VMID14 0x133e 3139#define mmGDS_OA_VMID14_BASE_IDX 0 3140#define mmGDS_OA_VMID15 0x133f 3141#define mmGDS_OA_VMID15_BASE_IDX 0 3142#define mmGDS_GWS_RESET0 0x1344 3143#define mmGDS_GWS_RESET0_BASE_IDX 0 3144#define mmGDS_GWS_RESET1 0x1345 3145#define mmGDS_GWS_RESET1_BASE_IDX 0 3146#define mmGDS_GWS_RESOURCE_RESET 0x1346 3147#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 3148#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348 3149#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 3150#define mmGDS_OA_RESET_MASK 0x1349 3151#define mmGDS_OA_RESET_MASK_BASE_IDX 0 3152#define mmGDS_OA_RESET 0x134a 3153#define mmGDS_OA_RESET_BASE_IDX 0 3154#define mmGDS_ENHANCE 0x134b 3155#define mmGDS_ENHANCE_BASE_IDX 0 3156#define mmGDS_OA_CGPG_RESTORE 0x134c 3157#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 3158#define mmGDS_CS_CTXSW_STATUS 0x134d 3159#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 3160#define mmGDS_CS_CTXSW_CNT0 0x134e 3161#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 3162#define mmGDS_CS_CTXSW_CNT1 0x134f 3163#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 3164#define mmGDS_CS_CTXSW_CNT2 0x1350 3165#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 3166#define mmGDS_CS_CTXSW_CNT3 0x1351 3167#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 3168#define mmGDS_GFX_CTXSW_STATUS 0x1352 3169#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 3170#define mmGDS_VS_CTXSW_CNT0 0x1353 3171#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 3172#define mmGDS_VS_CTXSW_CNT1 0x1354 3173#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 3174#define mmGDS_VS_CTXSW_CNT2 0x1355 3175#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 3176#define mmGDS_VS_CTXSW_CNT3 0x1356 3177#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 3178#define mmGDS_PS0_CTXSW_CNT0 0x1357 3179#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0 3180#define mmGDS_PS0_CTXSW_CNT1 0x1358 3181#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0 3182#define mmGDS_PS0_CTXSW_CNT2 0x1359 3183#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0 3184#define mmGDS_PS0_CTXSW_CNT3 0x135a 3185#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0 3186#define mmGDS_PS1_CTXSW_CNT0 0x135b 3187#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0 3188#define mmGDS_PS1_CTXSW_CNT1 0x135c 3189#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0 3190#define mmGDS_PS1_CTXSW_CNT2 0x135d 3191#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0 3192#define mmGDS_PS1_CTXSW_CNT3 0x135e 3193#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0 3194#define mmGDS_PS2_CTXSW_CNT0 0x135f 3195#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0 3196#define mmGDS_PS2_CTXSW_CNT1 0x1360 3197#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0 3198#define mmGDS_PS2_CTXSW_CNT2 0x1361 3199#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0 3200#define mmGDS_PS2_CTXSW_CNT3 0x1362 3201#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0 3202#define mmGDS_PS3_CTXSW_CNT0 0x1363 3203#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0 3204#define mmGDS_PS3_CTXSW_CNT1 0x1364 3205#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0 3206#define mmGDS_PS3_CTXSW_CNT2 0x1365 3207#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0 3208#define mmGDS_PS3_CTXSW_CNT3 0x1366 3209#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0 3210#define mmGDS_PS4_CTXSW_CNT0 0x1367 3211#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0 3212#define mmGDS_PS4_CTXSW_CNT1 0x1368 3213#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0 3214#define mmGDS_PS4_CTXSW_CNT2 0x1369 3215#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0 3216#define mmGDS_PS4_CTXSW_CNT3 0x136a 3217#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0 3218#define mmGDS_PS5_CTXSW_CNT0 0x136b 3219#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0 3220#define mmGDS_PS5_CTXSW_CNT1 0x136c 3221#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0 3222#define mmGDS_PS5_CTXSW_CNT2 0x136d 3223#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0 3224#define mmGDS_PS5_CTXSW_CNT3 0x136e 3225#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0 3226#define mmGDS_PS6_CTXSW_CNT0 0x136f 3227#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0 3228#define mmGDS_PS6_CTXSW_CNT1 0x1370 3229#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0 3230#define mmGDS_PS6_CTXSW_CNT2 0x1371 3231#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0 3232#define mmGDS_PS6_CTXSW_CNT3 0x1372 3233#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0 3234#define mmGDS_PS7_CTXSW_CNT0 0x1373 3235#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0 3236#define mmGDS_PS7_CTXSW_CNT1 0x1374 3237#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0 3238#define mmGDS_PS7_CTXSW_CNT2 0x1375 3239#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0 3240#define mmGDS_PS7_CTXSW_CNT3 0x1376 3241#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0 3242#define mmGDS_GS_CTXSW_CNT0 0x1377 3243#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 3244#define mmGDS_GS_CTXSW_CNT1 0x1378 3245#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 3246#define mmGDS_GS_CTXSW_CNT2 0x1379 3247#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 3248#define mmGDS_GS_CTXSW_CNT3 0x137a 3249#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 3250 3251 3252// addressBlock: gc_rasdec 3253// base address: 0xce00 3254#define mmRAS_SIGNATURE_CONTROL 0x1380 3255#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0 3256#define mmRAS_SIGNATURE_MASK 0x1381 3257#define mmRAS_SIGNATURE_MASK_BASE_IDX 0 3258#define mmRAS_SX_SIGNATURE0 0x1382 3259#define mmRAS_SX_SIGNATURE0_BASE_IDX 0 3260#define mmRAS_SX_SIGNATURE1 0x1383 3261#define mmRAS_SX_SIGNATURE1_BASE_IDX 0 3262#define mmRAS_SX_SIGNATURE2 0x1384 3263#define mmRAS_SX_SIGNATURE2_BASE_IDX 0 3264#define mmRAS_SX_SIGNATURE3 0x1385 3265#define mmRAS_SX_SIGNATURE3_BASE_IDX 0 3266#define mmRAS_DB_SIGNATURE0 0x138b 3267#define mmRAS_DB_SIGNATURE0_BASE_IDX 0 3268#define mmRAS_PA_SIGNATURE0 0x138c 3269#define mmRAS_PA_SIGNATURE0_BASE_IDX 0 3270#define mmRAS_VGT_SIGNATURE0 0x138d 3271#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0 3272#define mmRAS_SQ_SIGNATURE0 0x138e 3273#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0 3274#define mmRAS_SC_SIGNATURE0 0x138f 3275#define mmRAS_SC_SIGNATURE0_BASE_IDX 0 3276#define mmRAS_SC_SIGNATURE1 0x1390 3277#define mmRAS_SC_SIGNATURE1_BASE_IDX 0 3278#define mmRAS_SC_SIGNATURE2 0x1391 3279#define mmRAS_SC_SIGNATURE2_BASE_IDX 0 3280#define mmRAS_SC_SIGNATURE3 0x1392 3281#define mmRAS_SC_SIGNATURE3_BASE_IDX 0 3282#define mmRAS_SC_SIGNATURE4 0x1393 3283#define mmRAS_SC_SIGNATURE4_BASE_IDX 0 3284#define mmRAS_SC_SIGNATURE5 0x1394 3285#define mmRAS_SC_SIGNATURE5_BASE_IDX 0 3286#define mmRAS_SC_SIGNATURE6 0x1395 3287#define mmRAS_SC_SIGNATURE6_BASE_IDX 0 3288#define mmRAS_SC_SIGNATURE7 0x1396 3289#define mmRAS_SC_SIGNATURE7_BASE_IDX 0 3290#define mmRAS_IA_SIGNATURE0 0x1397 3291#define mmRAS_IA_SIGNATURE0_BASE_IDX 0 3292#define mmRAS_IA_SIGNATURE1 0x1398 3293#define mmRAS_IA_SIGNATURE1_BASE_IDX 0 3294#define mmRAS_SPI_SIGNATURE0 0x1399 3295#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0 3296#define mmRAS_SPI_SIGNATURE1 0x139a 3297#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0 3298#define mmRAS_TA_SIGNATURE0 0x139b 3299#define mmRAS_TA_SIGNATURE0_BASE_IDX 0 3300#define mmRAS_TD_SIGNATURE0 0x139c 3301#define mmRAS_TD_SIGNATURE0_BASE_IDX 0 3302#define mmRAS_CB_SIGNATURE0 0x139d 3303#define mmRAS_CB_SIGNATURE0_BASE_IDX 0 3304#define mmRAS_BCI_SIGNATURE0 0x139e 3305#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0 3306#define mmRAS_BCI_SIGNATURE1 0x139f 3307#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0 3308#define mmRAS_TA_SIGNATURE1 0x13a0 3309#define mmRAS_TA_SIGNATURE1_BASE_IDX 0 3310 3311 3312// addressBlock: gc_gfxdec0 3313// base address: 0x28000 3314#define mmDB_RENDER_CONTROL 0x0000 3315#define mmDB_RENDER_CONTROL_BASE_IDX 1 3316#define mmDB_COUNT_CONTROL 0x0001 3317#define mmDB_COUNT_CONTROL_BASE_IDX 1 3318#define mmDB_DEPTH_VIEW 0x0002 3319#define mmDB_DEPTH_VIEW_BASE_IDX 1 3320#define mmDB_RENDER_OVERRIDE 0x0003 3321#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 3322#define mmDB_RENDER_OVERRIDE2 0x0004 3323#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 3324#define mmDB_HTILE_DATA_BASE 0x0005 3325#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 3326#define mmDB_HTILE_DATA_BASE_HI 0x0006 3327#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 3328#define mmDB_DEPTH_SIZE 0x0007 3329#define mmDB_DEPTH_SIZE_BASE_IDX 1 3330#define mmDB_DEPTH_BOUNDS_MIN 0x0008 3331#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 3332#define mmDB_DEPTH_BOUNDS_MAX 0x0009 3333#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 3334#define mmDB_STENCIL_CLEAR 0x000a 3335#define mmDB_STENCIL_CLEAR_BASE_IDX 1 3336#define mmDB_DEPTH_CLEAR 0x000b 3337#define mmDB_DEPTH_CLEAR_BASE_IDX 1 3338#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c 3339#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 3340#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d 3341#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 3342#define mmDB_Z_INFO 0x000e 3343#define mmDB_Z_INFO_BASE_IDX 1 3344#define mmDB_STENCIL_INFO 0x000f 3345#define mmDB_STENCIL_INFO_BASE_IDX 1 3346#define mmDB_Z_READ_BASE 0x0010 3347#define mmDB_Z_READ_BASE_BASE_IDX 1 3348#define mmDB_Z_READ_BASE_HI 0x0011 3349#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 3350#define mmDB_STENCIL_READ_BASE 0x0012 3351#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 3352#define mmDB_STENCIL_READ_BASE_HI 0x0013 3353#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 3354#define mmDB_Z_WRITE_BASE 0x0014 3355#define mmDB_Z_WRITE_BASE_BASE_IDX 1 3356#define mmDB_Z_WRITE_BASE_HI 0x0015 3357#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 3358#define mmDB_STENCIL_WRITE_BASE 0x0016 3359#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 3360#define mmDB_STENCIL_WRITE_BASE_HI 0x0017 3361#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3362#define mmDB_DFSM_CONTROL 0x0018 3363#define mmDB_DFSM_CONTROL_BASE_IDX 1 3364#define mmDB_Z_INFO2 0x001a 3365#define mmDB_Z_INFO2_BASE_IDX 1 3366#define mmDB_STENCIL_INFO2 0x001b 3367#define mmDB_STENCIL_INFO2_BASE_IDX 1 3368#define mmTA_BC_BASE_ADDR 0x0020 3369#define mmTA_BC_BASE_ADDR_BASE_IDX 1 3370#define mmTA_BC_BASE_ADDR_HI 0x0021 3371#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 3372#define mmCOHER_DEST_BASE_HI_0 0x007a 3373#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 3374#define mmCOHER_DEST_BASE_HI_1 0x007b 3375#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 3376#define mmCOHER_DEST_BASE_HI_2 0x007c 3377#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 3378#define mmCOHER_DEST_BASE_HI_3 0x007d 3379#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 3380#define mmCOHER_DEST_BASE_2 0x007e 3381#define mmCOHER_DEST_BASE_2_BASE_IDX 1 3382#define mmCOHER_DEST_BASE_3 0x007f 3383#define mmCOHER_DEST_BASE_3_BASE_IDX 1 3384#define mmPA_SC_WINDOW_OFFSET 0x0080 3385#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 3386#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 3387#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 3388#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 3389#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 3390#define mmPA_SC_CLIPRECT_RULE 0x0083 3391#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 3392#define mmPA_SC_CLIPRECT_0_TL 0x0084 3393#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 3394#define mmPA_SC_CLIPRECT_0_BR 0x0085 3395#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 3396#define mmPA_SC_CLIPRECT_1_TL 0x0086 3397#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 3398#define mmPA_SC_CLIPRECT_1_BR 0x0087 3399#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 3400#define mmPA_SC_CLIPRECT_2_TL 0x0088 3401#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 3402#define mmPA_SC_CLIPRECT_2_BR 0x0089 3403#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 3404#define mmPA_SC_CLIPRECT_3_TL 0x008a 3405#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 3406#define mmPA_SC_CLIPRECT_3_BR 0x008b 3407#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 3408#define mmPA_SC_EDGERULE 0x008c 3409#define mmPA_SC_EDGERULE_BASE_IDX 1 3410#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 3411#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 3412#define mmCB_TARGET_MASK 0x008e 3413#define mmCB_TARGET_MASK_BASE_IDX 1 3414#define mmCB_SHADER_MASK 0x008f 3415#define mmCB_SHADER_MASK_BASE_IDX 1 3416#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 3417#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 3418#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 3419#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 3420#define mmCOHER_DEST_BASE_0 0x0092 3421#define mmCOHER_DEST_BASE_0_BASE_IDX 1 3422#define mmCOHER_DEST_BASE_1 0x0093 3423#define mmCOHER_DEST_BASE_1_BASE_IDX 1 3424#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 3425#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 3426#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 3427#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 3428#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 3429#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 3430#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 3431#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 3432#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 3433#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 3434#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 3435#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 3436#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a 3437#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 3438#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b 3439#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 3440#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c 3441#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 3442#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d 3443#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 3444#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e 3445#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 3446#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f 3447#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 3448#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 3449#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 3450#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 3451#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 3452#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 3453#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 3454#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 3455#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 3456#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 3457#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 3458#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 3459#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 3460#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 3461#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 3462#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 3463#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 3464#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 3465#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 3466#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 3467#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 3468#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa 3469#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 3470#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab 3471#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 3472#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac 3473#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 3474#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad 3475#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 3476#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae 3477#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 3478#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af 3479#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 3480#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 3481#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 3482#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 3483#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 3484#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 3485#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 3486#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 3487#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 3488#define mmPA_SC_VPORT_ZMIN_0 0x00b4 3489#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 3490#define mmPA_SC_VPORT_ZMAX_0 0x00b5 3491#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 3492#define mmPA_SC_VPORT_ZMIN_1 0x00b6 3493#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 3494#define mmPA_SC_VPORT_ZMAX_1 0x00b7 3495#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 3496#define mmPA_SC_VPORT_ZMIN_2 0x00b8 3497#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 3498#define mmPA_SC_VPORT_ZMAX_2 0x00b9 3499#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 3500#define mmPA_SC_VPORT_ZMIN_3 0x00ba 3501#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 3502#define mmPA_SC_VPORT_ZMAX_3 0x00bb 3503#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 3504#define mmPA_SC_VPORT_ZMIN_4 0x00bc 3505#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 3506#define mmPA_SC_VPORT_ZMAX_4 0x00bd 3507#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 3508#define mmPA_SC_VPORT_ZMIN_5 0x00be 3509#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 3510#define mmPA_SC_VPORT_ZMAX_5 0x00bf 3511#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 3512#define mmPA_SC_VPORT_ZMIN_6 0x00c0 3513#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 3514#define mmPA_SC_VPORT_ZMAX_6 0x00c1 3515#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 3516#define mmPA_SC_VPORT_ZMIN_7 0x00c2 3517#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 3518#define mmPA_SC_VPORT_ZMAX_7 0x00c3 3519#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 3520#define mmPA_SC_VPORT_ZMIN_8 0x00c4 3521#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 3522#define mmPA_SC_VPORT_ZMAX_8 0x00c5 3523#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 3524#define mmPA_SC_VPORT_ZMIN_9 0x00c6 3525#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 3526#define mmPA_SC_VPORT_ZMAX_9 0x00c7 3527#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 3528#define mmPA_SC_VPORT_ZMIN_10 0x00c8 3529#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 3530#define mmPA_SC_VPORT_ZMAX_10 0x00c9 3531#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 3532#define mmPA_SC_VPORT_ZMIN_11 0x00ca 3533#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 3534#define mmPA_SC_VPORT_ZMAX_11 0x00cb 3535#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 3536#define mmPA_SC_VPORT_ZMIN_12 0x00cc 3537#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 3538#define mmPA_SC_VPORT_ZMAX_12 0x00cd 3539#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 3540#define mmPA_SC_VPORT_ZMIN_13 0x00ce 3541#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 3542#define mmPA_SC_VPORT_ZMAX_13 0x00cf 3543#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 3544#define mmPA_SC_VPORT_ZMIN_14 0x00d0 3545#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 3546#define mmPA_SC_VPORT_ZMAX_14 0x00d1 3547#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 3548#define mmPA_SC_VPORT_ZMIN_15 0x00d2 3549#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 3550#define mmPA_SC_VPORT_ZMAX_15 0x00d3 3551#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 3552#define mmPA_SC_RASTER_CONFIG 0x00d4 3553#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 3554#define mmPA_SC_RASTER_CONFIG_1 0x00d5 3555#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 3556#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 3557#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 3558#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 3559#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 3560#define mmCP_PERFMON_CNTX_CNTL 0x00d8 3561#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 3562#define mmCP_PIPEID 0x00d9 3563#define mmCP_PIPEID_BASE_IDX 1 3564#define mmCP_RINGID 0x00d9 3565#define mmCP_RINGID_BASE_IDX 1 3566#define mmCP_VMID 0x00da 3567#define mmCP_VMID_BASE_IDX 1 3568#define mmPA_SC_RIGHT_VERT_GRID 0x00e8 3569#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 3570#define mmPA_SC_LEFT_VERT_GRID 0x00e9 3571#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3572#define mmPA_SC_HORIZ_GRID 0x00ea 3573#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 3574#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3575#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3576#define mmCB_BLEND_RED 0x0105 3577#define mmCB_BLEND_RED_BASE_IDX 1 3578#define mmCB_BLEND_GREEN 0x0106 3579#define mmCB_BLEND_GREEN_BASE_IDX 1 3580#define mmCB_BLEND_BLUE 0x0107 3581#define mmCB_BLEND_BLUE_BASE_IDX 1 3582#define mmCB_BLEND_ALPHA 0x0108 3583#define mmCB_BLEND_ALPHA_BASE_IDX 1 3584#define mmCB_DCC_CONTROL 0x0109 3585#define mmCB_DCC_CONTROL_BASE_IDX 1 3586#define mmDB_STENCIL_CONTROL 0x010b 3587#define mmDB_STENCIL_CONTROL_BASE_IDX 1 3588#define mmDB_STENCILREFMASK 0x010c 3589#define mmDB_STENCILREFMASK_BASE_IDX 1 3590#define mmDB_STENCILREFMASK_BF 0x010d 3591#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 3592#define mmPA_CL_VPORT_XSCALE 0x010f 3593#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 3594#define mmPA_CL_VPORT_XOFFSET 0x0110 3595#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 3596#define mmPA_CL_VPORT_YSCALE 0x0111 3597#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 3598#define mmPA_CL_VPORT_YOFFSET 0x0112 3599#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 3600#define mmPA_CL_VPORT_ZSCALE 0x0113 3601#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 3602#define mmPA_CL_VPORT_ZOFFSET 0x0114 3603#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 3604#define mmPA_CL_VPORT_XSCALE_1 0x0115 3605#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 3606#define mmPA_CL_VPORT_XOFFSET_1 0x0116 3607#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 3608#define mmPA_CL_VPORT_YSCALE_1 0x0117 3609#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 3610#define mmPA_CL_VPORT_YOFFSET_1 0x0118 3611#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 3612#define mmPA_CL_VPORT_ZSCALE_1 0x0119 3613#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 3614#define mmPA_CL_VPORT_ZOFFSET_1 0x011a 3615#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 3616#define mmPA_CL_VPORT_XSCALE_2 0x011b 3617#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 3618#define mmPA_CL_VPORT_XOFFSET_2 0x011c 3619#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 3620#define mmPA_CL_VPORT_YSCALE_2 0x011d 3621#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 3622#define mmPA_CL_VPORT_YOFFSET_2 0x011e 3623#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 3624#define mmPA_CL_VPORT_ZSCALE_2 0x011f 3625#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 3626#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 3627#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 3628#define mmPA_CL_VPORT_XSCALE_3 0x0121 3629#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 3630#define mmPA_CL_VPORT_XOFFSET_3 0x0122 3631#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 3632#define mmPA_CL_VPORT_YSCALE_3 0x0123 3633#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 3634#define mmPA_CL_VPORT_YOFFSET_3 0x0124 3635#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 3636#define mmPA_CL_VPORT_ZSCALE_3 0x0125 3637#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 3638#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 3639#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 3640#define mmPA_CL_VPORT_XSCALE_4 0x0127 3641#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 3642#define mmPA_CL_VPORT_XOFFSET_4 0x0128 3643#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 3644#define mmPA_CL_VPORT_YSCALE_4 0x0129 3645#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 3646#define mmPA_CL_VPORT_YOFFSET_4 0x012a 3647#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 3648#define mmPA_CL_VPORT_ZSCALE_4 0x012b 3649#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 3650#define mmPA_CL_VPORT_ZOFFSET_4 0x012c 3651#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 3652#define mmPA_CL_VPORT_XSCALE_5 0x012d 3653#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 3654#define mmPA_CL_VPORT_XOFFSET_5 0x012e 3655#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 3656#define mmPA_CL_VPORT_YSCALE_5 0x012f 3657#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 3658#define mmPA_CL_VPORT_YOFFSET_5 0x0130 3659#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 3660#define mmPA_CL_VPORT_ZSCALE_5 0x0131 3661#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 3662#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 3663#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 3664#define mmPA_CL_VPORT_XSCALE_6 0x0133 3665#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 3666#define mmPA_CL_VPORT_XOFFSET_6 0x0134 3667#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 3668#define mmPA_CL_VPORT_YSCALE_6 0x0135 3669#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 3670#define mmPA_CL_VPORT_YOFFSET_6 0x0136 3671#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 3672#define mmPA_CL_VPORT_ZSCALE_6 0x0137 3673#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 3674#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 3675#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 3676#define mmPA_CL_VPORT_XSCALE_7 0x0139 3677#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 3678#define mmPA_CL_VPORT_XOFFSET_7 0x013a 3679#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 3680#define mmPA_CL_VPORT_YSCALE_7 0x013b 3681#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 3682#define mmPA_CL_VPORT_YOFFSET_7 0x013c 3683#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 3684#define mmPA_CL_VPORT_ZSCALE_7 0x013d 3685#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 3686#define mmPA_CL_VPORT_ZOFFSET_7 0x013e 3687#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 3688#define mmPA_CL_VPORT_XSCALE_8 0x013f 3689#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 3690#define mmPA_CL_VPORT_XOFFSET_8 0x0140 3691#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 3692#define mmPA_CL_VPORT_YSCALE_8 0x0141 3693#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 3694#define mmPA_CL_VPORT_YOFFSET_8 0x0142 3695#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 3696#define mmPA_CL_VPORT_ZSCALE_8 0x0143 3697#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 3698#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 3699#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 3700#define mmPA_CL_VPORT_XSCALE_9 0x0145 3701#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 3702#define mmPA_CL_VPORT_XOFFSET_9 0x0146 3703#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 3704#define mmPA_CL_VPORT_YSCALE_9 0x0147 3705#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 3706#define mmPA_CL_VPORT_YOFFSET_9 0x0148 3707#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 3708#define mmPA_CL_VPORT_ZSCALE_9 0x0149 3709#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 3710#define mmPA_CL_VPORT_ZOFFSET_9 0x014a 3711#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 3712#define mmPA_CL_VPORT_XSCALE_10 0x014b 3713#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 3714#define mmPA_CL_VPORT_XOFFSET_10 0x014c 3715#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 3716#define mmPA_CL_VPORT_YSCALE_10 0x014d 3717#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 3718#define mmPA_CL_VPORT_YOFFSET_10 0x014e 3719#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 3720#define mmPA_CL_VPORT_ZSCALE_10 0x014f 3721#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 3722#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 3723#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 3724#define mmPA_CL_VPORT_XSCALE_11 0x0151 3725#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 3726#define mmPA_CL_VPORT_XOFFSET_11 0x0152 3727#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 3728#define mmPA_CL_VPORT_YSCALE_11 0x0153 3729#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 3730#define mmPA_CL_VPORT_YOFFSET_11 0x0154 3731#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 3732#define mmPA_CL_VPORT_ZSCALE_11 0x0155 3733#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 3734#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 3735#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 3736#define mmPA_CL_VPORT_XSCALE_12 0x0157 3737#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 3738#define mmPA_CL_VPORT_XOFFSET_12 0x0158 3739#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 3740#define mmPA_CL_VPORT_YSCALE_12 0x0159 3741#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1 3742#define mmPA_CL_VPORT_YOFFSET_12 0x015a 3743#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 3744#define mmPA_CL_VPORT_ZSCALE_12 0x015b 3745#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 3746#define mmPA_CL_VPORT_ZOFFSET_12 0x015c 3747#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 3748#define mmPA_CL_VPORT_XSCALE_13 0x015d 3749#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 3750#define mmPA_CL_VPORT_XOFFSET_13 0x015e 3751#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 3752#define mmPA_CL_VPORT_YSCALE_13 0x015f 3753#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 3754#define mmPA_CL_VPORT_YOFFSET_13 0x0160 3755#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 3756#define mmPA_CL_VPORT_ZSCALE_13 0x0161 3757#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 3758#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 3759#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 3760#define mmPA_CL_VPORT_XSCALE_14 0x0163 3761#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 3762#define mmPA_CL_VPORT_XOFFSET_14 0x0164 3763#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 3764#define mmPA_CL_VPORT_YSCALE_14 0x0165 3765#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 3766#define mmPA_CL_VPORT_YOFFSET_14 0x0166 3767#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 3768#define mmPA_CL_VPORT_ZSCALE_14 0x0167 3769#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 3770#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 3771#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 3772#define mmPA_CL_VPORT_XSCALE_15 0x0169 3773#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 3774#define mmPA_CL_VPORT_XOFFSET_15 0x016a 3775#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 3776#define mmPA_CL_VPORT_YSCALE_15 0x016b 3777#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 3778#define mmPA_CL_VPORT_YOFFSET_15 0x016c 3779#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 3780#define mmPA_CL_VPORT_ZSCALE_15 0x016d 3781#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 3782#define mmPA_CL_VPORT_ZOFFSET_15 0x016e 3783#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 3784#define mmPA_CL_UCP_0_X 0x016f 3785#define mmPA_CL_UCP_0_X_BASE_IDX 1 3786#define mmPA_CL_UCP_0_Y 0x0170 3787#define mmPA_CL_UCP_0_Y_BASE_IDX 1 3788#define mmPA_CL_UCP_0_Z 0x0171 3789#define mmPA_CL_UCP_0_Z_BASE_IDX 1 3790#define mmPA_CL_UCP_0_W 0x0172 3791#define mmPA_CL_UCP_0_W_BASE_IDX 1 3792#define mmPA_CL_UCP_1_X 0x0173 3793#define mmPA_CL_UCP_1_X_BASE_IDX 1 3794#define mmPA_CL_UCP_1_Y 0x0174 3795#define mmPA_CL_UCP_1_Y_BASE_IDX 1 3796#define mmPA_CL_UCP_1_Z 0x0175 3797#define mmPA_CL_UCP_1_Z_BASE_IDX 1 3798#define mmPA_CL_UCP_1_W 0x0176 3799#define mmPA_CL_UCP_1_W_BASE_IDX 1 3800#define mmPA_CL_UCP_2_X 0x0177 3801#define mmPA_CL_UCP_2_X_BASE_IDX 1 3802#define mmPA_CL_UCP_2_Y 0x0178 3803#define mmPA_CL_UCP_2_Y_BASE_IDX 1 3804#define mmPA_CL_UCP_2_Z 0x0179 3805#define mmPA_CL_UCP_2_Z_BASE_IDX 1 3806#define mmPA_CL_UCP_2_W 0x017a 3807#define mmPA_CL_UCP_2_W_BASE_IDX 1 3808#define mmPA_CL_UCP_3_X 0x017b 3809#define mmPA_CL_UCP_3_X_BASE_IDX 1 3810#define mmPA_CL_UCP_3_Y 0x017c 3811#define mmPA_CL_UCP_3_Y_BASE_IDX 1 3812#define mmPA_CL_UCP_3_Z 0x017d 3813#define mmPA_CL_UCP_3_Z_BASE_IDX 1 3814#define mmPA_CL_UCP_3_W 0x017e 3815#define mmPA_CL_UCP_3_W_BASE_IDX 1 3816#define mmPA_CL_UCP_4_X 0x017f 3817#define mmPA_CL_UCP_4_X_BASE_IDX 1 3818#define mmPA_CL_UCP_4_Y 0x0180 3819#define mmPA_CL_UCP_4_Y_BASE_IDX 1 3820#define mmPA_CL_UCP_4_Z 0x0181 3821#define mmPA_CL_UCP_4_Z_BASE_IDX 1 3822#define mmPA_CL_UCP_4_W 0x0182 3823#define mmPA_CL_UCP_4_W_BASE_IDX 1 3824#define mmPA_CL_UCP_5_X 0x0183 3825#define mmPA_CL_UCP_5_X_BASE_IDX 1 3826#define mmPA_CL_UCP_5_Y 0x0184 3827#define mmPA_CL_UCP_5_Y_BASE_IDX 1 3828#define mmPA_CL_UCP_5_Z 0x0185 3829#define mmPA_CL_UCP_5_Z_BASE_IDX 1 3830#define mmPA_CL_UCP_5_W 0x0186 3831#define mmPA_CL_UCP_5_W_BASE_IDX 1 3832#define mmSPI_PS_INPUT_CNTL_0 0x0191 3833#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 3834#define mmSPI_PS_INPUT_CNTL_1 0x0192 3835#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 3836#define mmSPI_PS_INPUT_CNTL_2 0x0193 3837#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 3838#define mmSPI_PS_INPUT_CNTL_3 0x0194 3839#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 3840#define mmSPI_PS_INPUT_CNTL_4 0x0195 3841#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 3842#define mmSPI_PS_INPUT_CNTL_5 0x0196 3843#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 3844#define mmSPI_PS_INPUT_CNTL_6 0x0197 3845#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 3846#define mmSPI_PS_INPUT_CNTL_7 0x0198 3847#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 3848#define mmSPI_PS_INPUT_CNTL_8 0x0199 3849#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 3850#define mmSPI_PS_INPUT_CNTL_9 0x019a 3851#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 3852#define mmSPI_PS_INPUT_CNTL_10 0x019b 3853#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 3854#define mmSPI_PS_INPUT_CNTL_11 0x019c 3855#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 3856#define mmSPI_PS_INPUT_CNTL_12 0x019d 3857#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 3858#define mmSPI_PS_INPUT_CNTL_13 0x019e 3859#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 3860#define mmSPI_PS_INPUT_CNTL_14 0x019f 3861#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 3862#define mmSPI_PS_INPUT_CNTL_15 0x01a0 3863#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 3864#define mmSPI_PS_INPUT_CNTL_16 0x01a1 3865#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 3866#define mmSPI_PS_INPUT_CNTL_17 0x01a2 3867#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 3868#define mmSPI_PS_INPUT_CNTL_18 0x01a3 3869#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 3870#define mmSPI_PS_INPUT_CNTL_19 0x01a4 3871#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 3872#define mmSPI_PS_INPUT_CNTL_20 0x01a5 3873#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 3874#define mmSPI_PS_INPUT_CNTL_21 0x01a6 3875#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 3876#define mmSPI_PS_INPUT_CNTL_22 0x01a7 3877#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 3878#define mmSPI_PS_INPUT_CNTL_23 0x01a8 3879#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 3880#define mmSPI_PS_INPUT_CNTL_24 0x01a9 3881#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 3882#define mmSPI_PS_INPUT_CNTL_25 0x01aa 3883#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 3884#define mmSPI_PS_INPUT_CNTL_26 0x01ab 3885#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 3886#define mmSPI_PS_INPUT_CNTL_27 0x01ac 3887#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 3888#define mmSPI_PS_INPUT_CNTL_28 0x01ad 3889#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 3890#define mmSPI_PS_INPUT_CNTL_29 0x01ae 3891#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 3892#define mmSPI_PS_INPUT_CNTL_30 0x01af 3893#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 3894#define mmSPI_PS_INPUT_CNTL_31 0x01b0 3895#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 3896#define mmSPI_VS_OUT_CONFIG 0x01b1 3897#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 3898#define mmSPI_PS_INPUT_ENA 0x01b3 3899#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 3900#define mmSPI_PS_INPUT_ADDR 0x01b4 3901#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 3902#define mmSPI_INTERP_CONTROL_0 0x01b5 3903#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 3904#define mmSPI_PS_IN_CONTROL 0x01b6 3905#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 3906#define mmSPI_BARYC_CNTL 0x01b8 3907#define mmSPI_BARYC_CNTL_BASE_IDX 1 3908#define mmSPI_TMPRING_SIZE 0x01ba 3909#define mmSPI_TMPRING_SIZE_BASE_IDX 1 3910#define mmSPI_SHADER_POS_FORMAT 0x01c3 3911#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 3912#define mmSPI_SHADER_Z_FORMAT 0x01c4 3913#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 3914#define mmSPI_SHADER_COL_FORMAT 0x01c5 3915#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 3916#define mmSX_PS_DOWNCONVERT 0x01d5 3917#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 3918#define mmSX_BLEND_OPT_EPSILON 0x01d6 3919#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 3920#define mmSX_BLEND_OPT_CONTROL 0x01d7 3921#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 3922#define mmSX_MRT0_BLEND_OPT 0x01d8 3923#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 3924#define mmSX_MRT1_BLEND_OPT 0x01d9 3925#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 3926#define mmSX_MRT2_BLEND_OPT 0x01da 3927#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 3928#define mmSX_MRT3_BLEND_OPT 0x01db 3929#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 3930#define mmSX_MRT4_BLEND_OPT 0x01dc 3931#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 3932#define mmSX_MRT5_BLEND_OPT 0x01dd 3933#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 3934#define mmSX_MRT6_BLEND_OPT 0x01de 3935#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 3936#define mmSX_MRT7_BLEND_OPT 0x01df 3937#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 3938#define mmCB_BLEND0_CONTROL 0x01e0 3939#define mmCB_BLEND0_CONTROL_BASE_IDX 1 3940#define mmCB_BLEND1_CONTROL 0x01e1 3941#define mmCB_BLEND1_CONTROL_BASE_IDX 1 3942#define mmCB_BLEND2_CONTROL 0x01e2 3943#define mmCB_BLEND2_CONTROL_BASE_IDX 1 3944#define mmCB_BLEND3_CONTROL 0x01e3 3945#define mmCB_BLEND3_CONTROL_BASE_IDX 1 3946#define mmCB_BLEND4_CONTROL 0x01e4 3947#define mmCB_BLEND4_CONTROL_BASE_IDX 1 3948#define mmCB_BLEND5_CONTROL 0x01e5 3949#define mmCB_BLEND5_CONTROL_BASE_IDX 1 3950#define mmCB_BLEND6_CONTROL 0x01e6 3951#define mmCB_BLEND6_CONTROL_BASE_IDX 1 3952#define mmCB_BLEND7_CONTROL 0x01e7 3953#define mmCB_BLEND7_CONTROL_BASE_IDX 1 3954#define mmCB_MRT0_EPITCH 0x01e8 3955#define mmCB_MRT0_EPITCH_BASE_IDX 1 3956#define mmCB_MRT1_EPITCH 0x01e9 3957#define mmCB_MRT1_EPITCH_BASE_IDX 1 3958#define mmCB_MRT2_EPITCH 0x01ea 3959#define mmCB_MRT2_EPITCH_BASE_IDX 1 3960#define mmCB_MRT3_EPITCH 0x01eb 3961#define mmCB_MRT3_EPITCH_BASE_IDX 1 3962#define mmCB_MRT4_EPITCH 0x01ec 3963#define mmCB_MRT4_EPITCH_BASE_IDX 1 3964#define mmCB_MRT5_EPITCH 0x01ed 3965#define mmCB_MRT5_EPITCH_BASE_IDX 1 3966#define mmCB_MRT6_EPITCH 0x01ee 3967#define mmCB_MRT6_EPITCH_BASE_IDX 1 3968#define mmCB_MRT7_EPITCH 0x01ef 3969#define mmCB_MRT7_EPITCH_BASE_IDX 1 3970#define mmCS_COPY_STATE 0x01f3 3971#define mmCS_COPY_STATE_BASE_IDX 1 3972#define mmGFX_COPY_STATE 0x01f4 3973#define mmGFX_COPY_STATE_BASE_IDX 1 3974#define mmPA_CL_POINT_X_RAD 0x01f5 3975#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 3976#define mmPA_CL_POINT_Y_RAD 0x01f6 3977#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 3978#define mmPA_CL_POINT_SIZE 0x01f7 3979#define mmPA_CL_POINT_SIZE_BASE_IDX 1 3980#define mmPA_CL_POINT_CULL_RAD 0x01f8 3981#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 3982#define mmVGT_DMA_BASE_HI 0x01f9 3983#define mmVGT_DMA_BASE_HI_BASE_IDX 1 3984#define mmVGT_DMA_BASE 0x01fa 3985#define mmVGT_DMA_BASE_BASE_IDX 1 3986#define mmVGT_DRAW_INITIATOR 0x01fc 3987#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 3988#define mmVGT_IMMED_DATA 0x01fd 3989#define mmVGT_IMMED_DATA_BASE_IDX 1 3990#define mmVGT_EVENT_ADDRESS_REG 0x01fe 3991#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 3992#define mmDB_DEPTH_CONTROL 0x0200 3993#define mmDB_DEPTH_CONTROL_BASE_IDX 1 3994#define mmDB_EQAA 0x0201 3995#define mmDB_EQAA_BASE_IDX 1 3996#define mmCB_COLOR_CONTROL 0x0202 3997#define mmCB_COLOR_CONTROL_BASE_IDX 1 3998#define mmDB_SHADER_CONTROL 0x0203 3999#define mmDB_SHADER_CONTROL_BASE_IDX 1 4000#define mmPA_CL_CLIP_CNTL 0x0204
4001#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 4002#define mmPA_SU_SC_MODE_CNTL 0x0205 4003#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 4004#define mmPA_CL_VTE_CNTL 0x0206 4005#define mmPA_CL_VTE_CNTL_BASE_IDX 1 4006#define mmPA_CL_VS_OUT_CNTL 0x0207 4007#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 4008#define mmPA_CL_NANINF_CNTL 0x0208 4009#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 4010#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 4011#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 4012#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a 4013#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 4014#define mmPA_SU_PRIM_FILTER_CNTL 0x020b 4015#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 4016#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 4017#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 4018#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d 4019#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 4020#define mmPA_CL_NGG_CNTL 0x020e 4021#define mmPA_CL_NGG_CNTL_BASE_IDX 1 4022#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f 4023#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 4024#define mmPA_SU_POINT_SIZE 0x0280 4025#define mmPA_SU_POINT_SIZE_BASE_IDX 1 4026#define mmPA_SU_POINT_MINMAX 0x0281 4027#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 4028#define mmPA_SU_LINE_CNTL 0x0282 4029#define mmPA_SU_LINE_CNTL_BASE_IDX 1 4030#define mmPA_SC_LINE_STIPPLE 0x0283 4031#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 4032#define mmVGT_OUTPUT_PATH_CNTL 0x0284 4033#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 4034#define mmVGT_HOS_CNTL 0x0285 4035#define mmVGT_HOS_CNTL_BASE_IDX 1 4036#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 4037#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 4038#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 4039#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 4040#define mmVGT_HOS_REUSE_DEPTH 0x0288 4041#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 4042#define mmVGT_GROUP_PRIM_TYPE 0x0289 4043#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 4044#define mmVGT_GROUP_FIRST_DECR 0x028a 4045#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 4046#define mmVGT_GROUP_DECR 0x028b 4047#define mmVGT_GROUP_DECR_BASE_IDX 1 4048#define mmVGT_GROUP_VECT_0_CNTL 0x028c 4049#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 4050#define mmVGT_GROUP_VECT_1_CNTL 0x028d 4051#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 4052#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e 4053#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 4054#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f 4055#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 4056#define mmVGT_GS_MODE 0x0290 4057#define mmVGT_GS_MODE_BASE_IDX 1 4058#define mmVGT_GS_ONCHIP_CNTL 0x0291 4059#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 4060#define mmPA_SC_MODE_CNTL_0 0x0292 4061#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 4062#define mmPA_SC_MODE_CNTL_1 0x0293 4063#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 4064#define mmVGT_ENHANCE 0x0294 4065#define mmVGT_ENHANCE_BASE_IDX 1 4066#define mmVGT_GS_PER_ES 0x0295 4067#define mmVGT_GS_PER_ES_BASE_IDX 1 4068#define mmVGT_ES_PER_GS 0x0296 4069#define mmVGT_ES_PER_GS_BASE_IDX 1 4070#define mmVGT_GS_PER_VS 0x0297 4071#define mmVGT_GS_PER_VS_BASE_IDX 1 4072#define mmVGT_GSVS_RING_OFFSET_1 0x0298 4073#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 4074#define mmVGT_GSVS_RING_OFFSET_2 0x0299 4075#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 4076#define mmVGT_GSVS_RING_OFFSET_3 0x029a 4077#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 4078#define mmVGT_GS_OUT_PRIM_TYPE 0x029b 4079#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 4080#define mmIA_ENHANCE 0x029c 4081#define mmIA_ENHANCE_BASE_IDX 1 4082#define mmVGT_DMA_SIZE 0x029d 4083#define mmVGT_DMA_SIZE_BASE_IDX 1 4084#define mmVGT_DMA_MAX_SIZE 0x029e 4085#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 4086#define mmVGT_DMA_INDEX_TYPE 0x029f 4087#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 4088#define mmWD_ENHANCE 0x02a0 4089#define mmWD_ENHANCE_BASE_IDX 1 4090#define mmVGT_PRIMITIVEID_EN 0x02a1 4091#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 4092#define mmVGT_DMA_NUM_INSTANCES 0x02a2 4093#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 4094#define mmVGT_PRIMITIVEID_RESET 0x02a3 4095#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 4096#define mmVGT_EVENT_INITIATOR 0x02a4 4097#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 4098#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 4099#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4100#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 4101#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4102#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 4103#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4104#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 4105#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 4106#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab 4107#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 4108#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac 4109#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 4110#define mmVGT_REUSE_OFF 0x02ad 4111#define mmVGT_REUSE_OFF_BASE_IDX 1 4112#define mmVGT_VTX_CNT_EN 0x02ae 4113#define mmVGT_VTX_CNT_EN_BASE_IDX 1 4114#define mmDB_HTILE_SURFACE 0x02af 4115#define mmDB_HTILE_SURFACE_BASE_IDX 1 4116#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 4117#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 4118#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 4119#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 4120#define mmDB_PRELOAD_CONTROL 0x02b2 4121#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 4122#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 4123#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 4124#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 4125#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 4126#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 4127#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 4128#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 4129#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 4130#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 4131#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 4132#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb 4133#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 4134#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc 4135#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 4136#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd 4137#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 4138#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf 4139#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 4140#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 4141#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 4142#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 4143#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 4144#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 4145#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 4146#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 4147#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 4148#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 4149#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 4150#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 4151#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 4152#define mmVGT_GS_MAX_VERT_OUT 0x02ce 4153#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 4154#define mmVGT_TESS_DISTRIBUTION 0x02d4 4155#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 4156#define mmVGT_SHADER_STAGES_EN 0x02d5 4157#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 4158#define mmVGT_LS_HS_CONFIG 0x02d6 4159#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 4160#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 4161#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 4162#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 4163#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 4164#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 4165#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 4166#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da 4167#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 4168#define mmVGT_TF_PARAM 0x02db 4169#define mmVGT_TF_PARAM_BASE_IDX 1 4170#define mmDB_ALPHA_TO_MASK 0x02dc 4171#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 4172#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd 4173#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 4174#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 4175#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 4176#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df 4177#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 4178#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 4179#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 4180#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 4181#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 4182#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 4183#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 4184#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 4185#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 4186#define mmVGT_GS_INSTANCE_CNT 0x02e4 4187#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 4188#define mmVGT_STRMOUT_CONFIG 0x02e5 4189#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 4190#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 4191#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 4192#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 4193#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 4194#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 4195#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 4196#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 4197#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 4198#define mmPA_SC_LINE_CNTL 0x02f7 4199#define mmPA_SC_LINE_CNTL_BASE_IDX 1 4200#define mmPA_SC_AA_CONFIG 0x02f8 4201#define mmPA_SC_AA_CONFIG_BASE_IDX 1 4202#define mmPA_SU_VTX_CNTL 0x02f9 4203#define mmPA_SU_VTX_CNTL_BASE_IDX 1 4204#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa 4205#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 4206#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb 4207#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 4208#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 4209#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 4210#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd 4211#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 4212#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 4213#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 4214#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 4215#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 4216#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 4217#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 4218#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 4219#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 4220#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 4221#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 4222#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 4223#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 4224#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 4225#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 4226#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 4227#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 4228#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 4229#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 4230#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 4231#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 4232#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 4233#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 4234#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 4235#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 4236#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 4237#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 4238#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 4239#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 4240#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 4241#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 4242#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 4243#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 4244#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 4245#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 4246#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 4247#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 4248#define mmPA_SC_SHADER_CONTROL 0x0310 4249#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 4250#define mmPA_SC_BINNER_CNTL_0 0x0311 4251#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 4252#define mmPA_SC_BINNER_CNTL_1 0x0312 4253#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 4254#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 4255#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 4256#define mmPA_SC_NGG_MODE_CNTL 0x0314 4257#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 4258#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 4259#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 4260#define mmVGT_OUT_DEALLOC_CNTL 0x0317 4261#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 4262#define mmCB_COLOR0_BASE 0x0318 4263#define mmCB_COLOR0_BASE_BASE_IDX 1 4264#define mmCB_COLOR0_BASE_EXT 0x0319 4265#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 4266#define mmCB_COLOR0_ATTRIB2 0x031a 4267#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 4268#define mmCB_COLOR0_VIEW 0x031b 4269#define mmCB_COLOR0_VIEW_BASE_IDX 1 4270#define mmCB_COLOR0_INFO 0x031c 4271#define mmCB_COLOR0_INFO_BASE_IDX 1 4272#define mmCB_COLOR0_ATTRIB 0x031d 4273#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 4274#define mmCB_COLOR0_DCC_CONTROL 0x031e 4275#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 4276#define mmCB_COLOR0_CMASK 0x031f 4277#define mmCB_COLOR0_CMASK_BASE_IDX 1 4278#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320 4279#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 4280#define mmCB_COLOR0_FMASK 0x0321 4281#define mmCB_COLOR0_FMASK_BASE_IDX 1 4282#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322 4283#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 4284#define mmCB_COLOR0_CLEAR_WORD0 0x0323 4285#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 4286#define mmCB_COLOR0_CLEAR_WORD1 0x0324 4287#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 4288#define mmCB_COLOR0_DCC_BASE 0x0325 4289#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 4290#define mmCB_COLOR0_DCC_BASE_EXT 0x0326 4291#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 4292#define mmCB_COLOR1_BASE 0x0327 4293#define mmCB_COLOR1_BASE_BASE_IDX 1 4294#define mmCB_COLOR1_BASE_EXT 0x0328 4295#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 4296#define mmCB_COLOR1_ATTRIB2 0x0329 4297#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 4298#define mmCB_COLOR1_VIEW 0x032a 4299#define mmCB_COLOR1_VIEW_BASE_IDX 1 4300#define mmCB_COLOR1_INFO 0x032b 4301#define mmCB_COLOR1_INFO_BASE_IDX 1 4302#define mmCB_COLOR1_ATTRIB 0x032c 4303#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 4304#define mmCB_COLOR1_DCC_CONTROL 0x032d 4305#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 4306#define mmCB_COLOR1_CMASK 0x032e 4307#define mmCB_COLOR1_CMASK_BASE_IDX 1 4308#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f 4309#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 4310#define mmCB_COLOR1_FMASK 0x0330 4311#define mmCB_COLOR1_FMASK_BASE_IDX 1 4312#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331 4313#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 4314#define mmCB_COLOR1_CLEAR_WORD0 0x0332 4315#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 4316#define mmCB_COLOR1_CLEAR_WORD1 0x0333 4317#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 4318#define mmCB_COLOR1_DCC_BASE 0x0334 4319#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 4320#define mmCB_COLOR1_DCC_BASE_EXT 0x0335 4321#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 4322#define mmCB_COLOR2_BASE 0x0336 4323#define mmCB_COLOR2_BASE_BASE_IDX 1 4324#define mmCB_COLOR2_BASE_EXT 0x0337 4325#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 4326#define mmCB_COLOR2_ATTRIB2 0x0338 4327#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 4328#define mmCB_COLOR2_VIEW 0x0339 4329#define mmCB_COLOR2_VIEW_BASE_IDX 1 4330#define mmCB_COLOR2_INFO 0x033a 4331#define mmCB_COLOR2_INFO_BASE_IDX 1 4332#define mmCB_COLOR2_ATTRIB 0x033b 4333#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 4334#define mmCB_COLOR2_DCC_CONTROL 0x033c 4335#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 4336#define mmCB_COLOR2_CMASK 0x033d 4337#define mmCB_COLOR2_CMASK_BASE_IDX 1 4338#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e 4339#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 4340#define mmCB_COLOR2_FMASK 0x033f 4341#define mmCB_COLOR2_FMASK_BASE_IDX 1 4342#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340 4343#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 4344#define mmCB_COLOR2_CLEAR_WORD0 0x0341 4345#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 4346#define mmCB_COLOR2_CLEAR_WORD1 0x0342 4347#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 4348#define mmCB_COLOR2_DCC_BASE 0x0343 4349#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 4350#define mmCB_COLOR2_DCC_BASE_EXT 0x0344 4351#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 4352#define mmCB_COLOR3_BASE 0x0345 4353#define mmCB_COLOR3_BASE_BASE_IDX 1 4354#define mmCB_COLOR3_BASE_EXT 0x0346 4355#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 4356#define mmCB_COLOR3_ATTRIB2 0x0347 4357#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 4358#define mmCB_COLOR3_VIEW 0x0348 4359#define mmCB_COLOR3_VIEW_BASE_IDX 1 4360#define mmCB_COLOR3_INFO 0x0349 4361#define mmCB_COLOR3_INFO_BASE_IDX 1 4362#define mmCB_COLOR3_ATTRIB 0x034a 4363#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 4364#define mmCB_COLOR3_DCC_CONTROL 0x034b 4365#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 4366#define mmCB_COLOR3_CMASK 0x034c 4367#define mmCB_COLOR3_CMASK_BASE_IDX 1 4368#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d 4369#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 4370#define mmCB_COLOR3_FMASK 0x034e 4371#define mmCB_COLOR3_FMASK_BASE_IDX 1 4372#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f 4373#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 4374#define mmCB_COLOR3_CLEAR_WORD0 0x0350 4375#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 4376#define mmCB_COLOR3_CLEAR_WORD1 0x0351 4377#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 4378#define mmCB_COLOR3_DCC_BASE 0x0352 4379#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 4380#define mmCB_COLOR3_DCC_BASE_EXT 0x0353 4381#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 4382#define mmCB_COLOR4_BASE 0x0354 4383#define mmCB_COLOR4_BASE_BASE_IDX 1 4384#define mmCB_COLOR4_BASE_EXT 0x0355 4385#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 4386#define mmCB_COLOR4_ATTRIB2 0x0356 4387#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 4388#define mmCB_COLOR4_VIEW 0x0357 4389#define mmCB_COLOR4_VIEW_BASE_IDX 1 4390#define mmCB_COLOR4_INFO 0x0358 4391#define mmCB_COLOR4_INFO_BASE_IDX 1 4392#define mmCB_COLOR4_ATTRIB 0x0359 4393#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 4394#define mmCB_COLOR4_DCC_CONTROL 0x035a 4395#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 4396#define mmCB_COLOR4_CMASK 0x035b 4397#define mmCB_COLOR4_CMASK_BASE_IDX 1 4398#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c 4399#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 4400#define mmCB_COLOR4_FMASK 0x035d 4401#define mmCB_COLOR4_FMASK_BASE_IDX 1 4402#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e 4403#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 4404#define mmCB_COLOR4_CLEAR_WORD0 0x035f 4405#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 4406#define mmCB_COLOR4_CLEAR_WORD1 0x0360 4407#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 4408#define mmCB_COLOR4_DCC_BASE 0x0361 4409#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 4410#define mmCB_COLOR4_DCC_BASE_EXT 0x0362 4411#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 4412#define mmCB_COLOR5_BASE 0x0363 4413#define mmCB_COLOR5_BASE_BASE_IDX 1 4414#define mmCB_COLOR5_BASE_EXT 0x0364 4415#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 4416#define mmCB_COLOR5_ATTRIB2 0x0365 4417#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 4418#define mmCB_COLOR5_VIEW 0x0366 4419#define mmCB_COLOR5_VIEW_BASE_IDX 1 4420#define mmCB_COLOR5_INFO 0x0367 4421#define mmCB_COLOR5_INFO_BASE_IDX 1 4422#define mmCB_COLOR5_ATTRIB 0x0368 4423#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 4424#define mmCB_COLOR5_DCC_CONTROL 0x0369 4425#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 4426#define mmCB_COLOR5_CMASK 0x036a 4427#define mmCB_COLOR5_CMASK_BASE_IDX 1 4428#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b 4429#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 4430#define mmCB_COLOR5_FMASK 0x036c 4431#define mmCB_COLOR5_FMASK_BASE_IDX 1 4432#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d 4433#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 4434#define mmCB_COLOR5_CLEAR_WORD0 0x036e 4435#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 4436#define mmCB_COLOR5_CLEAR_WORD1 0x036f 4437#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 4438#define mmCB_COLOR5_DCC_BASE 0x0370 4439#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 4440#define mmCB_COLOR5_DCC_BASE_EXT 0x0371 4441#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 4442#define mmCB_COLOR6_BASE 0x0372 4443#define mmCB_COLOR6_BASE_BASE_IDX 1 4444#define mmCB_COLOR6_BASE_EXT 0x0373 4445#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 4446#define mmCB_COLOR6_ATTRIB2 0x0374 4447#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 4448#define mmCB_COLOR6_VIEW 0x0375 4449#define mmCB_COLOR6_VIEW_BASE_IDX 1 4450#define mmCB_COLOR6_INFO 0x0376 4451#define mmCB_COLOR6_INFO_BASE_IDX 1 4452#define mmCB_COLOR6_ATTRIB 0x0377 4453#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 4454#define mmCB_COLOR6_DCC_CONTROL 0x0378 4455#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 4456#define mmCB_COLOR6_CMASK 0x0379 4457#define mmCB_COLOR6_CMASK_BASE_IDX 1 4458#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a 4459#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 4460#define mmCB_COLOR6_FMASK 0x037b 4461#define mmCB_COLOR6_FMASK_BASE_IDX 1 4462#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c 4463#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 4464#define mmCB_COLOR6_CLEAR_WORD0 0x037d 4465#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 4466#define mmCB_COLOR6_CLEAR_WORD1 0x037e 4467#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 4468#define mmCB_COLOR6_DCC_BASE 0x037f 4469#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 4470#define mmCB_COLOR6_DCC_BASE_EXT 0x0380 4471#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 4472#define mmCB_COLOR7_BASE 0x0381 4473#define mmCB_COLOR7_BASE_BASE_IDX 1 4474#define mmCB_COLOR7_BASE_EXT 0x0382 4475#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 4476#define mmCB_COLOR7_ATTRIB2 0x0383 4477#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 4478#define mmCB_COLOR7_VIEW 0x0384 4479#define mmCB_COLOR7_VIEW_BASE_IDX 1 4480#define mmCB_COLOR7_INFO 0x0385 4481#define mmCB_COLOR7_INFO_BASE_IDX 1 4482#define mmCB_COLOR7_ATTRIB 0x0386 4483#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 4484#define mmCB_COLOR7_DCC_CONTROL 0x0387 4485#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 4486#define mmCB_COLOR7_CMASK 0x0388 4487#define mmCB_COLOR7_CMASK_BASE_IDX 1 4488#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389 4489#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 4490#define mmCB_COLOR7_FMASK 0x038a 4491#define mmCB_COLOR7_FMASK_BASE_IDX 1 4492#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b 4493#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 4494#define mmCB_COLOR7_CLEAR_WORD0 0x038c 4495#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 4496#define mmCB_COLOR7_CLEAR_WORD1 0x038d 4497#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 4498#define mmCB_COLOR7_DCC_BASE 0x038e 4499#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 4500#define mmCB_COLOR7_DCC_BASE_EXT 0x038f 4501#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 4502 4503 4504// addressBlock: gc_gfxudec 4505// base address: 0x30000 4506#define mmCP_EOP_DONE_ADDR_LO 0x2000 4507#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 4508#define mmCP_EOP_DONE_ADDR_HI 0x2001 4509#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 4510#define mmCP_EOP_DONE_DATA_LO 0x2002 4511#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 4512#define mmCP_EOP_DONE_DATA_HI 0x2003 4513#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 4514#define mmCP_EOP_LAST_FENCE_LO 0x2004 4515#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 4516#define mmCP_EOP_LAST_FENCE_HI 0x2005 4517#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 4518#define mmCP_STREAM_OUT_ADDR_LO 0x2006 4519#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 4520#define mmCP_STREAM_OUT_ADDR_HI 0x2007 4521#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 4522#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 4523#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 4524#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 4525#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 4526#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a 4527#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 4528#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b 4529#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 4530#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c 4531#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 4532#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d 4533#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 4534#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e 4535#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 4536#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f 4537#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 4538#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 4539#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 4540#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 4541#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 4542#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 4543#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 4544#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 4545#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 4546#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 4547#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 4548#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 4549#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 4550#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 4551#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 4552#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 4553#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 4554#define mmCP_PIPE_STATS_ADDR_LO 0x2018 4555#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 4556#define mmCP_PIPE_STATS_ADDR_HI 0x2019 4557#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 4558#define mmCP_VGT_IAVERT_COUNT_LO 0x201a 4559#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 4560#define mmCP_VGT_IAVERT_COUNT_HI 0x201b 4561#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 4562#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c 4563#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 4564#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d 4565#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 4566#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e 4567#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 4568#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f 4569#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 4570#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 4571#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 4572#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 4573#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 4574#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 4575#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 4576#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 4577#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 4578#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 4579#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 4580#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 4581#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 4582#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 4583#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 4584#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 4585#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 4586#define mmCP_PA_CINVOC_COUNT_LO 0x2028 4587#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 4588#define mmCP_PA_CINVOC_COUNT_HI 0x2029 4589#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 4590#define mmCP_PA_CPRIM_COUNT_LO 0x202a 4591#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 4592#define mmCP_PA_CPRIM_COUNT_HI 0x202b 4593#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 4594#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c 4595#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 4596#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d 4597#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 4598#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e 4599#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 4600#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f 4601#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 4602#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 4603#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 4604#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 4605#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 4606#define mmCP_PIPE_STATS_CONTROL 0x203d 4607#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 4608#define mmCP_STREAM_OUT_CONTROL 0x203e 4609#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 4610#define mmCP_STRMOUT_CNTL 0x203f 4611#define mmCP_STRMOUT_CNTL_BASE_IDX 1 4612#define mmSCRATCH_REG0 0x2040 4613#define mmSCRATCH_REG0_BASE_IDX 1 4614#define mmSCRATCH_REG1 0x2041 4615#define mmSCRATCH_REG1_BASE_IDX 1 4616#define mmSCRATCH_REG2 0x2042 4617#define mmSCRATCH_REG2_BASE_IDX 1 4618#define mmSCRATCH_REG3 0x2043 4619#define mmSCRATCH_REG3_BASE_IDX 1 4620#define mmSCRATCH_REG4 0x2044 4621#define mmSCRATCH_REG4_BASE_IDX 1 4622#define mmSCRATCH_REG5 0x2045 4623#define mmSCRATCH_REG5_BASE_IDX 1 4624#define mmSCRATCH_REG6 0x2046 4625#define mmSCRATCH_REG6_BASE_IDX 1 4626#define mmSCRATCH_REG7 0x2047 4627#define mmSCRATCH_REG7_BASE_IDX 1 4628#define mmCP_APPEND_DATA_HI 0x204c 4629#define mmCP_APPEND_DATA_HI_BASE_IDX 1 4630#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d 4631#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 4632#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e 4633#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 4634#define mmSCRATCH_UMSK 0x2050 4635#define mmSCRATCH_UMSK_BASE_IDX 1 4636#define mmSCRATCH_ADDR 0x2051 4637#define mmSCRATCH_ADDR_BASE_IDX 1 4638#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 4639#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 4640#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 4641#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 4642#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 4643#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4644#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 4645#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4646#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 4647#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4648#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 4649#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4650#define mmCP_APPEND_ADDR_LO 0x2058 4651#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 4652#define mmCP_APPEND_ADDR_HI 0x2059 4653#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 4654#define mmCP_APPEND_DATA_LO 0x205a 4655#define mmCP_APPEND_DATA_LO_BASE_IDX 1 4656#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b 4657#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 4658#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c 4659#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 4660#define mmCP_ATOMIC_PREOP_LO 0x205d 4661#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 4662#define mmCP_ME_ATOMIC_PREOP_LO 0x205d 4663#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 4664#define mmCP_ATOMIC_PREOP_HI 0x205e 4665#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 4666#define mmCP_ME_ATOMIC_PREOP_HI 0x205e 4667#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 4668#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f 4669#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4670#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 4671#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4672#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 4673#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4674#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 4675#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4676#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 4677#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4678#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 4679#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4680#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 4681#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4682#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 4683#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4684#define mmCP_ME_MC_WADDR_LO 0x2069 4685#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 4686#define mmCP_ME_MC_WADDR_HI 0x206a 4687#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 4688#define mmCP_ME_MC_WDATA_LO 0x206b 4689#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 4690#define mmCP_ME_MC_WDATA_HI 0x206c 4691#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 4692#define mmCP_ME_MC_RADDR_LO 0x206d 4693#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 4694#define mmCP_ME_MC_RADDR_HI 0x206e 4695#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 4696#define mmCP_SEM_WAIT_TIMER 0x206f 4697#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 4698#define mmCP_SIG_SEM_ADDR_LO 0x2070 4699#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 4700#define mmCP_SIG_SEM_ADDR_HI 0x2071 4701#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 4702#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 4703#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 4704#define mmCP_WAIT_SEM_ADDR_LO 0x2075 4705#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 4706#define mmCP_WAIT_SEM_ADDR_HI 0x2076 4707#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 4708#define mmCP_DMA_PFP_CONTROL 0x2077 4709#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 4710#define mmCP_DMA_ME_CONTROL 0x2078 4711#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 4712#define mmCP_COHER_BASE_HI 0x2079 4713#define mmCP_COHER_BASE_HI_BASE_IDX 1 4714#define mmCP_COHER_START_DELAY 0x207b 4715#define mmCP_COHER_START_DELAY_BASE_IDX 1 4716#define mmCP_COHER_CNTL 0x207c 4717#define mmCP_COHER_CNTL_BASE_IDX 1 4718#define mmCP_COHER_SIZE 0x207d 4719#define mmCP_COHER_SIZE_BASE_IDX 1 4720#define mmCP_COHER_BASE 0x207e 4721#define mmCP_COHER_BASE_BASE_IDX 1 4722#define mmCP_COHER_STATUS 0x207f 4723#define mmCP_COHER_STATUS_BASE_IDX 1 4724#define mmCP_DMA_ME_SRC_ADDR 0x2080 4725#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 4726#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 4727#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 4728#define mmCP_DMA_ME_DST_ADDR 0x2082 4729#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 4730#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 4731#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 4732#define mmCP_DMA_ME_COMMAND 0x2084 4733#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 4734#define mmCP_DMA_PFP_SRC_ADDR 0x2085 4735#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 4736#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 4737#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 4738#define mmCP_DMA_PFP_DST_ADDR 0x2087 4739#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 4740#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 4741#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 4742#define mmCP_DMA_PFP_COMMAND 0x2089 4743#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 4744#define mmCP_DMA_CNTL 0x208a 4745#define mmCP_DMA_CNTL_BASE_IDX 1 4746#define mmCP_DMA_READ_TAGS 0x208b 4747#define mmCP_DMA_READ_TAGS_BASE_IDX 1 4748#define mmCP_COHER_SIZE_HI 0x208c 4749#define mmCP_COHER_SIZE_HI_BASE_IDX 1 4750#define mmCP_PFP_IB_CONTROL 0x208d 4751#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 4752#define mmCP_PFP_LOAD_CONTROL 0x208e 4753#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 4754#define mmCP_SCRATCH_INDEX 0x208f 4755#define mmCP_SCRATCH_INDEX_BASE_IDX 1 4756#define mmCP_SCRATCH_DATA 0x2090 4757#define mmCP_SCRATCH_DATA_BASE_IDX 1 4758#define mmCP_RB_OFFSET 0x2091 4759#define mmCP_RB_OFFSET_BASE_IDX 1 4760#define mmCP_IB1_OFFSET 0x2092 4761#define mmCP_IB1_OFFSET_BASE_IDX 1 4762#define mmCP_IB2_OFFSET 0x2093 4763#define mmCP_IB2_OFFSET_BASE_IDX 1 4764#define mmCP_IB1_PREAMBLE_BEGIN 0x2094 4765#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 4766#define mmCP_IB1_PREAMBLE_END 0x2095 4767#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1 4768#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 4769#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 4770#define mmCP_IB2_PREAMBLE_END 0x2097 4771#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 4772#define mmCP_CE_IB1_OFFSET 0x2098 4773#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 4774#define mmCP_CE_IB2_OFFSET 0x2099 4775#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 4776#define mmCP_CE_COUNTER 0x209a 4777#define mmCP_CE_COUNTER_BASE_IDX 1 4778#define mmCP_CE_RB_OFFSET 0x209b 4779#define mmCP_CE_RB_OFFSET_BASE_IDX 1 4780#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd 4781#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 4782#define mmCP_CE_IB1_CMD_BUFSZ 0x20be 4783#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 4784#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf 4785#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 4786#define mmCP_IB1_CMD_BUFSZ 0x20c0 4787#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 4788#define mmCP_IB2_CMD_BUFSZ 0x20c1 4789#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 4790#define mmCP_ST_CMD_BUFSZ 0x20c2 4791#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 4792#define mmCP_CE_INIT_BASE_LO 0x20c3 4793#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 4794#define mmCP_CE_INIT_BASE_HI 0x20c4 4795#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 4796#define mmCP_CE_INIT_BUFSZ 0x20c5 4797#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 4798#define mmCP_CE_IB1_BASE_LO 0x20c6 4799#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 4800#define mmCP_CE_IB1_BASE_HI 0x20c7 4801#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 4802#define mmCP_CE_IB1_BUFSZ 0x20c8 4803#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 4804#define mmCP_CE_IB2_BASE_LO 0x20c9 4805#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 4806#define mmCP_CE_IB2_BASE_HI 0x20ca 4807#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 4808#define mmCP_CE_IB2_BUFSZ 0x20cb 4809#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 4810#define mmCP_IB1_BASE_LO 0x20cc 4811#define mmCP_IB1_BASE_LO_BASE_IDX 1 4812#define mmCP_IB1_BASE_HI 0x20cd 4813#define mmCP_IB1_BASE_HI_BASE_IDX 1 4814#define mmCP_IB1_BUFSZ 0x20ce 4815#define mmCP_IB1_BUFSZ_BASE_IDX 1 4816#define mmCP_IB2_BASE_LO 0x20cf 4817#define mmCP_IB2_BASE_LO_BASE_IDX 1 4818#define mmCP_IB2_BASE_HI 0x20d0 4819#define mmCP_IB2_BASE_HI_BASE_IDX 1 4820#define mmCP_IB2_BUFSZ 0x20d1 4821#define mmCP_IB2_BUFSZ_BASE_IDX 1 4822#define mmCP_ST_BASE_LO 0x20d2 4823#define mmCP_ST_BASE_LO_BASE_IDX 1 4824#define mmCP_ST_BASE_HI 0x20d3 4825#define mmCP_ST_BASE_HI_BASE_IDX 1 4826#define mmCP_ST_BUFSZ 0x20d4 4827#define mmCP_ST_BUFSZ_BASE_IDX 1 4828#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 4829#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 4830#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 4831#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 4832#define mmCP_EOP_DONE_CNTX_ID 0x20d7 4833#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 4834#define mmCP_PFP_COMPLETION_STATUS 0x20ec 4835#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 4836#define mmCP_CE_COMPLETION_STATUS 0x20ed 4837#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 4838#define mmCP_PRED_NOT_VISIBLE 0x20ee 4839#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 4840#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 4841#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 4842#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 4843#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 4844#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 4845#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 4846#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 4847#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 4848#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 4849#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 4850#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 4851#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 4852#define mmCP_DISPATCH_INDR_ADDR 0x20f6 4853#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 4854#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 4855#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 4856#define mmCP_INDEX_BASE_ADDR 0x20f8 4857#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 4858#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 4859#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 4860#define mmCP_INDEX_TYPE 0x20fa 4861#define mmCP_INDEX_TYPE_BASE_IDX 1 4862#define mmCP_GDS_BKUP_ADDR 0x20fb 4863#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 4864#define mmCP_GDS_BKUP_ADDR_HI 0x20fc 4865#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 4866#define mmCP_SAMPLE_STATUS 0x20fd 4867#define mmCP_SAMPLE_STATUS_BASE_IDX 1 4868#define mmCP_ME_COHER_CNTL 0x20fe 4869#define mmCP_ME_COHER_CNTL_BASE_IDX 1 4870#define mmCP_ME_COHER_SIZE 0x20ff 4871#define mmCP_ME_COHER_SIZE_BASE_IDX 1 4872#define mmCP_ME_COHER_SIZE_HI 0x2100 4873#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 4874#define mmCP_ME_COHER_BASE 0x2101 4875#define mmCP_ME_COHER_BASE_BASE_IDX 1 4876#define mmCP_ME_COHER_BASE_HI 0x2102 4877#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 4878#define mmCP_ME_COHER_STATUS 0x2103 4879#define mmCP_ME_COHER_STATUS_BASE_IDX 1 4880#define mmRLC_GPM_PERF_COUNT_0 0x2140 4881#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 4882#define mmRLC_GPM_PERF_COUNT_1 0x2141 4883#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 4884#define mmGRBM_GFX_INDEX 0x2200 4885#define mmGRBM_GFX_INDEX_BASE_IDX 1 4886#define mmVGT_GSVS_RING_SIZE 0x2241 4887#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1 4888#define mmVGT_PRIMITIVE_TYPE 0x2242 4889#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 4890#define mmVGT_INDEX_TYPE 0x2243 4891#define mmVGT_INDEX_TYPE_BASE_IDX 1 4892#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 4893#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 4894#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 4895#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 4896#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 4897#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 4898#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 4899#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 4900#define mmVGT_MAX_VTX_INDX 0x2248 4901#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 4902#define mmVGT_MIN_VTX_INDX 0x2249 4903#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 4904#define mmVGT_INDX_OFFSET 0x224a 4905#define mmVGT_INDX_OFFSET_BASE_IDX 1 4906#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b 4907#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 4908#define mmVGT_NUM_INDICES 0x224c 4909#define mmVGT_NUM_INDICES_BASE_IDX 1 4910#define mmVGT_NUM_INSTANCES 0x224d 4911#define mmVGT_NUM_INSTANCES_BASE_IDX 1 4912#define mmVGT_TF_RING_SIZE 0x224e 4913#define mmVGT_TF_RING_SIZE_BASE_IDX 1 4914#define mmVGT_HS_OFFCHIP_PARAM 0x224f 4915#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 4916#define mmVGT_TF_MEMORY_BASE 0x2250 4917#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1 4918#define mmVGT_TF_MEMORY_BASE_HI 0x2251 4919#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 4920#define mmWD_POS_BUF_BASE 0x2252 4921#define mmWD_POS_BUF_BASE_BASE_IDX 1 4922#define mmWD_POS_BUF_BASE_HI 0x2253 4923#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 4924#define mmWD_CNTL_SB_BUF_BASE 0x2254 4925#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 4926#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 4927#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 4928#define mmWD_INDEX_BUF_BASE 0x2256 4929#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 4930#define mmWD_INDEX_BUF_BASE_HI 0x2257 4931#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 4932#define mmIA_MULTI_VGT_PARAM 0x2258 4933#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 4934#define mmVGT_INSTANCE_BASE_ID 0x225a 4935#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 4936#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 4937#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 4938#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 4939#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 4940#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 4941#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 4942#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 4943#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 4944#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 4945#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 4946#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b 4947#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 4948#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 4949#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 4950#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 4951#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 4952#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 4953#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 4954#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 4955#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 4956#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 4957#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 4958#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 4959#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 4960#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 4961#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 4962#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 4963#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 4964#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 4965#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 4966#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 4967#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 4968#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 4969#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 4970#define mmPA_SC_TRAP_SCREEN_H 0x22b1 4971#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 4972#define mmPA_SC_TRAP_SCREEN_V 0x22b2 4973#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 4974#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 4975#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 4976#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 4977#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 4978#define mmSQ_THREAD_TRACE_BASE 0x2330 4979#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1 4980#define mmSQ_THREAD_TRACE_SIZE 0x2331 4981#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1 4982#define mmSQ_THREAD_TRACE_MASK 0x2332 4983#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1 4984#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333 4985#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 4986#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334 4987#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 4988#define mmSQ_THREAD_TRACE_CTRL 0x2335 4989#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1 4990#define mmSQ_THREAD_TRACE_MODE 0x2336 4991#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1 4992#define mmSQ_THREAD_TRACE_BASE2 0x2337 4993#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1 4994#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 4995#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 4996#define mmSQ_THREAD_TRACE_WPTR 0x2339 4997#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1 4998#define mmSQ_THREAD_TRACE_STATUS 0x233a 4999#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1 5000#define mmSQ_THREAD_TRACE_HIWATER 0x233b
5001#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 5002#define mmSQ_THREAD_TRACE_CNTR 0x233c 5003#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1 5004#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 5005#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 5006#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 5007#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 5008#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 5009#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 5010#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 5011#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 5012#define mmSQC_CACHES 0x2348 5013#define mmSQC_CACHES_BASE_IDX 1 5014#define mmSQC_WRITEBACK 0x2349 5015#define mmSQC_WRITEBACK_BASE_IDX 1 5016#define mmTA_CS_BC_BASE_ADDR 0x2380 5017#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 5018#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 5019#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 5020#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 5021#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 5022#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 5023#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 5024#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 5025#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 5026#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 5027#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 5028#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 5029#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 5030#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 5031#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 5032#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 5033#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 5034#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 5035#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 5036#define mmDB_ZPASS_COUNT_LOW 0x23fe 5037#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 5038#define mmDB_ZPASS_COUNT_HI 0x23ff 5039#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 5040#define mmGDS_RD_ADDR 0x2400 5041#define mmGDS_RD_ADDR_BASE_IDX 1 5042#define mmGDS_RD_DATA 0x2401 5043#define mmGDS_RD_DATA_BASE_IDX 1 5044#define mmGDS_RD_BURST_ADDR 0x2402 5045#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 5046#define mmGDS_RD_BURST_COUNT 0x2403 5047#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 5048#define mmGDS_RD_BURST_DATA 0x2404 5049#define mmGDS_RD_BURST_DATA_BASE_IDX 1 5050#define mmGDS_WR_ADDR 0x2405 5051#define mmGDS_WR_ADDR_BASE_IDX 1 5052#define mmGDS_WR_DATA 0x2406 5053#define mmGDS_WR_DATA_BASE_IDX 1 5054#define mmGDS_WR_BURST_ADDR 0x2407 5055#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 5056#define mmGDS_WR_BURST_DATA 0x2408 5057#define mmGDS_WR_BURST_DATA_BASE_IDX 1 5058#define mmGDS_WRITE_COMPLETE 0x2409 5059#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 5060#define mmGDS_ATOM_CNTL 0x240a 5061#define mmGDS_ATOM_CNTL_BASE_IDX 1 5062#define mmGDS_ATOM_COMPLETE 0x240b 5063#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 5064#define mmGDS_ATOM_BASE 0x240c 5065#define mmGDS_ATOM_BASE_BASE_IDX 1 5066#define mmGDS_ATOM_SIZE 0x240d 5067#define mmGDS_ATOM_SIZE_BASE_IDX 1 5068#define mmGDS_ATOM_OFFSET0 0x240e 5069#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 5070#define mmGDS_ATOM_OFFSET1 0x240f 5071#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 5072#define mmGDS_ATOM_DST 0x2410 5073#define mmGDS_ATOM_DST_BASE_IDX 1 5074#define mmGDS_ATOM_OP 0x2411 5075#define mmGDS_ATOM_OP_BASE_IDX 1 5076#define mmGDS_ATOM_SRC0 0x2412 5077#define mmGDS_ATOM_SRC0_BASE_IDX 1 5078#define mmGDS_ATOM_SRC0_U 0x2413 5079#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 5080#define mmGDS_ATOM_SRC1 0x2414 5081#define mmGDS_ATOM_SRC1_BASE_IDX 1 5082#define mmGDS_ATOM_SRC1_U 0x2415 5083#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 5084#define mmGDS_ATOM_READ0 0x2416 5085#define mmGDS_ATOM_READ0_BASE_IDX 1 5086#define mmGDS_ATOM_READ0_U 0x2417 5087#define mmGDS_ATOM_READ0_U_BASE_IDX 1 5088#define mmGDS_ATOM_READ1 0x2418 5089#define mmGDS_ATOM_READ1_BASE_IDX 1 5090#define mmGDS_ATOM_READ1_U 0x2419 5091#define mmGDS_ATOM_READ1_U_BASE_IDX 1 5092#define mmGDS_GWS_RESOURCE_CNTL 0x241a 5093#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 5094#define mmGDS_GWS_RESOURCE 0x241b 5095#define mmGDS_GWS_RESOURCE_BASE_IDX 1 5096#define mmGDS_GWS_RESOURCE_CNT 0x241c 5097#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 5098#define mmGDS_OA_CNTL 0x241d 5099#define mmGDS_OA_CNTL_BASE_IDX 1 5100#define mmGDS_OA_COUNTER 0x241e 5101#define mmGDS_OA_COUNTER_BASE_IDX 1 5102#define mmGDS_OA_ADDRESS 0x241f 5103#define mmGDS_OA_ADDRESS_BASE_IDX 1 5104#define mmGDS_OA_INCDEC 0x2420 5105#define mmGDS_OA_INCDEC_BASE_IDX 1 5106#define mmGDS_OA_RING_SIZE 0x2421 5107#define mmGDS_OA_RING_SIZE_BASE_IDX 1 5108#define mmSPI_CONFIG_CNTL 0x2440 5109#define mmSPI_CONFIG_CNTL_BASE_IDX 1 5110#define mmSPI_CONFIG_CNTL_1 0x2441 5111#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1 5112#define mmSPI_CONFIG_CNTL_2 0x2442 5113#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1 5114 5115 5116// addressBlock: gc_perfddec 5117// base address: 0x34000 5118#define mmCPG_PERFCOUNTER1_LO 0x3000 5119#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 5120#define mmCPG_PERFCOUNTER1_HI 0x3001 5121#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 5122#define mmCPG_PERFCOUNTER0_LO 0x3002 5123#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 5124#define mmCPG_PERFCOUNTER0_HI 0x3003 5125#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 5126#define mmCPC_PERFCOUNTER1_LO 0x3004 5127#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 5128#define mmCPC_PERFCOUNTER1_HI 0x3005 5129#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 5130#define mmCPC_PERFCOUNTER0_LO 0x3006 5131#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 5132#define mmCPC_PERFCOUNTER0_HI 0x3007 5133#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 5134#define mmCPF_PERFCOUNTER1_LO 0x3008 5135#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 5136#define mmCPF_PERFCOUNTER1_HI 0x3009 5137#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 5138#define mmCPF_PERFCOUNTER0_LO 0x300a 5139#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 5140#define mmCPF_PERFCOUNTER0_HI 0x300b 5141#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 5142#define mmCPF_LATENCY_STATS_DATA 0x300c 5143#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 5144#define mmCPG_LATENCY_STATS_DATA 0x300d 5145#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 5146#define mmCPC_LATENCY_STATS_DATA 0x300e 5147#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 5148#define mmGRBM_PERFCOUNTER0_LO 0x3040 5149#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 5150#define mmGRBM_PERFCOUNTER0_HI 0x3041 5151#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 5152#define mmGRBM_PERFCOUNTER1_LO 0x3043 5153#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 5154#define mmGRBM_PERFCOUNTER1_HI 0x3044 5155#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 5156#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 5157#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 5158#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 5159#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 5160#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 5161#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 5162#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 5163#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 5164#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 5165#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 5166#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a 5167#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 5168#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b 5169#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 5170#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c 5171#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 5172#define mmWD_PERFCOUNTER0_LO 0x3080 5173#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1 5174#define mmWD_PERFCOUNTER0_HI 0x3081 5175#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1 5176#define mmWD_PERFCOUNTER1_LO 0x3082 5177#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1 5178#define mmWD_PERFCOUNTER1_HI 0x3083 5179#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1 5180#define mmWD_PERFCOUNTER2_LO 0x3084 5181#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1 5182#define mmWD_PERFCOUNTER2_HI 0x3085 5183#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1 5184#define mmWD_PERFCOUNTER3_LO 0x3086 5185#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1 5186#define mmWD_PERFCOUNTER3_HI 0x3087 5187#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1 5188#define mmIA_PERFCOUNTER0_LO 0x3088 5189#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1 5190#define mmIA_PERFCOUNTER0_HI 0x3089 5191#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1 5192#define mmIA_PERFCOUNTER1_LO 0x308a 5193#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1 5194#define mmIA_PERFCOUNTER1_HI 0x308b 5195#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1 5196#define mmIA_PERFCOUNTER2_LO 0x308c 5197#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1 5198#define mmIA_PERFCOUNTER2_HI 0x308d 5199#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1 5200#define mmIA_PERFCOUNTER3_LO 0x308e 5201#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1 5202#define mmIA_PERFCOUNTER3_HI 0x308f 5203#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1 5204#define mmVGT_PERFCOUNTER0_LO 0x3090 5205#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1 5206#define mmVGT_PERFCOUNTER0_HI 0x3091 5207#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1 5208#define mmVGT_PERFCOUNTER1_LO 0x3092 5209#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1 5210#define mmVGT_PERFCOUNTER1_HI 0x3093 5211#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1 5212#define mmVGT_PERFCOUNTER2_LO 0x3094 5213#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1 5214#define mmVGT_PERFCOUNTER2_HI 0x3095 5215#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1 5216#define mmVGT_PERFCOUNTER3_LO 0x3096 5217#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1 5218#define mmVGT_PERFCOUNTER3_HI 0x3097 5219#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1 5220#define mmPA_SU_PERFCOUNTER0_LO 0x3100 5221#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 5222#define mmPA_SU_PERFCOUNTER0_HI 0x3101 5223#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 5224#define mmPA_SU_PERFCOUNTER1_LO 0x3102 5225#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 5226#define mmPA_SU_PERFCOUNTER1_HI 0x3103 5227#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 5228#define mmPA_SU_PERFCOUNTER2_LO 0x3104 5229#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 5230#define mmPA_SU_PERFCOUNTER2_HI 0x3105 5231#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 5232#define mmPA_SU_PERFCOUNTER3_LO 0x3106 5233#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 5234#define mmPA_SU_PERFCOUNTER3_HI 0x3107 5235#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 5236#define mmPA_SC_PERFCOUNTER0_LO 0x3140 5237#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 5238#define mmPA_SC_PERFCOUNTER0_HI 0x3141 5239#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 5240#define mmPA_SC_PERFCOUNTER1_LO 0x3142 5241#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 5242#define mmPA_SC_PERFCOUNTER1_HI 0x3143 5243#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 5244#define mmPA_SC_PERFCOUNTER2_LO 0x3144 5245#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 5246#define mmPA_SC_PERFCOUNTER2_HI 0x3145 5247#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 5248#define mmPA_SC_PERFCOUNTER3_LO 0x3146 5249#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 5250#define mmPA_SC_PERFCOUNTER3_HI 0x3147 5251#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 5252#define mmPA_SC_PERFCOUNTER4_LO 0x3148 5253#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 5254#define mmPA_SC_PERFCOUNTER4_HI 0x3149 5255#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 5256#define mmPA_SC_PERFCOUNTER5_LO 0x314a 5257#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 5258#define mmPA_SC_PERFCOUNTER5_HI 0x314b 5259#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 5260#define mmPA_SC_PERFCOUNTER6_LO 0x314c 5261#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 5262#define mmPA_SC_PERFCOUNTER6_HI 0x314d 5263#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 5264#define mmPA_SC_PERFCOUNTER7_LO 0x314e 5265#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 5266#define mmPA_SC_PERFCOUNTER7_HI 0x314f 5267#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 5268#define mmSPI_PERFCOUNTER0_HI 0x3180 5269#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 5270#define mmSPI_PERFCOUNTER0_LO 0x3181 5271#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 5272#define mmSPI_PERFCOUNTER1_HI 0x3182 5273#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 5274#define mmSPI_PERFCOUNTER1_LO 0x3183 5275#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 5276#define mmSPI_PERFCOUNTER2_HI 0x3184 5277#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 5278#define mmSPI_PERFCOUNTER2_LO 0x3185 5279#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 5280#define mmSPI_PERFCOUNTER3_HI 0x3186 5281#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 5282#define mmSPI_PERFCOUNTER3_LO 0x3187 5283#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 5284#define mmSPI_PERFCOUNTER4_HI 0x3188 5285#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 5286#define mmSPI_PERFCOUNTER4_LO 0x3189 5287#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 5288#define mmSPI_PERFCOUNTER5_HI 0x318a 5289#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 5290#define mmSPI_PERFCOUNTER5_LO 0x318b 5291#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 5292#define mmSQ_PERFCOUNTER0_LO 0x31c0 5293#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 5294#define mmSQ_PERFCOUNTER0_HI 0x31c1 5295#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 5296#define mmSQ_PERFCOUNTER1_LO 0x31c2 5297#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 5298#define mmSQ_PERFCOUNTER1_HI 0x31c3 5299#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 5300#define mmSQ_PERFCOUNTER2_LO 0x31c4 5301#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 5302#define mmSQ_PERFCOUNTER2_HI 0x31c5 5303#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 5304#define mmSQ_PERFCOUNTER3_LO 0x31c6 5305#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 5306#define mmSQ_PERFCOUNTER3_HI 0x31c7 5307#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 5308#define mmSQ_PERFCOUNTER4_LO 0x31c8 5309#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 5310#define mmSQ_PERFCOUNTER4_HI 0x31c9 5311#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 5312#define mmSQ_PERFCOUNTER5_LO 0x31ca 5313#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 5314#define mmSQ_PERFCOUNTER5_HI 0x31cb 5315#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 5316#define mmSQ_PERFCOUNTER6_LO 0x31cc 5317#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 5318#define mmSQ_PERFCOUNTER6_HI 0x31cd 5319#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 5320#define mmSQ_PERFCOUNTER7_LO 0x31ce 5321#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 5322#define mmSQ_PERFCOUNTER7_HI 0x31cf 5323#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 5324#define mmSQ_PERFCOUNTER8_LO 0x31d0 5325#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 5326#define mmSQ_PERFCOUNTER8_HI 0x31d1 5327#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 5328#define mmSQ_PERFCOUNTER9_LO 0x31d2 5329#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 5330#define mmSQ_PERFCOUNTER9_HI 0x31d3 5331#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 5332#define mmSQ_PERFCOUNTER10_LO 0x31d4 5333#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 5334#define mmSQ_PERFCOUNTER10_HI 0x31d5 5335#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 5336#define mmSQ_PERFCOUNTER11_LO 0x31d6 5337#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 5338#define mmSQ_PERFCOUNTER11_HI 0x31d7 5339#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 5340#define mmSQ_PERFCOUNTER12_LO 0x31d8 5341#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 5342#define mmSQ_PERFCOUNTER12_HI 0x31d9 5343#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 5344#define mmSQ_PERFCOUNTER13_LO 0x31da 5345#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 5346#define mmSQ_PERFCOUNTER13_HI 0x31db 5347#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 5348#define mmSQ_PERFCOUNTER14_LO 0x31dc 5349#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 5350#define mmSQ_PERFCOUNTER14_HI 0x31dd 5351#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 5352#define mmSQ_PERFCOUNTER15_LO 0x31de 5353#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 5354#define mmSQ_PERFCOUNTER15_HI 0x31df 5355#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 5356#define mmSX_PERFCOUNTER0_LO 0x3240 5357#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 5358#define mmSX_PERFCOUNTER0_HI 0x3241 5359#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 5360#define mmSX_PERFCOUNTER1_LO 0x3242 5361#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 5362#define mmSX_PERFCOUNTER1_HI 0x3243 5363#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 5364#define mmSX_PERFCOUNTER2_LO 0x3244 5365#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 5366#define mmSX_PERFCOUNTER2_HI 0x3245 5367#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 5368#define mmSX_PERFCOUNTER3_LO 0x3246 5369#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 5370#define mmSX_PERFCOUNTER3_HI 0x3247 5371#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 5372#define mmGDS_PERFCOUNTER0_LO 0x3280 5373#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 5374#define mmGDS_PERFCOUNTER0_HI 0x3281 5375#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 5376#define mmGDS_PERFCOUNTER1_LO 0x3282 5377#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 5378#define mmGDS_PERFCOUNTER1_HI 0x3283 5379#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 5380#define mmGDS_PERFCOUNTER2_LO 0x3284 5381#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 5382#define mmGDS_PERFCOUNTER2_HI 0x3285 5383#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 5384#define mmGDS_PERFCOUNTER3_LO 0x3286 5385#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 5386#define mmGDS_PERFCOUNTER3_HI 0x3287 5387#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 5388#define mmTA_PERFCOUNTER0_LO 0x32c0 5389#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 5390#define mmTA_PERFCOUNTER0_HI 0x32c1 5391#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 5392#define mmTA_PERFCOUNTER1_LO 0x32c2 5393#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 5394#define mmTA_PERFCOUNTER1_HI 0x32c3 5395#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 5396#define mmTD_PERFCOUNTER0_LO 0x3300 5397#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 5398#define mmTD_PERFCOUNTER0_HI 0x3301 5399#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 5400#define mmTD_PERFCOUNTER1_LO 0x3302 5401#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 5402#define mmTD_PERFCOUNTER1_HI 0x3303 5403#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 5404#define mmTCP_PERFCOUNTER0_LO 0x3340 5405#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 5406#define mmTCP_PERFCOUNTER0_HI 0x3341 5407#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 5408#define mmTCP_PERFCOUNTER1_LO 0x3342 5409#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 5410#define mmTCP_PERFCOUNTER1_HI 0x3343 5411#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 5412#define mmTCP_PERFCOUNTER2_LO 0x3344 5413#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 5414#define mmTCP_PERFCOUNTER2_HI 0x3345 5415#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 5416#define mmTCP_PERFCOUNTER3_LO 0x3346 5417#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 5418#define mmTCP_PERFCOUNTER3_HI 0x3347 5419#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 5420#define mmTCC_PERFCOUNTER0_LO 0x3380 5421#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1 5422#define mmTCC_PERFCOUNTER0_HI 0x3381 5423#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1 5424#define mmTCC_PERFCOUNTER1_LO 0x3382 5425#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1 5426#define mmTCC_PERFCOUNTER1_HI 0x3383 5427#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1 5428#define mmTCC_PERFCOUNTER2_LO 0x3384 5429#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1 5430#define mmTCC_PERFCOUNTER2_HI 0x3385 5431#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1 5432#define mmTCC_PERFCOUNTER3_LO 0x3386 5433#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1 5434#define mmTCC_PERFCOUNTER3_HI 0x3387 5435#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1 5436#define mmTCA_PERFCOUNTER0_LO 0x3390 5437#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1 5438#define mmTCA_PERFCOUNTER0_HI 0x3391 5439#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1 5440#define mmTCA_PERFCOUNTER1_LO 0x3392 5441#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1 5442#define mmTCA_PERFCOUNTER1_HI 0x3393 5443#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1 5444#define mmTCA_PERFCOUNTER2_LO 0x3394 5445#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1 5446#define mmTCA_PERFCOUNTER2_HI 0x3395 5447#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1 5448#define mmTCA_PERFCOUNTER3_LO 0x3396 5449#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1 5450#define mmTCA_PERFCOUNTER3_HI 0x3397 5451#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1 5452#define mmCB_PERFCOUNTER0_LO 0x3406 5453#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 5454#define mmCB_PERFCOUNTER0_HI 0x3407 5455#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 5456#define mmCB_PERFCOUNTER1_LO 0x3408 5457#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 5458#define mmCB_PERFCOUNTER1_HI 0x3409 5459#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 5460#define mmCB_PERFCOUNTER2_LO 0x340a 5461#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 5462#define mmCB_PERFCOUNTER2_HI 0x340b 5463#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 5464#define mmCB_PERFCOUNTER3_LO 0x340c 5465#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 5466#define mmCB_PERFCOUNTER3_HI 0x340d 5467#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 5468#define mmDB_PERFCOUNTER0_LO 0x3440 5469#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 5470#define mmDB_PERFCOUNTER0_HI 0x3441 5471#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 5472#define mmDB_PERFCOUNTER1_LO 0x3442 5473#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 5474#define mmDB_PERFCOUNTER1_HI 0x3443 5475#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 5476#define mmDB_PERFCOUNTER2_LO 0x3444 5477#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 5478#define mmDB_PERFCOUNTER2_HI 0x3445 5479#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 5480#define mmDB_PERFCOUNTER3_LO 0x3446 5481#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 5482#define mmDB_PERFCOUNTER3_HI 0x3447 5483#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 5484#define mmRLC_PERFCOUNTER0_LO 0x3480 5485#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 5486#define mmRLC_PERFCOUNTER0_HI 0x3481 5487#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 5488#define mmRLC_PERFCOUNTER1_LO 0x3482 5489#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 5490#define mmRLC_PERFCOUNTER1_HI 0x3483 5491#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 5492#define mmRMI_PERFCOUNTER0_LO 0x34c0 5493#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 5494#define mmRMI_PERFCOUNTER0_HI 0x34c1 5495#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 5496#define mmRMI_PERFCOUNTER1_LO 0x34c2 5497#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 5498#define mmRMI_PERFCOUNTER1_HI 0x34c3 5499#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 5500#define mmRMI_PERFCOUNTER2_LO 0x34c4 5501#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 5502#define mmRMI_PERFCOUNTER2_HI 0x34c5 5503#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 5504#define mmRMI_PERFCOUNTER3_LO 0x34c6 5505#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 5506#define mmRMI_PERFCOUNTER3_HI 0x34c7 5507#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 5508 5509 5510// addressBlock: gc_utcl2_atcl2pfcntrdec 5511// base address: 0x35400 5512#define mmATC_L2_PERFCOUNTER_LO 0x3500 5513#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1 5514#define mmATC_L2_PERFCOUNTER_HI 0x3501 5515#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1 5516 5517 5518// addressBlock: gc_utcl2_vml2prdec 5519// base address: 0x35420 5520#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508 5521#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 5522#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509 5523#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 5524 5525 5526// addressBlock: gc_perfsdec 5527// base address: 0x36000 5528#define mmCPG_PERFCOUNTER1_SELECT 0x3800 5529#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 5530#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 5531#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 5532#define mmCPG_PERFCOUNTER0_SELECT 0x3802 5533#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 5534#define mmCPC_PERFCOUNTER1_SELECT 0x3803 5535#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 5536#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 5537#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5538#define mmCPF_PERFCOUNTER1_SELECT 0x3805 5539#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 5540#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 5541#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 5542#define mmCPF_PERFCOUNTER0_SELECT 0x3807 5543#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 5544#define mmCP_PERFMON_CNTL 0x3808 5545#define mmCP_PERFMON_CNTL_BASE_IDX 1 5546#define mmCPC_PERFCOUNTER0_SELECT 0x3809 5547#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 5548#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 5549#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5550#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 5551#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5552#define mmCPF_LATENCY_STATS_SELECT 0x380c 5553#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 5554#define mmCPG_LATENCY_STATS_SELECT 0x380d 5555#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 5556#define mmCPC_LATENCY_STATS_SELECT 0x380e 5557#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 5558#define mmCP_DRAW_OBJECT 0x3810 5559#define mmCP_DRAW_OBJECT_BASE_IDX 1 5560#define mmCP_DRAW_OBJECT_COUNTER 0x3811 5561#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 5562#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 5563#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 5564#define mmCP_DRAW_WINDOW_HI 0x3813 5565#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 5566#define mmCP_DRAW_WINDOW_LO 0x3814 5567#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 5568#define mmCP_DRAW_WINDOW_CNTL 0x3815 5569#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 5570#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 5571#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 5572#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 5573#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 5574#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 5575#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 5576#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 5577#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 5578#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 5579#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 5580#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 5581#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 5582#define mmWD_PERFCOUNTER0_SELECT 0x3880 5583#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1 5584#define mmWD_PERFCOUNTER1_SELECT 0x3881 5585#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1 5586#define mmWD_PERFCOUNTER2_SELECT 0x3882 5587#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1 5588#define mmWD_PERFCOUNTER3_SELECT 0x3883 5589#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1 5590#define mmIA_PERFCOUNTER0_SELECT 0x3884 5591#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1 5592#define mmIA_PERFCOUNTER1_SELECT 0x3885 5593#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1 5594#define mmIA_PERFCOUNTER2_SELECT 0x3886 5595#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1 5596#define mmIA_PERFCOUNTER3_SELECT 0x3887 5597#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1 5598#define mmIA_PERFCOUNTER0_SELECT1 0x3888 5599#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5600#define mmVGT_PERFCOUNTER0_SELECT 0x388c 5601#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 5602#define mmVGT_PERFCOUNTER1_SELECT 0x388d 5603#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 5604#define mmVGT_PERFCOUNTER2_SELECT 0x388e 5605#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 5606#define mmVGT_PERFCOUNTER3_SELECT 0x388f 5607#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 5608#define mmVGT_PERFCOUNTER0_SELECT1 0x3890 5609#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 5610#define mmVGT_PERFCOUNTER1_SELECT1 0x3891 5611#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 5612#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894 5613#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 5614#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 5615#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 5616#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 5617#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 5618#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 5619#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 5620#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 5621#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 5622#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 5623#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 5624#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905 5625#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 5626#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 5627#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 5628#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 5629#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5630#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 5631#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 5632#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 5633#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 5634#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 5635#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 5636#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 5637#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 5638#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 5639#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 5640#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 5641#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 5642#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 5643#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 5644#define mmSPI_PERFCOUNTER0_SELECT 0x3980 5645#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 5646#define mmSPI_PERFCOUNTER1_SELECT 0x3981 5647#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 5648#define mmSPI_PERFCOUNTER2_SELECT 0x3982 5649#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 5650#define mmSPI_PERFCOUNTER3_SELECT 0x3983 5651#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 5652#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 5653#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 5654#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 5655#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 5656#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 5657#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 5658#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 5659#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 5660#define mmSPI_PERFCOUNTER4_SELECT 0x3988 5661#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 5662#define mmSPI_PERFCOUNTER5_SELECT 0x3989 5663#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 5664#define mmSPI_PERFCOUNTER_BINS 0x398a 5665#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 5666#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 5667#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 5668#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 5669#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 5670#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 5671#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 5672#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 5673#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 5674#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 5675#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 5676#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 5677#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 5678#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 5679#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 5680#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 5681#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 5682#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 5683#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 5684#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 5685#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 5686#define mmSQ_PERFCOUNTER10_SELECT 0x39ca 5687#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 5688#define mmSQ_PERFCOUNTER11_SELECT 0x39cb 5689#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 5690#define mmSQ_PERFCOUNTER12_SELECT 0x39cc 5691#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 5692#define mmSQ_PERFCOUNTER13_SELECT 0x39cd 5693#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 5694#define mmSQ_PERFCOUNTER14_SELECT 0x39ce 5695#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 5696#define mmSQ_PERFCOUNTER15_SELECT 0x39cf 5697#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 5698#define mmSQ_PERFCOUNTER_CTRL 0x39e0 5699#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 5700#define mmSQ_PERFCOUNTER_MASK 0x39e1 5701#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1 5702#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 5703#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 5704#define mmSX_PERFCOUNTER0_SELECT 0x3a40 5705#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 5706#define mmSX_PERFCOUNTER1_SELECT 0x3a41 5707#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 5708#define mmSX_PERFCOUNTER2_SELECT 0x3a42 5709#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 5710#define mmSX_PERFCOUNTER3_SELECT 0x3a43 5711#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 5712#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 5713#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 5714#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 5715#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 5716#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 5717#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 5718#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 5719#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 5720#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 5721#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 5722#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 5723#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 5724#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 5725#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 5726#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 5727#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 5728#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 5729#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5730#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 5731#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 5732#define mmTD_PERFCOUNTER0_SELECT 0x3b00 5733#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 5734#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 5735#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 5736#define mmTD_PERFCOUNTER1_SELECT 0x3b02 5737#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 5738#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 5739#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 5740#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 5741#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 5742#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 5743#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 5744#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 5745#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 5746#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 5747#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 5748#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 5749#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 5750#define mmTCC_PERFCOUNTER0_SELECT 0x3b80 5751#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 5752#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81 5753#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5754#define mmTCC_PERFCOUNTER1_SELECT 0x3b82 5755#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 5756#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83 5757#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 5758#define mmTCC_PERFCOUNTER2_SELECT 0x3b84 5759#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 5760#define mmTCC_PERFCOUNTER3_SELECT 0x3b85 5761#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 5762#define mmTCA_PERFCOUNTER0_SELECT 0x3b90 5763#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 5764#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91 5765#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5766#define mmTCA_PERFCOUNTER1_SELECT 0x3b92 5767#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 5768#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93 5769#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 5770#define mmTCA_PERFCOUNTER2_SELECT 0x3b94 5771#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 5772#define mmTCA_PERFCOUNTER3_SELECT 0x3b95 5773#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 5774#define mmCB_PERFCOUNTER_FILTER 0x3c00 5775#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 5776#define mmCB_PERFCOUNTER0_SELECT 0x3c01 5777#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 5778#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 5779#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 5780#define mmCB_PERFCOUNTER1_SELECT 0x3c03 5781#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 5782#define mmCB_PERFCOUNTER2_SELECT 0x3c04 5783#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 5784#define mmCB_PERFCOUNTER3_SELECT 0x3c05 5785#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 5786#define mmDB_PERFCOUNTER0_SELECT 0x3c40 5787#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 5788#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 5789#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 5790#define mmDB_PERFCOUNTER1_SELECT 0x3c42 5791#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 5792#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 5793#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 5794#define mmDB_PERFCOUNTER2_SELECT 0x3c44 5795#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 5796#define mmDB_PERFCOUNTER3_SELECT 0x3c46 5797#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 5798#define mmRLC_SPM_PERFMON_CNTL 0x3c80 5799#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 5800#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 5801#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 5802#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 5803#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 5804#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 5805#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 5806#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 5807#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 5808#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85 5809#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 5810#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86 5811#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 5812#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 5813#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5814#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 5815#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5816#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 5817#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5818#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a 5819#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5820#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b 5821#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5822#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c 5823#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5824#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d 5825#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5826#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e 5827#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5828#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 5829#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5830#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 5831#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5832#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 5833#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5834#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 5835#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5836#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 5837#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5838#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 5839#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5840#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 5841#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5842#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 5843#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5844#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 5845#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5846#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a 5847#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5848#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b 5849#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 5850#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c 5851#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 5852#define mmRLC_SPM_RING_RDPTR 0x3c9d 5853#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 5854#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e 5855#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 5856#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0x3c9f 5857#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5858#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0x3ca0 5859#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5860#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0x3ca1 5861#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5862#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0x3ca2 5863#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5864#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 5865#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 5866#define mmRLC_PERFMON_CLK_CNTL 0x3cbf 5867#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 5868#define mmRLC_PERFMON_CNTL 0x3cc0 5869#define mmRLC_PERFMON_CNTL_BASE_IDX 1 5870#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 5871#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 5872#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 5873#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 5874#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 5875#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 5876#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 5877#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 5878#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 5879#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 5880#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 5881#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 5882#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 5883#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 5884#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 5885#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 5886#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 5887#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 5888#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 5889#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 5890#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 5891#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 5892#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 5893#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 5894#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 5895#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 5896#define mmRMI_PERF_COUNTER_CNTL 0x3d06 5897#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 5898 5899 5900// addressBlock: gc_utcl2_atcl2pfcntldec 5901// base address: 0x37500 5902#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40 5903#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 5904#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41 5905#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 5906#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 5907#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 5908 5909 5910// addressBlock: gc_utcl2_vml2pldec 5911// base address: 0x37530 5912#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c 5913#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 5914#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d 5915#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 5916#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e 5917#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 5918#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f 5919#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 5920#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 5921#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 5922#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 5923#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 5924#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 5925#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 5926#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 5927#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 5928#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 5929#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 5930 5931 5932// addressBlock: gc_rlcpdec 5933// base address: 0x3b000 5934#define mmRLC_CNTL 0x4c00 5935#define mmRLC_CNTL_BASE_IDX 1 5936#define mmRLC_STAT 0x4c04 5937#define mmRLC_STAT_BASE_IDX 1 5938#define mmRLC_SAFE_MODE 0x4c05 5939#define mmRLC_SAFE_MODE_BASE_IDX 1 5940#define mmRLC_MEM_SLP_CNTL 0x4c06 5941#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 5942#define mmSMU_RLC_RESPONSE 0x4c07 5943#define mmSMU_RLC_RESPONSE_BASE_IDX 1 5944#define mmRLC_RLCV_SAFE_MODE 0x4c08 5945#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 5946#define mmRLC_SMU_SAFE_MODE 0x4c09 5947#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 5948#define mmRLC_RLCV_COMMAND 0x4c0a 5949#define mmRLC_RLCV_COMMAND_BASE_IDX 1 5950#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 5951#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 5952#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 5953#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 5954#define mmRLC_GPM_TIMER_INT_0 0x4c0e 5955#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 5956#define mmRLC_GPM_TIMER_INT_1 0x4c0f 5957#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 5958#define mmRLC_GPM_TIMER_INT_2 0x4c10 5959#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 5960#define mmRLC_GPM_TIMER_CTRL 0x4c11 5961#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 5962#define mmRLC_LB_CNTR_MAX 0x4c12 5963#define mmRLC_LB_CNTR_MAX_BASE_IDX 1 5964#define mmRLC_GPM_TIMER_STAT 0x4c13 5965#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 5966#define mmRLC_GPM_TIMER_INT_3 0x4c15 5967#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 5968#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 5969#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 5970#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 5971#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 5972#define mmRLC_INT_STAT 0x4c18 5973#define mmRLC_INT_STAT_BASE_IDX 1 5974#define mmRLC_LB_CNTL 0x4c19 5975#define mmRLC_LB_CNTL_BASE_IDX 1 5976#define mmRLC_MGCG_CTRL 0x4c1a 5977#define mmRLC_MGCG_CTRL_BASE_IDX 1 5978#define mmRLC_LB_CNTR_INIT 0x4c1b 5979#define mmRLC_LB_CNTR_INIT_BASE_IDX 1 5980#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c 5981#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 5982#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e 5983#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 5984#define mmRLC_PG_DELAY_2 0x4c1f 5985#define mmRLC_PG_DELAY_2_BASE_IDX 1 5986#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 5987#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 5988#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 5989#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 5990#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 5991#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 5992#define mmRLC_UCODE_CNTL 0x4c27 5993#define mmRLC_UCODE_CNTL_BASE_IDX 1 5994#define mmRLC_GPM_THREAD_RESET 0x4c28 5995#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 5996#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 5997#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 5998#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 5999#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 6000#define mmRLC_FIREWALL_VIOLATION 0x4c2b
6001#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1 6002#define mmRLC_GPM_STAT 0x4c40 6003#define mmRLC_GPM_STAT_BASE_IDX 1 6004#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 6005#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 6006#define mmRLC_GPU_CLOCK_32 0x4c42 6007#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 6008#define mmRLC_PG_CNTL 0x4c43 6009#define mmRLC_PG_CNTL_BASE_IDX 1 6010#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 6011#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 6012#define mmRLC_GPM_THREAD_ENABLE 0x4c45 6013#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 6014#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 6015#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 6016#define mmRLC_CGCG_CGLS_CTRL 0x4c49 6017#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 6018#define mmRLC_CGCG_RAMP_CTRL 0x4c4a 6019#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 6020#define mmRLC_DYN_PG_STATUS 0x4c4b 6021#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 6022#define mmRLC_DYN_PG_REQUEST 0x4c4c 6023#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 6024#define mmRLC_PG_DELAY 0x4c4d 6025#define mmRLC_PG_DELAY_BASE_IDX 1 6026#define mmRLC_CU_STATUS 0x4c4e 6027#define mmRLC_CU_STATUS_BASE_IDX 1 6028#define mmRLC_LB_INIT_CU_MASK 0x4c4f 6029#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1 6030#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 6031#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 6032#define mmRLC_LB_PARAMS 0x4c51 6033#define mmRLC_LB_PARAMS_BASE_IDX 1 6034#define mmRLC_THREAD1_DELAY 0x4c52 6035#define mmRLC_THREAD1_DELAY_BASE_IDX 1 6036#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 6037#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 6038#define mmRLC_MAX_PG_CU 0x4c54 6039#define mmRLC_MAX_PG_CU_BASE_IDX 1 6040#define mmRLC_AUTO_PG_CTRL 0x4c55 6041#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 6042#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 6043#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 6044#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59 6045#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 6046#define mmRLC_SERDES_RD_DATA_0 0x4c5a 6047#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 6048#define mmRLC_SERDES_RD_DATA_1 0x4c5b 6049#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 6050#define mmRLC_SERDES_RD_DATA_2 0x4c5c 6051#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 6052#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d 6053#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 6054#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e 6055#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 6056#define mmRLC_SERDES_WR_CTRL 0x4c5f 6057#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1 6058#define mmRLC_SERDES_WR_DATA 0x4c60 6059#define mmRLC_SERDES_WR_DATA_BASE_IDX 1 6060#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61 6061#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 6062#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 6063#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 6064#define mmRLC_GPM_GENERAL_0 0x4c63 6065#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 6066#define mmRLC_GPM_GENERAL_1 0x4c64 6067#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 6068#define mmRLC_GPM_GENERAL_2 0x4c65 6069#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 6070#define mmRLC_GPM_GENERAL_3 0x4c66 6071#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 6072#define mmRLC_GPM_GENERAL_4 0x4c67 6073#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 6074#define mmRLC_GPM_GENERAL_5 0x4c68 6075#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 6076#define mmRLC_GPM_GENERAL_6 0x4c69 6077#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 6078#define mmRLC_GPM_GENERAL_7 0x4c6a 6079#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 6080#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c 6081#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 6082#define mmRLC_GPM_SCRATCH_DATA 0x4c6d 6083#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 6084#define mmRLC_STATIC_PG_STATUS 0x4c6e 6085#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 6086#define mmRLC_SPM_MC_CNTL 0x4c71 6087#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 6088#define mmRLC_SPM_INT_CNTL 0x4c72 6089#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 6090#define mmRLC_SPM_INT_STATUS 0x4c73 6091#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 6092#define mmRLC_SMU_MESSAGE 0x4c76 6093#define mmRLC_SMU_MESSAGE_BASE_IDX 1 6094#define mmRLC_GPM_LOG_SIZE 0x4c77 6095#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 6096#define mmRLC_PG_DELAY_3 0x4c78 6097#define mmRLC_PG_DELAY_3_BASE_IDX 1 6098#define mmRLC_GPR_REG1 0x4c79 6099#define mmRLC_GPR_REG1_BASE_IDX 1 6100#define mmRLC_GPR_REG2 0x4c7a 6101#define mmRLC_GPR_REG2_BASE_IDX 1 6102#define mmRLC_GPM_LOG_CONT 0x4c7b 6103#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 6104#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c 6105#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 6106#define mmRLC_GPM_INT_DISABLE_TH1 0x4c7d 6107#define mmRLC_GPM_INT_DISABLE_TH1_BASE_IDX 1 6108#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e 6109#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 6110#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f 6111#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 6112#define mmRLC_SRM_CNTL 0x4c80 6113#define mmRLC_SRM_CNTL_BASE_IDX 1 6114#define mmRLC_SRM_ARAM_ADDR 0x4c83 6115#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 6116#define mmRLC_SRM_ARAM_DATA 0x4c84 6117#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 6118#define mmRLC_SRM_DRAM_ADDR 0x4c85 6119#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 6120#define mmRLC_SRM_DRAM_DATA 0x4c86 6121#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 6122#define mmRLC_SRM_GPM_COMMAND 0x4c87 6123#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 6124#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 6125#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 6126#define mmRLC_SRM_RLCV_COMMAND 0x4c89 6127#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 6128#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a 6129#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 6130#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 6131#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 6132#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 6133#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 6134#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 6135#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 6136#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 6137#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 6138#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 6139#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 6140#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 6141#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 6142#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 6143#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 6144#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 6145#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 6146#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 6147#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 6148#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 6149#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 6150#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 6151#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 6152#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 6153#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 6154#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 6155#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 6156#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 6157#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 6158#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 6159#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 6160#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 6161#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 6162#define mmRLC_SRM_STAT 0x4c9b 6163#define mmRLC_SRM_STAT_BASE_IDX 1 6164#define mmRLC_SRM_GPM_ABORT 0x4c9c 6165#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 6166#define mmRLC_CSIB_ADDR_LO 0x4ca2 6167#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 6168#define mmRLC_CSIB_ADDR_HI 0x4ca3 6169#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 6170#define mmRLC_CSIB_LENGTH 0x4ca4 6171#define mmRLC_CSIB_LENGTH_BASE_IDX 1 6172#define mmRLC_SMU_COMMAND 0x4ca9 6173#define mmRLC_SMU_COMMAND_BASE_IDX 1 6174#define mmRLC_CP_SCHEDULERS 0x4caa 6175#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 6176#define mmRLC_SMU_ARGUMENT_1 0x4cab 6177#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 6178#define mmRLC_SMU_ARGUMENT_2 0x4cac 6179#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 6180#define mmRLC_GPM_GENERAL_8 0x4cad 6181#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 6182#define mmRLC_GPM_GENERAL_9 0x4cae 6183#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 6184#define mmRLC_GPM_GENERAL_10 0x4caf 6185#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 6186#define mmRLC_GPM_GENERAL_11 0x4cb0 6187#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 6188#define mmRLC_GPM_GENERAL_12 0x4cb1 6189#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 6190#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 6191#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 6192#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 6193#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 6194#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 6195#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 6196#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 6197#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 6198#define mmRLC_UTCL1_STATUS_2 0x4cb6 6199#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 6200#define mmRLC_LB_THR_CONFIG_2 0x4cb8 6201#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1 6202#define mmRLC_LB_THR_CONFIG_3 0x4cb9 6203#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1 6204#define mmRLC_LB_THR_CONFIG_4 0x4cba 6205#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1 6206#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc 6207#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 6208#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd 6209#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 6210#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 6211#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 6212#define mmRLC_LB_THR_CONFIG_1 0x4cbf 6213#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1 6214#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 6215#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 6216#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 6217#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 6218#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 6219#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 6220#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 6221#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 6222#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 6223#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 6224#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 6225#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 6226#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 6227#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 6228#define mmRLC_SEMAPHORE_0 0x4cc7 6229#define mmRLC_SEMAPHORE_0_BASE_IDX 1 6230#define mmRLC_SEMAPHORE_1 0x4cc8 6231#define mmRLC_SEMAPHORE_1_BASE_IDX 1 6232#define mmRLC_CP_EOF_INT 0x4cca 6233#define mmRLC_CP_EOF_INT_BASE_IDX 1 6234#define mmRLC_CP_EOF_INT_CNT 0x4ccb 6235#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 6236#define mmRLC_SPARE_INT 0x4ccc 6237#define mmRLC_SPARE_INT_BASE_IDX 1 6238#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd 6239#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 6240#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce 6241#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 6242#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf 6243#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 6244#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 6245#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 6246#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 6247#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 6248#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 6249#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 6250#define mmRLC_DSM_TRIG 0x4cd3 6251#define mmRLC_DSM_TRIG_BASE_IDX 1 6252#define mmRLC_UTCL1_STATUS 0x4cd4 6253#define mmRLC_UTCL1_STATUS_BASE_IDX 1 6254#define mmRLC_R2I_CNTL_0 0x4cd5 6255#define mmRLC_R2I_CNTL_0_BASE_IDX 1 6256#define mmRLC_R2I_CNTL_1 0x4cd6 6257#define mmRLC_R2I_CNTL_1_BASE_IDX 1 6258#define mmRLC_R2I_CNTL_2 0x4cd7 6259#define mmRLC_R2I_CNTL_2_BASE_IDX 1 6260#define mmRLC_R2I_CNTL_3 0x4cd8 6261#define mmRLC_R2I_CNTL_3_BASE_IDX 1 6262#define mmRLC_UTCL2_CNTL 0x4cd9 6263#define mmRLC_UTCL2_CNTL_BASE_IDX 1 6264#define mmRLC_LBPW_CU_STAT 0x4cda 6265#define mmRLC_LBPW_CU_STAT_BASE_IDX 1 6266#define mmRLC_DS_CNTL 0x4cdb 6267#define mmRLC_DS_CNTL_BASE_IDX 1 6268#define mmRLC_RLCV_SPARE_INT 0x4f30 6269#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 6270 6271 6272// addressBlock: gc_pwrdec 6273// base address: 0x3c000 6274#define mmCGTS_SM_CTRL_REG 0x5000 6275#define mmCGTS_SM_CTRL_REG_BASE_IDX 1 6276#define mmCGTS_RD_CTRL_REG 0x5001 6277#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 6278#define mmCGTS_RD_REG 0x5002 6279#define mmCGTS_RD_REG_BASE_IDX 1 6280#define mmCGTS_TCC_DISABLE 0x5003 6281#define mmCGTS_TCC_DISABLE_BASE_IDX 1 6282#define mmCGTS_USER_TCC_DISABLE 0x5004 6283#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 6284#define mmCGTS_CU0_SP0_CTRL_REG 0x5008 6285#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 6286#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 6287#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 6288#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a 6289#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 6290#define mmCGTS_CU0_SP1_CTRL_REG 0x500b 6291#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 6292#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c 6293#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 6294#define mmCGTS_CU1_SP0_CTRL_REG 0x500d 6295#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 6296#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e 6297#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 6298#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f 6299#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 6300#define mmCGTS_CU1_SP1_CTRL_REG 0x5010 6301#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 6302#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011 6303#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 6304#define mmCGTS_CU2_SP0_CTRL_REG 0x5012 6305#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 6306#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 6307#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 6308#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014 6309#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 6310#define mmCGTS_CU2_SP1_CTRL_REG 0x5015 6311#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 6312#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016 6313#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 6314#define mmCGTS_CU3_SP0_CTRL_REG 0x5017 6315#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 6316#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 6317#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 6318#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019 6319#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 6320#define mmCGTS_CU3_SP1_CTRL_REG 0x501a 6321#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 6322#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b 6323#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 6324#define mmCGTS_CU4_SP0_CTRL_REG 0x501c 6325#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 6326#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d 6327#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 6328#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e 6329#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 6330#define mmCGTS_CU4_SP1_CTRL_REG 0x501f 6331#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 6332#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020 6333#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 6334#define mmCGTS_CU5_SP0_CTRL_REG 0x5021 6335#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 6336#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 6337#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 6338#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023 6339#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 6340#define mmCGTS_CU5_SP1_CTRL_REG 0x5024 6341#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 6342#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025 6343#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 6344#define mmCGTS_CU6_SP0_CTRL_REG 0x5026 6345#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 6346#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 6347#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 6348#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028 6349#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 6350#define mmCGTS_CU6_SP1_CTRL_REG 0x5029 6351#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 6352#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a 6353#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 6354#define mmCGTS_CU7_SP0_CTRL_REG 0x502b 6355#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 6356#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c 6357#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 6358#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d 6359#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 6360#define mmCGTS_CU7_SP1_CTRL_REG 0x502e 6361#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 6362#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f 6363#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 6364#define mmCGTS_CU8_SP0_CTRL_REG 0x5030 6365#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 6366#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 6367#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 6368#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032 6369#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 6370#define mmCGTS_CU8_SP1_CTRL_REG 0x5033 6371#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 6372#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034 6373#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 6374#define mmCGTS_CU9_SP0_CTRL_REG 0x5035 6375#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 6376#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 6377#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 6378#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037 6379#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 6380#define mmCGTS_CU9_SP1_CTRL_REG 0x5038 6381#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 6382#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039 6383#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 6384#define mmCGTS_CU10_SP0_CTRL_REG 0x503a 6385#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 6386#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b 6387#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 6388#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c 6389#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 6390#define mmCGTS_CU10_SP1_CTRL_REG 0x503d 6391#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 6392#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e 6393#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 6394#define mmCGTS_CU11_SP0_CTRL_REG 0x503f 6395#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 6396#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 6397#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 6398#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041 6399#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 6400#define mmCGTS_CU11_SP1_CTRL_REG 0x5042 6401#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 6402#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043 6403#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 6404#define mmCGTS_CU12_SP0_CTRL_REG 0x5044 6405#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 6406#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 6407#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 6408#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046 6409#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 6410#define mmCGTS_CU12_SP1_CTRL_REG 0x5047 6411#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 6412#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048 6413#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 6414#define mmCGTS_CU13_SP0_CTRL_REG 0x5049 6415#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 6416#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a 6417#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 6418#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b 6419#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 6420#define mmCGTS_CU13_SP1_CTRL_REG 0x504c 6421#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 6422#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d 6423#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 6424#define mmCGTS_CU14_SP0_CTRL_REG 0x504e 6425#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 6426#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f 6427#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 6428#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050 6429#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 6430#define mmCGTS_CU14_SP1_CTRL_REG 0x5051 6431#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 6432#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052 6433#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 6434#define mmCGTS_CU15_SP0_CTRL_REG 0x5053 6435#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 6436#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 6437#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 6438#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055 6439#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 6440#define mmCGTS_CU15_SP1_CTRL_REG 0x5056 6441#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 6442#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057 6443#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 6444#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058 6445#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 6446#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059 6447#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 6448#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a 6449#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 6450#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b 6451#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 6452#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c 6453#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 6454#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d 6455#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 6456#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e 6457#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 6458#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f 6459#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 6460#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060 6461#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 6462#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061 6463#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 6464#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062 6465#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 6466#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063 6467#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 6468#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064 6469#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 6470#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065 6471#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 6472#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066 6473#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 6474#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067 6475#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 6476#define mmCGTT_SPI_CLK_CTRL 0x5080 6477#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 6478#define mmCGTT_PC_CLK_CTRL 0x5081 6479#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 6480#define mmCGTT_BCI_CLK_CTRL 0x5082 6481#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 6482#define mmCGTT_VGT_CLK_CTRL 0x5084 6483#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 6484#define mmCGTT_IA_CLK_CTRL 0x5085 6485#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 6486#define mmCGTT_WD_CLK_CTRL 0x5086 6487#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 6488#define mmCGTT_PA_CLK_CTRL 0x5088 6489#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 6490#define mmCGTT_SC_CLK_CTRL0 0x5089 6491#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 6492#define mmCGTT_SC_CLK_CTRL1 0x508a 6493#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 6494#define mmCGTT_SQ_CLK_CTRL 0x508c 6495#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 6496#define mmCGTT_SQG_CLK_CTRL 0x508d 6497#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 6498#define mmSQ_ALU_CLK_CTRL 0x508e 6499#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 6500#define mmSQ_TEX_CLK_CTRL 0x508f 6501#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 6502#define mmSQ_LDS_CLK_CTRL 0x5090 6503#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 6504#define mmSQ_POWER_THROTTLE 0x5091 6505#define mmSQ_POWER_THROTTLE_BASE_IDX 1 6506#define mmSQ_POWER_THROTTLE2 0x5092 6507#define mmSQ_POWER_THROTTLE2_BASE_IDX 1 6508#define mmCGTT_SX_CLK_CTRL0 0x5094 6509#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 6510#define mmCGTT_SX_CLK_CTRL1 0x5095 6511#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 6512#define mmCGTT_SX_CLK_CTRL2 0x5096 6513#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 6514#define mmCGTT_SX_CLK_CTRL3 0x5097 6515#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 6516#define mmCGTT_SX_CLK_CTRL4 0x5098 6517#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 6518#define mmTD_CGTT_CTRL 0x509c 6519#define mmTD_CGTT_CTRL_BASE_IDX 1 6520#define mmTA_CGTT_CTRL 0x509d 6521#define mmTA_CGTT_CTRL_BASE_IDX 1 6522#define mmCGTT_TCPI_CLK_CTRL 0x509e 6523#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 6524#define mmCGTT_TCI_CLK_CTRL 0x509f 6525#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1 6526#define mmCGTT_GDS_CLK_CTRL 0x50a0 6527#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 6528#define mmDB_CGTT_CLK_CTRL_0 0x50a4 6529#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 6530#define mmCB_CGTT_SCLK_CTRL 0x50a8 6531#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 6532#define mmTCC_CGTT_SCLK_CTRL 0x50ac 6533#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1 6534#define mmTCA_CGTT_SCLK_CTRL 0x50ad 6535#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1 6536#define mmCGTT_CP_CLK_CTRL 0x50b0 6537#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 6538#define mmCGTT_CPF_CLK_CTRL 0x50b1 6539#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 6540#define mmCGTT_CPC_CLK_CTRL 0x50b2 6541#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 6542#define mmCGTT_RLC_CLK_CTRL 0x50b5 6543#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 6544#define mmRLC_GFX_RM_CNTL 0x50b6 6545#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 6546#define mmRMI_CGTT_SCLK_CTRL 0x50c0 6547#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 6548#define mmCGTT_TCPF_CLK_CTRL 0x50c1 6549#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 6550 6551 6552// addressBlock: gc_ea_pwrdec 6553// base address: 0x3c000 6554#define mmGCEA_CGTT_CLK_CTRL 0x50c4 6555#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 6556 6557 6558// addressBlock: gc_utcl2_vmsharedhvdec 6559// base address: 0x3ea00 6560#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 6561#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 6562#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 6563#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 6564#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 6565#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 6566#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 6567#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 6568#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 6569#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 6570#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 6571#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 6572#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 6573#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 6574#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 6575#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 6576#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 6577#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 6578#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 6579#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 6580#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 6581#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 6582#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 6583#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 6584#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 6585#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 6586#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 6587#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 6588#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 6589#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 6590#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 6591#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 6592#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90 6593#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 6594#define mmMC_VM_MARC_BASE_LO_0 0x5a91 6595#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1 6596#define mmMC_VM_MARC_BASE_LO_1 0x5a92 6597#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1 6598#define mmMC_VM_MARC_BASE_LO_2 0x5a93 6599#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1 6600#define mmMC_VM_MARC_BASE_LO_3 0x5a94 6601#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1 6602#define mmMC_VM_MARC_BASE_HI_0 0x5a95 6603#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1 6604#define mmMC_VM_MARC_BASE_HI_1 0x5a96 6605#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1 6606#define mmMC_VM_MARC_BASE_HI_2 0x5a97 6607#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1 6608#define mmMC_VM_MARC_BASE_HI_3 0x5a98 6609#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1 6610#define mmMC_VM_MARC_RELOC_LO_0 0x5a99 6611#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 6612#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a 6613#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 6614#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b 6615#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 6616#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c 6617#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 6618#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d 6619#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 6620#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e 6621#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 6622#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f 6623#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 6624#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0 6625#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 6626#define mmMC_VM_MARC_LEN_LO_0 0x5aa1 6627#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1 6628#define mmMC_VM_MARC_LEN_LO_1 0x5aa2 6629#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1 6630#define mmMC_VM_MARC_LEN_LO_2 0x5aa3 6631#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1 6632#define mmMC_VM_MARC_LEN_LO_3 0x5aa4 6633#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1 6634#define mmMC_VM_MARC_LEN_HI_0 0x5aa5 6635#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1 6636#define mmMC_VM_MARC_LEN_HI_1 0x5aa6 6637#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1 6638#define mmMC_VM_MARC_LEN_HI_2 0x5aa7 6639#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1 6640#define mmMC_VM_MARC_LEN_HI_3 0x5aa8 6641#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1 6642#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9 6643#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 6644#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa 6645#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 6646#define mmVM_PCIE_ATS_CNTL 0x5aab 6647#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1 6648#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac 6649#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 6650#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad 6651#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 6652#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae 6653#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 6654#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf 6655#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 6656#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0 6657#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 6658#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1 6659#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 6660#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2 6661#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 6662#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3 6663#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 6664#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4 6665#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 6666#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5 6667#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 6668#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6 6669#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 6670#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7 6671#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 6672#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8 6673#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 6674#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9 6675#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 6676#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba 6677#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 6678#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb 6679#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 6680#define mmUTCL2_CGTT_CLK_CTRL 0x5abc 6681#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 6682 6683 6684// addressBlock: gc_hypdec 6685// base address: 0x3e000 6686#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 6687#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 6688#define mmCP_PFP_UCODE_ADDR 0x5814 6689#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 6690#define mmCP_HYP_PFP_UCODE_DATA 0x5815 6691#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 6692#define mmCP_PFP_UCODE_DATA 0x5815 6693#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 6694#define mmCP_HYP_ME_UCODE_ADDR 0x5816 6695#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 6696#define mmCP_ME_RAM_RADDR 0x5816 6697#define mmCP_ME_RAM_RADDR_BASE_IDX 1 6698#define mmCP_ME_RAM_WADDR 0x5816 6699#define mmCP_ME_RAM_WADDR_BASE_IDX 1 6700#define mmCP_HYP_ME_UCODE_DATA 0x5817 6701#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 6702#define mmCP_ME_RAM_DATA 0x5817 6703#define mmCP_ME_RAM_DATA_BASE_IDX 1 6704#define mmCP_CE_UCODE_ADDR 0x5818 6705#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 6706#define mmCP_HYP_CE_UCODE_ADDR 0x5818 6707#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 6708#define mmCP_CE_UCODE_DATA 0x5819 6709#define mmCP_CE_UCODE_DATA_BASE_IDX 1 6710#define mmCP_HYP_CE_UCODE_DATA 0x5819 6711#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 6712#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a 6713#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 6714#define mmCP_MEC_ME1_UCODE_ADDR 0x581a 6715#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 6716#define mmCP_HYP_MEC1_UCODE_DATA 0x581b 6717#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 6718#define mmCP_MEC_ME1_UCODE_DATA 0x581b 6719#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 6720#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c 6721#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 6722#define mmCP_MEC_ME2_UCODE_ADDR 0x581c 6723#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 6724#define mmCP_HYP_MEC2_UCODE_DATA 0x581d 6725#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 6726#define mmCP_MEC_ME2_UCODE_DATA 0x581d 6727#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 6728#define mmRLC_GPM_UCODE_ADDR 0x583c 6729#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 6730#define mmRLC_GPM_UCODE_DATA 0x583d 6731#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 6732#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 6733#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 6734#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 6735#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 6736#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 6737#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 6738#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 6739#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 6740#define mmGRBM_CAM_INDEX 0x5a04 6741#define mmGRBM_CAM_INDEX_BASE_IDX 1 6742#define mmGRBM_HYP_CAM_INDEX 0x5a04 6743#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 6744#define mmGRBM_CAM_DATA 0x5a05 6745#define mmGRBM_CAM_DATA_BASE_IDX 1 6746#define mmGRBM_HYP_CAM_DATA 0x5a05 6747#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1 6748#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 6749#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 6750#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 6751#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 6752#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 6753#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 6754#define mmRLC_RLCV_TIMER_INT_0 0x5b25 6755#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 6756#define mmRLC_RLCV_TIMER_CTRL 0x5b26 6757#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 6758#define mmRLC_RLCV_TIMER_STAT 0x5b27 6759#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 6760#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 6761#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 6762#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 6763#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 6764#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 6765#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 6766#define mmRLC_GPU_IOV_VF_MASK 0x5b2d 6767#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 6768#define mmRLC_HYP_SEMAPHORE_2 0x5b2e 6769#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 6770#define mmRLC_HYP_SEMAPHORE_3 0x5b2f 6771#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 6772#define mmRLC_CLK_CNTL 0x5b31 6773#define mmRLC_CLK_CNTL_BASE_IDX 1 6774#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 6775#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 6776#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 6777#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 6778#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 6779#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 6780#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 6781#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 6782#define mmRLC_GPU_IOV_SCH_0 0x5b38 6783#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 6784#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 6785#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 6786#define mmRLC_GPU_IOV_SCH_3 0x5b3a 6787#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 6788#define mmRLC_GPU_IOV_SCH_1 0x5b3b 6789#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 6790#define mmRLC_GPU_IOV_SCH_2 0x5b3c 6791#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 6792#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42 6793#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 6794#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43 6795#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 6796#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 6797#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 6798#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45 6799#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 6800#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 6801#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 6802#define mmRLC_GPU_IOV_F32_RESET 0x5b47 6803#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 6804#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48 6805#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 6806#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49 6807#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 6808#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a 6809#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 6810#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c 6811#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 6812#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 6813#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 6814#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e 6815#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 6816#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f 6817#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 6818#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 6819#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 6820#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 6821#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 6822 6823 6824// addressBlock: gccacind 6825// base address: 0x0 6826#define ixGC_CAC_CNTL 0x0000 6827#define ixGC_CAC_OVR_SEL 0x0001 6828#define ixGC_CAC_OVR_VAL 0x0002 6829#define ixGC_CAC_WEIGHT_BCI_0 0x0003 6830#define ixGC_CAC_WEIGHT_CB_0 0x0004 6831#define ixGC_CAC_WEIGHT_CB_1 0x0005 6832#define ixGC_CAC_WEIGHT_CBR_0 0x0006 6833#define ixGC_CAC_WEIGHT_CBR_1 0x0007 6834#define ixGC_CAC_WEIGHT_CP_0 0x0008 6835#define ixGC_CAC_WEIGHT_CP_1 0x0009 6836#define ixGC_CAC_WEIGHT_DB_0 0x000a 6837#define ixGC_CAC_WEIGHT_DB_1 0x000b 6838#define ixGC_CAC_WEIGHT_DBR_0 0x000c 6839#define ixGC_CAC_WEIGHT_DBR_1 0x000d 6840#define ixGC_CAC_WEIGHT_GDS_0 0x000e 6841#define ixGC_CAC_WEIGHT_GDS_1 0x000f 6842#define ixGC_CAC_WEIGHT_IA_0 0x0010 6843#define ixGC_CAC_WEIGHT_LDS_0 0x0011 6844#define ixGC_CAC_WEIGHT_LDS_1 0x0012 6845#define ixGC_CAC_WEIGHT_PA_0 0x0013 6846#define ixGC_CAC_WEIGHT_PC_0 0x0014 6847#define ixGC_CAC_WEIGHT_SC_0 0x0015 6848#define ixGC_CAC_WEIGHT_SPI_0 0x0016 6849#define ixGC_CAC_WEIGHT_SPI_1 0x0017 6850#define ixGC_CAC_WEIGHT_SPI_2 0x0018 6851#define ixGC_CAC_WEIGHT_SQ_0 0x001a 6852#define ixGC_CAC_WEIGHT_SQ_1 0x001b 6853#define ixGC_CAC_WEIGHT_SQ_2 0x001c 6854#define ixGC_CAC_WEIGHT_SQ_3 0x001d 6855#define ixGC_CAC_WEIGHT_SQ_4 0x001e 6856#define ixGC_CAC_WEIGHT_SX_0 0x001f 6857#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 6858#define ixGC_CAC_WEIGHT_TA_0 0x0021 6859#define ixGC_CAC_WEIGHT_TCC_0 0x0022 6860#define ixGC_CAC_WEIGHT_TCC_1 0x0023 6861#define ixGC_CAC_WEIGHT_TCC_2 0x0024 6862#define ixGC_CAC_WEIGHT_TCP_0 0x0025 6863#define ixGC_CAC_WEIGHT_TCP_1 0x0026 6864#define ixGC_CAC_WEIGHT_TCP_2 0x0027 6865#define ixGC_CAC_WEIGHT_TD_0 0x0028 6866#define ixGC_CAC_WEIGHT_TD_1 0x0029 6867#define ixGC_CAC_WEIGHT_TD_2 0x002a 6868#define ixGC_CAC_WEIGHT_VGT_0 0x002b 6869#define ixGC_CAC_WEIGHT_VGT_1 0x002c 6870#define ixGC_CAC_WEIGHT_WD_0 0x002d 6871#define ixGC_CAC_WEIGHT_CU_0 0x0032 6872#define ixGC_CAC_WEIGHT_CU_1 0x0033 6873#define ixGC_CAC_WEIGHT_CU_2 0x0034 6874#define ixGC_CAC_WEIGHT_CU_3 0x0035 6875#define ixGC_CAC_WEIGHT_CU_4 0x0036 6876#define ixGC_CAC_WEIGHT_CU_5 0x0037 6877#define ixGC_CAC_WEIGHT_CU_6 0x0038 6878#define ixGC_CAC_WEIGHT_CU_7 0x0039 6879#define ixGC_CAC_ACC_BCI0 0x0042 6880#define ixGC_CAC_ACC_CB0 0x0043 6881#define ixGC_CAC_ACC_CB1 0x0044 6882#define ixGC_CAC_ACC_CB2 0x0045 6883#define ixGC_CAC_ACC_CB3 0x0046 6884#define ixGC_CAC_ACC_CBR0 0x0047 6885#define ixGC_CAC_ACC_CBR1 0x0048 6886#define ixGC_CAC_ACC_CBR2 0x0049 6887#define ixGC_CAC_ACC_CBR3 0x004a 6888#define ixGC_CAC_ACC_CP0 0x004b 6889#define ixGC_CAC_ACC_CP1 0x004c 6890#define ixGC_CAC_ACC_CP2 0x004d 6891#define ixGC_CAC_ACC_DB0 0x004e 6892#define ixGC_CAC_ACC_DB1 0x004f 6893#define ixGC_CAC_ACC_DB2 0x0050 6894#define ixGC_CAC_ACC_DB3 0x0051 6895#define ixGC_CAC_ACC_DBR0 0x0052 6896#define ixGC_CAC_ACC_DBR1 0x0053 6897#define ixGC_CAC_ACC_DBR2 0x0054 6898#define ixGC_CAC_ACC_DBR3 0x0055 6899#define ixGC_CAC_ACC_GDS0 0x0056 6900#define ixGC_CAC_ACC_GDS1 0x0057 6901#define ixGC_CAC_ACC_GDS2 0x0058 6902#define ixGC_CAC_ACC_GDS3 0x0059 6903#define ixGC_CAC_ACC_IA0 0x005a 6904#define ixGC_CAC_ACC_LDS0 0x005b 6905#define ixGC_CAC_ACC_LDS1 0x005c 6906#define ixGC_CAC_ACC_LDS2 0x005d 6907#define ixGC_CAC_ACC_LDS3 0x005e 6908#define ixGC_CAC_ACC_PA0 0x005f 6909#define ixGC_CAC_ACC_PA1 0x0060 6910#define ixGC_CAC_ACC_PC0 0x0061 6911#define ixGC_CAC_ACC_SC0 0x0062 6912#define ixGC_CAC_ACC_SPI0 0x0063 6913#define ixGC_CAC_ACC_SPI1 0x0064 6914#define ixGC_CAC_ACC_SPI2 0x0065 6915#define ixGC_CAC_ACC_SPI3 0x0066 6916#define ixGC_CAC_ACC_SPI4 0x0067 6917#define ixGC_CAC_ACC_SPI5 0x0068 6918#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f 6919#define ixGC_CAC_ACC_EA0 0x0070 6920#define ixGC_CAC_ACC_EA1 0x0071 6921#define ixGC_CAC_ACC_EA2 0x0072 6922#define ixGC_CAC_ACC_EA3 0x0073 6923#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 6924#define ixGC_CAC_OVRD_EA 0x0075 6925#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 6926#define ixGC_CAC_WEIGHT_EA_0 0x0077 6927#define ixGC_CAC_WEIGHT_EA_1 0x0078 6928#define ixGC_CAC_WEIGHT_RMI_0 0x0079 6929#define ixGC_CAC_ACC_RMI0 0x007a 6930#define ixGC_CAC_OVRD_RMI 0x007b 6931#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c 6932#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d 6933#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e 6934#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f 6935#define ixGC_CAC_ACC_EA4 0x0080 6936#define ixGC_CAC_ACC_EA5 0x0081 6937#define ixGC_CAC_WEIGHT_EA_2 0x0082 6938#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 6939#define ixGC_CAC_ACC_SQ0_UPPER 0x008a 6940#define ixGC_CAC_ACC_SQ1_LOWER 0x008b 6941#define ixGC_CAC_ACC_SQ1_UPPER 0x008c 6942#define ixGC_CAC_ACC_SQ2_LOWER 0x008d 6943#define ixGC_CAC_ACC_SQ2_UPPER 0x008e 6944#define ixGC_CAC_ACC_SQ3_LOWER 0x008f 6945#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 6946#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 6947#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 6948#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 6949#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 6950#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 6951#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 6952#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 6953#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 6954#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 6955#define ixGC_CAC_ACC_SQ8_UPPER 0x009a 6956#define ixGC_CAC_ACC_SX0 0x009b 6957#define ixGC_CAC_ACC_SXRB0 0x009c 6958#define ixGC_CAC_ACC_SXRB1 0x009d 6959#define ixGC_CAC_ACC_TA0 0x009e 6960#define ixGC_CAC_ACC_TCC0 0x009f 6961#define ixGC_CAC_ACC_TCC1 0x00a0 6962#define ixGC_CAC_ACC_TCC2 0x00a1 6963#define ixGC_CAC_ACC_TCC3 0x00a2 6964#define ixGC_CAC_ACC_TCC4 0x00a3 6965#define ixGC_CAC_ACC_TCP0 0x00a4 6966#define ixGC_CAC_ACC_TCP1 0x00a5 6967#define ixGC_CAC_ACC_TCP2 0x00a6 6968#define ixGC_CAC_ACC_TCP3 0x00a7 6969#define ixGC_CAC_ACC_TCP4 0x00a8 6970#define ixGC_CAC_ACC_TD0 0x00a9 6971#define ixGC_CAC_ACC_TD1 0x00aa 6972#define ixGC_CAC_ACC_TD2 0x00ab 6973#define ixGC_CAC_ACC_TD3 0x00ac 6974#define ixGC_CAC_ACC_TD4 0x00ad 6975#define ixGC_CAC_ACC_TD5 0x00ae 6976#define ixGC_CAC_ACC_VGT0 0x00af 6977#define ixGC_CAC_ACC_VGT1 0x00b0 6978#define ixGC_CAC_ACC_VGT2 0x00b1 6979#define ixGC_CAC_ACC_WD0 0x00b2 6980#define ixGC_CAC_ACC_CU0 0x00ba 6981#define ixGC_CAC_ACC_CU1 0x00bb 6982#define ixGC_CAC_ACC_CU2 0x00bc 6983#define ixGC_CAC_ACC_CU3 0x00bd 6984#define ixGC_CAC_ACC_CU4 0x00be 6985#define ixGC_CAC_ACC_CU5 0x00bf 6986#define ixGC_CAC_ACC_CU6 0x00c0 6987#define ixGC_CAC_ACC_CU7 0x00c1 6988#define ixGC_CAC_ACC_CU8 0x00c2 6989#define ixGC_CAC_ACC_CU9 0x00c3 6990#define ixGC_CAC_ACC_CU10 0x00c4 6991#define ixGC_CAC_ACC_CU11 0x00c5 6992#define ixGC_CAC_ACC_CU12 0x00c6 6993#define ixGC_CAC_ACC_CU13 0x00c7 6994#define ixGC_CAC_ACC_CU14 0x00c8 6995#define ixGC_CAC_ACC_CU15 0x00c9 6996#define ixGC_CAC_OVRD_BCI 0x00da 6997#define ixGC_CAC_OVRD_CB 0x00db 6998#define ixGC_CAC_OVRD_CBR 0x00dc 6999#define ixGC_CAC_OVRD_CP 0x00dd 7000#define ixGC_CAC_OVRD_DB 0x00de
7001#define ixGC_CAC_OVRD_DBR 0x00df 7002#define ixGC_CAC_OVRD_GDS 0x00e0 7003#define ixGC_CAC_OVRD_IA 0x00e1 7004#define ixGC_CAC_OVRD_LDS 0x00e2 7005#define ixGC_CAC_OVRD_PA 0x00e3 7006#define ixGC_CAC_OVRD_PC 0x00e4 7007#define ixGC_CAC_OVRD_SC 0x00e5 7008#define ixGC_CAC_OVRD_SPI 0x00e6 7009#define ixGC_CAC_OVRD_CU 0x00e7 7010#define ixGC_CAC_OVRD_SQ 0x00e8 7011#define ixGC_CAC_OVRD_SX 0x00e9 7012#define ixGC_CAC_OVRD_SXRB 0x00ea 7013#define ixGC_CAC_OVRD_TA 0x00eb 7014#define ixGC_CAC_OVRD_TCC 0x00ec 7015#define ixGC_CAC_OVRD_TCP 0x00ed 7016#define ixGC_CAC_OVRD_TD 0x00ee 7017#define ixGC_CAC_OVRD_VGT 0x00ef 7018#define ixGC_CAC_OVRD_WD 0x00f0 7019#define ixGC_CAC_ACC_BCI1 0x00ff 7020#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 7021#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 7022#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 7023#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 7024#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 7025#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 7026#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 7027#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 7028#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 7029#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 7030#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a 7031#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b 7032#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c 7033#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d 7034#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e 7035#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f 7036#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 7037#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 7038#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 7039#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 7040#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 7041#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 7042#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 7043#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 7044#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 7045#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 7046#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a 7047#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b 7048#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c 7049#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d 7050#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e 7051#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f 7052#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 7053#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 7054#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 7055#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 7056 7057 7058// addressBlock: secacind 7059// base address: 0x0 7060#define ixSE_CAC_CNTL 0x0000 7061#define ixSE_CAC_OVR_SEL 0x0001 7062#define ixSE_CAC_OVR_VAL 0x0002 7063 7064 7065// addressBlock: sqind 7066// base address: 0x0 7067#define ixSQ_WAVE_MODE 0x0011 7068#define ixSQ_WAVE_STATUS 0x0012 7069#define ixSQ_WAVE_TRAPSTS 0x0013 7070#define ixSQ_WAVE_HW_ID 0x0014 7071#define ixSQ_WAVE_GPR_ALLOC 0x0015 7072#define ixSQ_WAVE_LDS_ALLOC 0x0016 7073#define ixSQ_WAVE_IB_STS 0x0017 7074#define ixSQ_WAVE_PC_LO 0x0018 7075#define ixSQ_WAVE_PC_HI 0x0019 7076#define ixSQ_WAVE_INST_DW0 0x001a 7077#define ixSQ_WAVE_INST_DW1 0x001b 7078#define ixSQ_WAVE_IB_DBG0 0x001c 7079#define ixSQ_WAVE_IB_DBG1 0x001d 7080#define ixSQ_WAVE_FLUSH_IB 0x001e 7081#define ixSQ_WAVE_TTMP0 0x026c 7082#define ixSQ_WAVE_TTMP1 0x026d 7083#define ixSQ_WAVE_TTMP2 0x026e 7084#define ixSQ_WAVE_TTMP3 0x026f 7085#define ixSQ_WAVE_TTMP4 0x0270 7086#define ixSQ_WAVE_TTMP5 0x0271 7087#define ixSQ_WAVE_TTMP6 0x0272 7088#define ixSQ_WAVE_TTMP7 0x0273 7089#define ixSQ_WAVE_TTMP8 0x0274 7090#define ixSQ_WAVE_TTMP9 0x0275 7091#define ixSQ_WAVE_TTMP10 0x0276 7092#define ixSQ_WAVE_TTMP11 0x0277 7093#define ixSQ_WAVE_TTMP12 0x0278 7094#define ixSQ_WAVE_TTMP13 0x0279 7095#define ixSQ_WAVE_TTMP14 0x027a 7096#define ixSQ_WAVE_TTMP15 0x027b 7097#define ixSQ_WAVE_M0 0x027c 7098#define ixSQ_WAVE_EXEC_LO 0x027e 7099#define ixSQ_WAVE_EXEC_HI 0x027f 7100#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 7101#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 7102#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 7103#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 7104#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 7105#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 7106#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 7107#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 7108 7109 7110// addressBlock: didtind 7111// base address: 0x0 7112#define ixDIDT_SQ_CTRL0 0x0000 7113#define ixDIDT_SQ_CTRL1 0x0001 7114#define ixDIDT_SQ_CTRL2 0x0002 7115#define ixDIDT_SQ_STALL_CTRL 0x0004 7116#define ixDIDT_SQ_TUNING_CTRL 0x0005 7117#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 7118#define ixDIDT_SQ_CTRL3 0x0007 7119#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 7120#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 7121#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a 7122#define ixDIDT_SQ_STALL_PATTERN_7 0x000b 7123#define ixDIDT_SQ_WEIGHT0_3 0x0010 7124#define ixDIDT_SQ_WEIGHT4_7 0x0011 7125#define ixDIDT_SQ_WEIGHT8_11 0x0012 7126#define ixDIDT_SQ_EDC_CTRL 0x0013 7127#define ixDIDT_SQ_EDC_THRESHOLD 0x0014 7128#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 7129#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 7130#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 7131#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 7132#define ixDIDT_SQ_EDC_STATUS 0x0019 7133#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a 7134#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b 7135#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c 7136#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d 7137#define ixDIDT_SQ_EDC_OVERFLOW 0x001e 7138#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f 7139#define ixDIDT_DB_CTRL0 0x0020 7140#define ixDIDT_DB_CTRL1 0x0021 7141#define ixDIDT_DB_CTRL2 0x0022 7142#define ixDIDT_DB_STALL_CTRL 0x0024 7143#define ixDIDT_DB_TUNING_CTRL 0x0025 7144#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 7145#define ixDIDT_DB_CTRL3 0x0027 7146#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 7147#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 7148#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a 7149#define ixDIDT_DB_STALL_PATTERN_7 0x002b 7150#define ixDIDT_DB_WEIGHT0_3 0x0030 7151#define ixDIDT_DB_WEIGHT4_7 0x0031 7152#define ixDIDT_DB_WEIGHT8_11 0x0032 7153#define ixDIDT_DB_EDC_CTRL 0x0033 7154#define ixDIDT_DB_EDC_THRESHOLD 0x0034 7155#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 7156#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 7157#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 7158#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 7159#define ixDIDT_DB_EDC_STATUS 0x0039 7160#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a 7161#define ixDIDT_DB_EDC_OVERFLOW 0x003e 7162#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f 7163#define ixDIDT_TD_CTRL0 0x0040 7164#define ixDIDT_TD_CTRL1 0x0041 7165#define ixDIDT_TD_CTRL2 0x0042 7166#define ixDIDT_TD_STALL_CTRL 0x0044 7167#define ixDIDT_TD_TUNING_CTRL 0x0045 7168#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 7169#define ixDIDT_TD_CTRL3 0x0047 7170#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 7171#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 7172#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a 7173#define ixDIDT_TD_STALL_PATTERN_7 0x004b 7174#define ixDIDT_TD_WEIGHT0_3 0x0050 7175#define ixDIDT_TD_WEIGHT4_7 0x0051 7176#define ixDIDT_TD_WEIGHT8_11 0x0052 7177#define ixDIDT_TD_EDC_CTRL 0x0053 7178#define ixDIDT_TD_EDC_THRESHOLD 0x0054 7179#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 7180#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 7181#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 7182#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 7183#define ixDIDT_TD_EDC_STATUS 0x0059 7184#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a 7185#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b 7186#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c 7187#define ixDIDT_TD_EDC_STALL_DELAY_4 0x005d 7188#define ixDIDT_TD_EDC_OVERFLOW 0x005e 7189#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f 7190#define ixDIDT_TCP_CTRL0 0x0060 7191#define ixDIDT_TCP_CTRL1 0x0061 7192#define ixDIDT_TCP_CTRL2 0x0062 7193#define ixDIDT_TCP_STALL_CTRL 0x0064 7194#define ixDIDT_TCP_TUNING_CTRL 0x0065 7195#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 7196#define ixDIDT_TCP_CTRL3 0x0067 7197#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 7198#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 7199#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a 7200#define ixDIDT_TCP_STALL_PATTERN_7 0x006b 7201#define ixDIDT_TCP_WEIGHT0_3 0x0070 7202#define ixDIDT_TCP_WEIGHT4_7 0x0071 7203#define ixDIDT_TCP_WEIGHT8_11 0x0072 7204#define ixDIDT_TCP_EDC_CTRL 0x0073 7205#define ixDIDT_TCP_EDC_THRESHOLD 0x0074 7206#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 7207#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 7208#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 7209#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 7210#define ixDIDT_TCP_EDC_STATUS 0x0079 7211#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a 7212#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b 7213#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c 7214#define ixDIDT_TCP_EDC_STALL_DELAY_4 0x007d 7215#define ixDIDT_TCP_EDC_OVERFLOW 0x007e 7216#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f 7217#define ixDIDT_DBR_CTRL0 0x0080 7218#define ixDIDT_DBR_CTRL1 0x0081 7219#define ixDIDT_DBR_CTRL2 0x0082 7220#define ixDIDT_DBR_STALL_CTRL 0x0084 7221#define ixDIDT_DBR_TUNING_CTRL 0x0085 7222#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL 0x0086 7223#define ixDIDT_DBR_CTRL3 0x0087 7224#define ixDIDT_DBR_STALL_PATTERN_1_2 0x0088 7225#define ixDIDT_DBR_STALL_PATTERN_3_4 0x0089 7226#define ixDIDT_DBR_STALL_PATTERN_5_6 0x008a 7227#define ixDIDT_DBR_STALL_PATTERN_7 0x008b 7228#define ixDIDT_DBR_WEIGHT0_3 0x0090 7229#define ixDIDT_DBR_WEIGHT4_7 0x0091 7230#define ixDIDT_DBR_WEIGHT8_11 0x0092 7231#define ixDIDT_DBR_EDC_CTRL 0x0093 7232#define ixDIDT_DBR_EDC_THRESHOLD 0x0094 7233#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2 0x0095 7234#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4 0x0096 7235#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097 7236#define ixDIDT_DBR_EDC_STALL_PATTERN_7 0x0098 7237#define ixDIDT_DBR_EDC_STATUS 0x0099 7238#define ixDIDT_DBR_EDC_STALL_DELAY_1 0x009a 7239#define ixDIDT_DBR_EDC_OVERFLOW 0x009e 7240#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA 0x009f 7241#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 7242#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 7243#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 7244#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 7245#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 7246 7247 7248 7249#endif 7250