linux/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
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   1/*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef _VEGA12_HWMGR_H_
  25#define _VEGA12_HWMGR_H_
  26
  27#include "hwmgr.h"
  28#include "vega12/smu9_driver_if.h"
  29#include "ppatomfwctrl.h"
  30
  31#define VEGA12_MAX_HARDWARE_POWERLEVELS 2
  32
  33#define WaterMarksExist  1
  34#define WaterMarksLoaded 2
  35
  36#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS   16
  37#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
  38#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
  39#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS     4
  40
  41enum
  42{
  43        GNLD_DPM_PREFETCHER = 0,
  44        GNLD_DPM_GFXCLK,
  45        GNLD_DPM_UCLK,
  46        GNLD_DPM_SOCCLK,
  47        GNLD_DPM_UVD,
  48        GNLD_DPM_VCE,
  49        GNLD_ULV,
  50        GNLD_DPM_MP0CLK,
  51        GNLD_DPM_LINK,
  52        GNLD_DPM_DCEFCLK,
  53        GNLD_DS_GFXCLK,
  54        GNLD_DS_SOCCLK,
  55        GNLD_DS_LCLK,
  56        GNLD_PPT,
  57        GNLD_TDC,
  58        GNLD_THERMAL,
  59        GNLD_GFX_PER_CU_CG,
  60        GNLD_RM,
  61        GNLD_DS_DCEFCLK,
  62        GNLD_ACDC,
  63        GNLD_VR0HOT,
  64        GNLD_VR1HOT,
  65        GNLD_FW_CTF,
  66        GNLD_LED_DISPLAY,
  67        GNLD_FAN_CONTROL,
  68        GNLD_DIDT,
  69        GNLD_GFXOFF,
  70        GNLD_CG,
  71        GNLD_ACG,
  72
  73        GNLD_FEATURES_MAX
  74};
  75
  76
  77#define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
  78
  79#define SMC_DPM_FEATURES    0x30F
  80
  81struct smu_features {
  82        bool supported;
  83        bool enabled;
  84        bool allowed;
  85        uint32_t smu_feature_id;
  86        uint64_t smu_feature_bitmap;
  87};
  88
  89struct vega12_dpm_level {
  90        bool            enabled;
  91        uint32_t        value;
  92        uint32_t        param1;
  93};
  94
  95#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
  96#define MAX_REGULAR_DPM_NUMBER 16
  97#define MAX_PCIE_CONF 2
  98#define VEGA12_MINIMUM_ENGINE_CLOCK 2500
  99
 100struct vega12_dpm_state {
 101        uint32_t  soft_min_level;
 102        uint32_t  soft_max_level;
 103        uint32_t  hard_min_level;
 104        uint32_t  hard_max_level;
 105};
 106
 107struct vega12_single_dpm_table {
 108        uint32_t                count;
 109        struct vega12_dpm_state dpm_state;
 110        struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
 111};
 112
 113struct vega12_odn_dpm_control {
 114        uint32_t        count;
 115        uint32_t        entries[MAX_REGULAR_DPM_NUMBER];
 116};
 117
 118struct vega12_pcie_table {
 119        uint16_t count;
 120        uint8_t  pcie_gen[MAX_PCIE_CONF];
 121        uint8_t  pcie_lane[MAX_PCIE_CONF];
 122        uint32_t lclk[MAX_PCIE_CONF];
 123};
 124
 125struct vega12_dpm_table {
 126        struct vega12_single_dpm_table  soc_table;
 127        struct vega12_single_dpm_table  gfx_table;
 128        struct vega12_single_dpm_table  mem_table;
 129        struct vega12_single_dpm_table  eclk_table;
 130        struct vega12_single_dpm_table  vclk_table;
 131        struct vega12_single_dpm_table  dclk_table;
 132        struct vega12_single_dpm_table  dcef_table;
 133        struct vega12_single_dpm_table  pixel_table;
 134        struct vega12_single_dpm_table  display_table;
 135        struct vega12_single_dpm_table  phy_table;
 136        struct vega12_pcie_table        pcie_table;
 137};
 138
 139#define VEGA12_MAX_LEAKAGE_COUNT  8
 140struct vega12_leakage_voltage {
 141        uint16_t  count;
 142        uint16_t  leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
 143        uint16_t  actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
 144};
 145
 146struct vega12_display_timing {
 147        uint32_t  min_clock_in_sr;
 148        uint32_t  num_existing_displays;
 149};
 150
 151struct vega12_dpmlevel_enable_mask {
 152        uint32_t  uvd_dpm_enable_mask;
 153        uint32_t  vce_dpm_enable_mask;
 154        uint32_t  samu_dpm_enable_mask;
 155        uint32_t  sclk_dpm_enable_mask;
 156        uint32_t  mclk_dpm_enable_mask;
 157};
 158
 159struct vega12_vbios_boot_state {
 160        bool        bsoc_vddc_lock;
 161        uint8_t     uc_cooling_id;
 162        uint16_t    vddc;
 163        uint16_t    vddci;
 164        uint16_t    mvddc;
 165        uint16_t    vdd_gfx;
 166        uint32_t    gfx_clock;
 167        uint32_t    mem_clock;
 168        uint32_t    soc_clock;
 169        uint32_t    dcef_clock;
 170        uint32_t    eclock;
 171        uint32_t    dclock;
 172        uint32_t    vclock;
 173};
 174
 175#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 176#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 177#define DPMTABLE_UPDATE_SCLK        0x00000004
 178#define DPMTABLE_UPDATE_MCLK        0x00000008
 179#define DPMTABLE_OD_UPDATE_VDDC     0x00000010
 180
 181struct vega12_smc_state_table {
 182        uint32_t        soc_boot_level;
 183        uint32_t        gfx_boot_level;
 184        uint32_t        dcef_boot_level;
 185        uint32_t        mem_boot_level;
 186        uint32_t        uvd_boot_level;
 187        uint32_t        vce_boot_level;
 188        uint32_t        gfx_max_level;
 189        uint32_t        mem_max_level;
 190        uint8_t         vr_hot_gpio;
 191        uint8_t         ac_dc_gpio;
 192        uint8_t         therm_out_gpio;
 193        uint8_t         therm_out_polarity;
 194        uint8_t         therm_out_mode;
 195        PPTable_t       pp_table;
 196        Watermarks_t    water_marks_table;
 197        AvfsDebugTable_t avfs_debug_table;
 198        AvfsFuseOverride_t avfs_fuse_override_table;
 199        SmuMetrics_t    smu_metrics;
 200        DriverSmuConfig_t driver_smu_config;
 201        DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
 202        OverDriveTable_t overdrive_table;
 203};
 204
 205struct vega12_mclk_latency_entries {
 206        uint32_t  frequency;
 207        uint32_t  latency;
 208};
 209
 210struct vega12_mclk_latency_table {
 211        uint32_t  count;
 212        struct vega12_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
 213};
 214
 215struct vega12_registry_data {
 216        uint64_t  disallowed_features;
 217        uint8_t   ac_dc_switch_gpio_support;
 218        uint8_t   acg_loop_support;
 219        uint8_t   clock_stretcher_support;
 220        uint8_t   db_ramping_support;
 221        uint8_t   didt_mode;
 222        uint8_t   didt_support;
 223        uint8_t   edc_didt_support;
 224        uint8_t   force_dpm_high;
 225        uint8_t   fuzzy_fan_control_support;
 226        uint8_t   mclk_dpm_key_disabled;
 227        uint8_t   od_state_in_dc_support;
 228        uint8_t   pcie_lane_override;
 229        uint8_t   pcie_speed_override;
 230        uint32_t  pcie_clock_override;
 231        uint8_t   pcie_dpm_key_disabled;
 232        uint8_t   dcefclk_dpm_key_disabled;
 233        uint8_t   prefetcher_dpm_key_disabled;
 234        uint8_t   quick_transition_support;
 235        uint8_t   regulator_hot_gpio_support;
 236        uint8_t   master_deep_sleep_support;
 237        uint8_t   gfx_clk_deep_sleep_support;
 238        uint8_t   sclk_deep_sleep_support;
 239        uint8_t   lclk_deep_sleep_support;
 240        uint8_t   dce_fclk_deep_sleep_support;
 241        uint8_t   sclk_dpm_key_disabled;
 242        uint8_t   sclk_throttle_low_notification;
 243        uint8_t   skip_baco_hardware;
 244        uint8_t   socclk_dpm_key_disabled;
 245        uint8_t   sq_ramping_support;
 246        uint8_t   tcp_ramping_support;
 247        uint8_t   td_ramping_support;
 248        uint8_t   dbr_ramping_support;
 249        uint8_t   gc_didt_support;
 250        uint8_t   psm_didt_support;
 251        uint8_t   thermal_support;
 252        uint8_t   fw_ctf_enabled;
 253        uint8_t   led_dpm_enabled;
 254        uint8_t   fan_control_support;
 255        uint8_t   ulv_support;
 256        uint8_t   odn_feature_enable;
 257        uint8_t   disable_water_mark;
 258        uint8_t   disable_workload_policy;
 259        uint32_t  force_workload_policy_mask;
 260        uint8_t   disable_3d_fs_detection;
 261        uint8_t   disable_pp_tuning;
 262        uint8_t   disable_xlpp_tuning;
 263        uint32_t  perf_ui_tuning_profile_turbo;
 264        uint32_t  perf_ui_tuning_profile_powerSave;
 265        uint32_t  perf_ui_tuning_profile_xl;
 266        uint16_t  zrpm_stop_temp;
 267        uint16_t  zrpm_start_temp;
 268        uint32_t  stable_pstate_sclk_dpm_percentage;
 269        uint8_t   fps_support;
 270        uint8_t   vr0hot;
 271        uint8_t   vr1hot;
 272        uint8_t   disable_auto_wattman;
 273        uint32_t  auto_wattman_debug;
 274        uint32_t  auto_wattman_sample_period;
 275        uint8_t   auto_wattman_threshold;
 276        uint8_t   log_avfs_param;
 277        uint8_t   enable_enginess;
 278        uint8_t   custom_fan_support;
 279        uint8_t   disable_pcc_limit_control;
 280};
 281
 282struct vega12_odn_clock_voltage_dependency_table {
 283        uint32_t count;
 284        struct phm_ppt_v1_clock_voltage_dependency_record
 285                entries[MAX_REGULAR_DPM_NUMBER];
 286};
 287
 288struct vega12_odn_dpm_table {
 289        struct vega12_odn_dpm_control           control_gfxclk_state;
 290        struct vega12_odn_dpm_control           control_memclk_state;
 291        struct phm_odn_clock_levels             odn_core_clock_dpm_levels;
 292        struct phm_odn_clock_levels             odn_memory_clock_dpm_levels;
 293        struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_sclk;
 294        struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_mclk;
 295        struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_socclk;
 296        uint32_t                                odn_mclk_min_limit;
 297};
 298
 299struct vega12_odn_fan_table {
 300        uint32_t        target_fan_speed;
 301        uint32_t        target_temperature;
 302        uint32_t        min_performance_clock;
 303        uint32_t        min_fan_limit;
 304        bool            force_fan_pwm;
 305};
 306
 307struct vega12_clock_range {
 308        uint32_t        ACMax;
 309        uint32_t        ACMin;
 310        uint32_t        DCMax;
 311};
 312
 313struct vega12_hwmgr {
 314        struct vega12_dpm_table          dpm_table;
 315        struct vega12_dpm_table          golden_dpm_table;
 316        struct vega12_registry_data      registry_data;
 317        struct vega12_vbios_boot_state   vbios_boot_state;
 318        struct vega12_mclk_latency_table mclk_latency_table;
 319
 320        struct vega12_leakage_voltage    vddc_leakage;
 321
 322        uint32_t                           vddc_control;
 323        struct pp_atomfwctrl_voltage_table vddc_voltage_table;
 324        uint32_t                           mvdd_control;
 325        struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
 326        uint32_t                           vddci_control;
 327        struct pp_atomfwctrl_voltage_table vddci_voltage_table;
 328
 329        uint32_t                           active_auto_throttle_sources;
 330        uint32_t                           water_marks_bitmap;
 331
 332        struct vega12_odn_dpm_table       odn_dpm_table;
 333        struct vega12_odn_fan_table       odn_fan_table;
 334
 335        /* ---- General data ---- */
 336        uint8_t                           need_update_dpm_table;
 337
 338        bool                           cac_enabled;
 339        bool                           battery_state;
 340        bool                           is_tlu_enabled;
 341        bool                           avfs_exist;
 342
 343        uint32_t                       low_sclk_interrupt_threshold;
 344
 345        uint32_t                       total_active_cus;
 346
 347        struct vega12_display_timing display_timing;
 348
 349        /* ---- Vega12 Dyn Register Settings ---- */
 350
 351        uint32_t                       debug_settings;
 352        uint32_t                       lowest_uclk_reserved_for_ulv;
 353        uint32_t                       gfxclk_average_alpha;
 354        uint32_t                       socclk_average_alpha;
 355        uint32_t                       uclk_average_alpha;
 356        uint32_t                       gfx_activity_average_alpha;
 357        uint32_t                       display_voltage_mode;
 358        uint32_t                       dcef_clk_quad_eqn_a;
 359        uint32_t                       dcef_clk_quad_eqn_b;
 360        uint32_t                       dcef_clk_quad_eqn_c;
 361        uint32_t                       disp_clk_quad_eqn_a;
 362        uint32_t                       disp_clk_quad_eqn_b;
 363        uint32_t                       disp_clk_quad_eqn_c;
 364        uint32_t                       pixel_clk_quad_eqn_a;
 365        uint32_t                       pixel_clk_quad_eqn_b;
 366        uint32_t                       pixel_clk_quad_eqn_c;
 367        uint32_t                       phy_clk_quad_eqn_a;
 368        uint32_t                       phy_clk_quad_eqn_b;
 369        uint32_t                       phy_clk_quad_eqn_c;
 370
 371        /* ---- Thermal Temperature Setting ---- */
 372        struct vega12_dpmlevel_enable_mask     dpm_level_enable_mask;
 373
 374        /* ---- Power Gating States ---- */
 375        bool                           uvd_power_gated;
 376        bool                           vce_power_gated;
 377        bool                           samu_power_gated;
 378        bool                           need_long_memory_training;
 379
 380        /* Internal settings to apply the application power optimization parameters */
 381        bool                           apply_optimized_settings;
 382        uint32_t                       disable_dpm_mask;
 383
 384        /* ---- Overdrive next setting ---- */
 385        uint32_t                       apply_overdrive_next_settings_mask;
 386
 387        /* ---- Workload Mask ---- */
 388        uint32_t                       workload_mask;
 389
 390        /* ---- SMU9 ---- */
 391        uint32_t                       smu_version;
 392        struct smu_features            smu_features[GNLD_FEATURES_MAX];
 393        struct vega12_smc_state_table  smc_state_table;
 394
 395        struct vega12_clock_range      clk_range[PPCLK_COUNT];
 396
 397        /* ---- Gfxoff ---- */
 398        bool                           gfxoff_controlled_by_driver;
 399
 400        unsigned long                  metrics_time;
 401        SmuMetrics_t                   metrics_table;
 402};
 403
 404#define VEGA12_DPM2_NEAR_TDP_DEC                      10
 405#define VEGA12_DPM2_ABOVE_SAFE_INC                    5
 406#define VEGA12_DPM2_BELOW_SAFE_INC                    20
 407
 408#define VEGA12_DPM2_LTA_WINDOW_SIZE                   7
 409
 410#define VEGA12_DPM2_LTS_TRUNCATE                      0
 411
 412#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT            80
 413
 414#define VEGA12_DPM2_MAXPS_PERCENT_M                   90
 415#define VEGA12_DPM2_MAXPS_PERCENT_H                   90
 416
 417#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN         50
 418
 419#define VEGA12_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 420#define VEGA12_DPM2_SQ_RAMP_MIN_POWER                 0x12
 421#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 422#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
 423#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
 424
 425#define VEGA12_VOLTAGE_CONTROL_NONE                   0x0
 426#define VEGA12_VOLTAGE_CONTROL_BY_GPIO                0x1
 427#define VEGA12_VOLTAGE_CONTROL_BY_SVID2               0x2
 428#define VEGA12_VOLTAGE_CONTROL_MERGED                 0x3
 429/* To convert to Q8.8 format for firmware */
 430#define VEGA12_Q88_FORMAT_CONVERSION_UNIT             256
 431
 432#define VEGA12_UNUSED_GPIO_PIN       0x7F
 433
 434#define VEGA12_THERM_OUT_MODE_DISABLE       0x0
 435#define VEGA12_THERM_OUT_MODE_THERM_ONLY    0x1
 436#define VEGA12_THERM_OUT_MODE_THERM_VRHOT   0x2
 437
 438#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT   0xffffffff
 439#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT    0xffffffff
 440
 441#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 442#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 443#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
 444#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
 445#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
 446#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT         0xffffffff
 447#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT          0xffffffff
 448
 449#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL         0x3
 450#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL         0x3
 451#define VEGA12_UMD_PSTATE_MCLK_LEVEL           0x2
 452#define VEGA12_UMD_PSTATE_UVDCLK_LEVEL         0x3
 453#define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL        0x3
 454
 455int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
 456
 457#endif /* _VEGA12_HWMGR_H_ */
 458