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23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "hardwaremanager.h"
29#include "hwmgr_ppt.h"
30#include "ppatomctrl.h"
31#include "power_state.h"
32#include "smu_helper.h"
33
34struct pp_hwmgr;
35struct phm_fan_speed_info;
36struct pp_atomctrl_voltage_table;
37
38#define VOLTAGE_SCALE 4
39#define VOLTAGE_VID_OFFSET_SCALE1 625
40#define VOLTAGE_VID_OFFSET_SCALE2 100
41
42enum DISPLAY_GAP {
43 DISPLAY_GAP_VBLANK_OR_WM = 0,
44 DISPLAY_GAP_VBLANK = 1,
45 DISPLAY_GAP_WATERMARK = 2,
46 DISPLAY_GAP_IGNORE = 3
47};
48typedef enum DISPLAY_GAP DISPLAY_GAP;
49
50enum BACO_STATE {
51 BACO_STATE_OUT = 0,
52 BACO_STATE_IN,
53};
54
55struct vi_dpm_level {
56 bool enabled;
57 uint32_t value;
58 uint32_t param1;
59};
60
61struct vi_dpm_table {
62 uint32_t count;
63 struct vi_dpm_level dpm_level[1];
64};
65
66#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
67#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
68#define PCIE_PERF_REQ_GEN1 2
69#define PCIE_PERF_REQ_GEN2 3
70#define PCIE_PERF_REQ_GEN3 4
71
72enum PHM_BackEnd_Magic {
73 PHM_Dummy_Magic = 0xAA5555AA,
74 PHM_RV770_Magic = 0xDCBAABCD,
75 PHM_Kong_Magic = 0x239478DF,
76 PHM_NIslands_Magic = 0x736C494E,
77 PHM_Sumo_Magic = 0x8339FA11,
78 PHM_SIslands_Magic = 0x369431AC,
79 PHM_Trinity_Magic = 0x96751873,
80 PHM_CIslands_Magic = 0x38AC78B0,
81 PHM_Kv_Magic = 0xDCBBABC0,
82 PHM_VIslands_Magic = 0x20130307,
83 PHM_Cz_Magic = 0x67DCBA25,
84 PHM_Rv_Magic = 0x20161121
85};
86
87struct phm_set_power_state_input {
88 const struct pp_hw_power_state *pcurrent_state;
89 const struct pp_hw_power_state *pnew_state;
90};
91
92struct phm_clock_array {
93 uint32_t count;
94 uint32_t values[1];
95};
96
97struct phm_clock_voltage_dependency_record {
98 uint32_t clk;
99 uint32_t v;
100};
101
102struct phm_vceclock_voltage_dependency_record {
103 uint32_t ecclk;
104 uint32_t evclk;
105 uint32_t v;
106};
107
108struct phm_uvdclock_voltage_dependency_record {
109 uint32_t vclk;
110 uint32_t dclk;
111 uint32_t v;
112};
113
114struct phm_samuclock_voltage_dependency_record {
115 uint32_t samclk;
116 uint32_t v;
117};
118
119struct phm_acpclock_voltage_dependency_record {
120 uint32_t acpclk;
121 uint32_t v;
122};
123
124struct phm_clock_voltage_dependency_table {
125 uint32_t count;
126 struct phm_clock_voltage_dependency_record entries[1];
127};
128
129struct phm_phase_shedding_limits_record {
130 uint32_t Voltage;
131 uint32_t Sclk;
132 uint32_t Mclk;
133};
134
135struct phm_uvd_clock_voltage_dependency_record {
136 uint32_t vclk;
137 uint32_t dclk;
138 uint32_t v;
139};
140
141struct phm_uvd_clock_voltage_dependency_table {
142 uint8_t count;
143 struct phm_uvd_clock_voltage_dependency_record entries[1];
144};
145
146struct phm_acp_clock_voltage_dependency_record {
147 uint32_t acpclk;
148 uint32_t v;
149};
150
151struct phm_acp_clock_voltage_dependency_table {
152 uint32_t count;
153 struct phm_acp_clock_voltage_dependency_record entries[1];
154};
155
156struct phm_vce_clock_voltage_dependency_record {
157 uint32_t ecclk;
158 uint32_t evclk;
159 uint32_t v;
160};
161
162struct phm_phase_shedding_limits_table {
163 uint32_t count;
164 struct phm_phase_shedding_limits_record entries[1];
165};
166
167struct phm_vceclock_voltage_dependency_table {
168 uint8_t count;
169 struct phm_vceclock_voltage_dependency_record entries[1];
170};
171
172struct phm_uvdclock_voltage_dependency_table {
173 uint8_t count;
174 struct phm_uvdclock_voltage_dependency_record entries[1];
175};
176
177struct phm_samuclock_voltage_dependency_table {
178 uint8_t count;
179 struct phm_samuclock_voltage_dependency_record entries[1];
180};
181
182struct phm_acpclock_voltage_dependency_table {
183 uint32_t count;
184 struct phm_acpclock_voltage_dependency_record entries[1];
185};
186
187struct phm_vce_clock_voltage_dependency_table {
188 uint8_t count;
189 struct phm_vce_clock_voltage_dependency_record entries[1];
190};
191
192struct pp_smumgr_func {
193 char *name;
194 int (*smu_init)(struct pp_hwmgr *hwmgr);
195 int (*smu_fini)(struct pp_hwmgr *hwmgr);
196 int (*start_smu)(struct pp_hwmgr *hwmgr);
197 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
198 uint32_t firmware);
199 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
200 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
201 uint32_t firmware);
202 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
203 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
204 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
205 uint16_t msg, uint32_t parameter);
206 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
207 void **table);
208 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
209 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
210 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
211 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
212 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
213 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
214 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
215 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
216 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
217 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
218 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
219 uint32_t (*get_mac_definition)(uint32_t value);
220 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
221 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
222 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
223 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
224};
225
226struct pp_hwmgr_func {
227 int (*backend_init)(struct pp_hwmgr *hw_mgr);
228 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
229 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
230 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
231
232 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
233 struct pp_power_state *prequest_ps,
234 const struct pp_power_state *pcurrent_ps);
235
236 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
237
238 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
239 enum amd_dpm_forced_level level);
240
241 int (*dynamic_state_management_enable)(
242 struct pp_hwmgr *hw_mgr);
243 int (*dynamic_state_management_disable)(
244 struct pp_hwmgr *hw_mgr);
245
246 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
247 struct pp_hw_power_state *hw_ps);
248
249 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
250 unsigned long, struct pp_power_state *);
251 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
252 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
253 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
254 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
255 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
256 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
257 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
258 int (*power_state_set)(struct pp_hwmgr *hwmgr,
259 const void *state);
260 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
261 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
262 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
263 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
264 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
265 const uint32_t *msg_id);
266 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
267 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
268 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
269 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
270 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
271 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
272 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
273 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
274 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
275 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
276 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
277 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
278 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
279 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
280 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
281 const struct pp_hw_power_state *pstate1,
282 const struct pp_hw_power_state *pstate2,
283 bool *equal);
284 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
285 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
286 bool cc6_disable, bool pstate_disable,
287 bool pstate_switch_disable);
288 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
289 struct amd_pp_simple_clock_info *info);
290 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
291 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
292 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
293 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
294 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
295 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
296 enum amd_pp_clock_type type,
297 struct pp_clock_levels_with_latency *clocks);
298 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
299 enum amd_pp_clock_type type,
300 struct pp_clock_levels_with_voltage *clocks);
301 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
302 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
303 struct pp_display_clock_request *clock);
304 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
305 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
306 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
307 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
308 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
309 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
310 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
311 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
312 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
313 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
314 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
315 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
316 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
317 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
318 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
319 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
320 uint32_t virtual_addr_low,
321 uint32_t virtual_addr_hi,
322 uint32_t mc_addr_low,
323 uint32_t mc_addr_hi,
324 uint32_t size);
325 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
326 bool enable,
327 bool lock);
328 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
329 struct PP_TemperatureRange *range);
330 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
331 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
332 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
333 enum PP_OD_DPM_TABLE_COMMAND type,
334 long *input, uint32_t size);
335 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
336 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
337 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
338 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
339 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
340 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
341 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
342 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
343 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
344 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
345 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
346 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
347};
348
349struct pp_table_func {
350 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
351 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
352 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
353 int (*pptable_get_vce_state_table_entry)(
354 struct pp_hwmgr *hwmgr,
355 unsigned long i,
356 struct amd_vce_state *vce_state,
357 void **clock_info,
358 unsigned long *flag);
359};
360
361union phm_cac_leakage_record {
362 struct {
363 uint16_t Vddc;
364 uint32_t Leakage;
365 };
366 struct {
367 uint16_t Vddc1;
368 uint16_t Vddc2;
369 uint16_t Vddc3;
370 };
371};
372
373struct phm_cac_leakage_table {
374 uint32_t count;
375 union phm_cac_leakage_record entries[1];
376};
377
378struct phm_samu_clock_voltage_dependency_record {
379 uint32_t samclk;
380 uint32_t v;
381};
382
383
384struct phm_samu_clock_voltage_dependency_table {
385 uint8_t count;
386 struct phm_samu_clock_voltage_dependency_record entries[1];
387};
388
389struct phm_cac_tdp_table {
390 uint16_t usTDP;
391 uint16_t usConfigurableTDP;
392 uint16_t usTDC;
393 uint16_t usBatteryPowerLimit;
394 uint16_t usSmallPowerLimit;
395 uint16_t usLowCACLeakage;
396 uint16_t usHighCACLeakage;
397 uint16_t usMaximumPowerDeliveryLimit;
398 uint16_t usEDCLimit;
399 uint16_t usOperatingTempMinLimit;
400 uint16_t usOperatingTempMaxLimit;
401 uint16_t usOperatingTempStep;
402 uint16_t usOperatingTempHyst;
403 uint16_t usDefaultTargetOperatingTemp;
404 uint16_t usTargetOperatingTemp;
405 uint16_t usPowerTuneDataSetID;
406 uint16_t usSoftwareShutdownTemp;
407 uint16_t usClockStretchAmount;
408 uint16_t usTemperatureLimitHotspot;
409 uint16_t usTemperatureLimitLiquid1;
410 uint16_t usTemperatureLimitLiquid2;
411 uint16_t usTemperatureLimitVrVddc;
412 uint16_t usTemperatureLimitVrMvdd;
413 uint16_t usTemperatureLimitPlx;
414 uint8_t ucLiquid1_I2C_address;
415 uint8_t ucLiquid2_I2C_address;
416 uint8_t ucLiquid_I2C_Line;
417 uint8_t ucVr_I2C_address;
418 uint8_t ucVr_I2C_Line;
419 uint8_t ucPlx_I2C_address;
420 uint8_t ucPlx_I2C_Line;
421 uint32_t usBoostPowerLimit;
422 uint8_t ucCKS_LDO_REFSEL;
423};
424
425struct phm_tdp_table {
426 uint16_t usTDP;
427 uint16_t usConfigurableTDP;
428 uint16_t usTDC;
429 uint16_t usBatteryPowerLimit;
430 uint16_t usSmallPowerLimit;
431 uint16_t usLowCACLeakage;
432 uint16_t usHighCACLeakage;
433 uint16_t usMaximumPowerDeliveryLimit;
434 uint16_t usEDCLimit;
435 uint16_t usOperatingTempMinLimit;
436 uint16_t usOperatingTempMaxLimit;
437 uint16_t usOperatingTempStep;
438 uint16_t usOperatingTempHyst;
439 uint16_t usDefaultTargetOperatingTemp;
440 uint16_t usTargetOperatingTemp;
441 uint16_t usPowerTuneDataSetID;
442 uint16_t usSoftwareShutdownTemp;
443 uint16_t usClockStretchAmount;
444 uint16_t usTemperatureLimitTedge;
445 uint16_t usTemperatureLimitHotspot;
446 uint16_t usTemperatureLimitLiquid1;
447 uint16_t usTemperatureLimitLiquid2;
448 uint16_t usTemperatureLimitHBM;
449 uint16_t usTemperatureLimitVrVddc;
450 uint16_t usTemperatureLimitVrMvdd;
451 uint16_t usTemperatureLimitPlx;
452 uint8_t ucLiquid1_I2C_address;
453 uint8_t ucLiquid2_I2C_address;
454 uint8_t ucLiquid_I2C_Line;
455 uint8_t ucVr_I2C_address;
456 uint8_t ucVr_I2C_Line;
457 uint8_t ucPlx_I2C_address;
458 uint8_t ucPlx_I2C_Line;
459 uint8_t ucLiquid_I2C_LineSDA;
460 uint8_t ucVr_I2C_LineSDA;
461 uint8_t ucPlx_I2C_LineSDA;
462 uint32_t usBoostPowerLimit;
463 uint16_t usBoostStartTemperature;
464 uint16_t usBoostStopTemperature;
465 uint32_t ulBoostClock;
466};
467
468struct phm_ppm_table {
469 uint8_t ppm_design;
470 uint16_t cpu_core_number;
471 uint32_t platform_tdp;
472 uint32_t small_ac_platform_tdp;
473 uint32_t platform_tdc;
474 uint32_t small_ac_platform_tdc;
475 uint32_t apu_tdp;
476 uint32_t dgpu_tdp;
477 uint32_t dgpu_ulv_power;
478 uint32_t tj_max;
479};
480
481struct phm_vq_budgeting_record {
482 uint32_t ulCUs;
483 uint32_t ulSustainableSOCPowerLimitLow;
484 uint32_t ulSustainableSOCPowerLimitHigh;
485 uint32_t ulMinSclkLow;
486 uint32_t ulMinSclkHigh;
487 uint8_t ucDispConfig;
488 uint32_t ulDClk;
489 uint32_t ulEClk;
490 uint32_t ulSustainableSclk;
491 uint32_t ulSustainableCUs;
492};
493
494struct phm_vq_budgeting_table {
495 uint8_t numEntries;
496 struct phm_vq_budgeting_record entries[1];
497};
498
499struct phm_clock_and_voltage_limits {
500 uint32_t sclk;
501 uint32_t mclk;
502 uint32_t gfxclk;
503 uint16_t vddc;
504 uint16_t vddci;
505 uint16_t vddgfx;
506 uint16_t vddmem;
507};
508
509
510
511struct phm_ppt_v1_information {
512 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
513 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
514 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
515 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
516 struct phm_clock_array *valid_sclk_values;
517 struct phm_clock_array *valid_mclk_values;
518 struct phm_clock_array *valid_socclk_values;
519 struct phm_clock_array *valid_dcefclk_values;
520 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
521 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
522 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
523 struct phm_ppm_table *ppm_parameter_table;
524 struct phm_cac_tdp_table *cac_dtp_table;
525 struct phm_tdp_table *tdp_table;
526 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
527 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
528 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
529 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
530 struct phm_ppt_v1_pcie_table *pcie_table;
531 struct phm_ppt_v1_gpio_table *gpio_table;
532 uint16_t us_ulv_voltage_offset;
533 uint16_t us_ulv_smnclk_did;
534 uint16_t us_ulv_mp1clk_did;
535 uint16_t us_ulv_gfxclk_bypass;
536 uint16_t us_gfxclk_slew_rate;
537 uint16_t us_min_gfxclk_freq_limit;
538};
539
540struct phm_ppt_v2_information {
541 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
542 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
543 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
544 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
545 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
546 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
547 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
548 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
549
550 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
551
552 struct phm_clock_array *valid_sclk_values;
553 struct phm_clock_array *valid_mclk_values;
554 struct phm_clock_array *valid_socclk_values;
555 struct phm_clock_array *valid_dcefclk_values;
556
557 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
558 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
559
560 struct phm_ppm_table *ppm_parameter_table;
561 struct phm_cac_tdp_table *cac_dtp_table;
562 struct phm_tdp_table *tdp_table;
563
564 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
565 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
566 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
567 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
568
569 struct phm_ppt_v1_pcie_table *pcie_table;
570
571 uint16_t us_ulv_voltage_offset;
572 uint16_t us_ulv_smnclk_did;
573 uint16_t us_ulv_mp1clk_did;
574 uint16_t us_ulv_gfxclk_bypass;
575 uint16_t us_gfxclk_slew_rate;
576 uint16_t us_min_gfxclk_freq_limit;
577
578 uint8_t uc_gfx_dpm_voltage_mode;
579 uint8_t uc_soc_dpm_voltage_mode;
580 uint8_t uc_uclk_dpm_voltage_mode;
581 uint8_t uc_uvd_dpm_voltage_mode;
582 uint8_t uc_vce_dpm_voltage_mode;
583 uint8_t uc_mp0_dpm_voltage_mode;
584 uint8_t uc_dcef_dpm_voltage_mode;
585};
586
587struct phm_ppt_v3_information
588{
589 uint8_t uc_thermal_controller_type;
590
591 uint16_t us_small_power_limit1;
592 uint16_t us_small_power_limit2;
593 uint16_t us_boost_power_limit;
594
595 uint16_t us_od_turbo_power_limit;
596 uint16_t us_od_powersave_power_limit;
597 uint16_t us_software_shutdown_temp;
598
599 uint32_t *power_saving_clock_max;
600 uint32_t *power_saving_clock_min;
601
602 uint8_t *od_feature_capabilities;
603 uint32_t *od_settings_max;
604 uint32_t *od_settings_min;
605
606 void *smc_pptable;
607};
608
609struct phm_dynamic_state_info {
610 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
611 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
612 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
613 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
614 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
615 struct phm_clock_array *valid_sclk_values;
616 struct phm_clock_array *valid_mclk_values;
617 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
618 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
619 uint32_t mclk_sclk_ratio;
620 uint32_t sclk_mclk_delta;
621 uint32_t vddc_vddci_delta;
622 uint32_t min_vddc_for_pcie_gen2;
623 struct phm_cac_leakage_table *cac_leakage_table;
624 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
625
626 struct phm_vce_clock_voltage_dependency_table
627 *vce_clock_voltage_dependency_table;
628 struct phm_uvd_clock_voltage_dependency_table
629 *uvd_clock_voltage_dependency_table;
630 struct phm_acp_clock_voltage_dependency_table
631 *acp_clock_voltage_dependency_table;
632 struct phm_samu_clock_voltage_dependency_table
633 *samu_clock_voltage_dependency_table;
634
635 struct phm_ppm_table *ppm_parameter_table;
636 struct phm_cac_tdp_table *cac_dtp_table;
637 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
638};
639
640struct pp_fan_info {
641 bool bNoFan;
642 uint8_t ucTachometerPulsesPerRevolution;
643 uint32_t ulMinRPM;
644 uint32_t ulMaxRPM;
645};
646
647struct pp_advance_fan_control_parameters {
648 uint16_t usTMin;
649 uint16_t usTMed;
650 uint16_t usTHigh;
651 uint16_t usPWMMin;
652 uint16_t usPWMMed;
653 uint16_t usPWMHigh;
654 uint8_t ucTHyst;
655 uint32_t ulCycleDelay;
656 uint16_t usTMax;
657 uint8_t ucFanControlMode;
658 uint16_t usFanPWMMinLimit;
659 uint16_t usFanPWMMaxLimit;
660 uint16_t usFanPWMStep;
661 uint16_t usDefaultMaxFanPWM;
662 uint16_t usFanOutputSensitivity;
663 uint16_t usDefaultFanOutputSensitivity;
664 uint16_t usMaxFanPWM;
665 uint16_t usFanRPMMinLimit;
666 uint16_t usFanRPMMaxLimit;
667 uint16_t usFanRPMStep;
668 uint16_t usDefaultMaxFanRPM;
669 uint16_t usMaxFanRPM;
670 uint16_t usFanCurrentLow;
671 uint16_t usFanCurrentHigh;
672 uint16_t usFanRPMLow;
673 uint16_t usFanRPMHigh;
674 uint32_t ulMinFanSCLKAcousticLimit;
675 uint8_t ucTargetTemperature;
676 uint8_t ucMinimumPWMLimit;
677 uint16_t usFanGainEdge;
678 uint16_t usFanGainHotspot;
679 uint16_t usFanGainLiquid;
680 uint16_t usFanGainVrVddc;
681 uint16_t usFanGainVrMvdd;
682 uint16_t usFanGainPlx;
683 uint16_t usFanGainHbm;
684 uint8_t ucEnableZeroRPM;
685 uint8_t ucFanStopTemperature;
686 uint8_t ucFanStartTemperature;
687 uint32_t ulMaxFanSCLKAcousticLimit;
688 uint32_t ulTargetGfxClk;
689 uint16_t usZeroRPMStartTemperature;
690 uint16_t usZeroRPMStopTemperature;
691 uint16_t usMGpuThrottlingRPMLimit;
692};
693
694struct pp_thermal_controller_info {
695 uint8_t ucType;
696 uint8_t ucI2cLine;
697 uint8_t ucI2cAddress;
698 uint8_t use_hw_fan_control;
699 struct pp_fan_info fanInfo;
700 struct pp_advance_fan_control_parameters advanceFanControlParameters;
701};
702
703struct phm_microcode_version_info {
704 uint32_t SMC;
705 uint32_t DMCU;
706 uint32_t MC;
707 uint32_t NB;
708};
709
710enum PP_TABLE_VERSION {
711 PP_TABLE_V0 = 0,
712 PP_TABLE_V1,
713 PP_TABLE_V2,
714 PP_TABLE_MAX
715};
716
717
718
719
720#define Workload_Policy_Max 6
721
722struct pp_hwmgr {
723 void *adev;
724 uint32_t chip_family;
725 uint32_t chip_id;
726 uint32_t smu_version;
727 bool not_vf;
728 bool pm_en;
729 struct mutex smu_lock;
730
731 uint32_t pp_table_version;
732 void *device;
733 struct pp_smumgr *smumgr;
734 const void *soft_pp_table;
735 uint32_t soft_pp_table_size;
736 void *hardcode_pp_table;
737 bool need_pp_table_upload;
738
739 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
740 uint32_t num_vce_state_tables;
741
742 enum amd_dpm_forced_level dpm_level;
743 enum amd_dpm_forced_level saved_dpm_level;
744 enum amd_dpm_forced_level request_dpm_level;
745 uint32_t usec_timeout;
746 void *pptable;
747 struct phm_platform_descriptor platform_descriptor;
748 void *backend;
749
750 void *smu_backend;
751 const struct pp_smumgr_func *smumgr_funcs;
752 bool is_kicker;
753
754 enum PP_DAL_POWERLEVEL dal_power_level;
755 struct phm_dynamic_state_info dyn_state;
756 const struct pp_hwmgr_func *hwmgr_func;
757 const struct pp_table_func *pptable_func;
758
759 struct pp_power_state *ps;
760 uint32_t num_ps;
761 struct pp_thermal_controller_info thermal_controller;
762 bool fan_ctrl_is_in_default_mode;
763 uint32_t fan_ctrl_default_mode;
764 bool fan_ctrl_enabled;
765 uint32_t tmin;
766 struct phm_microcode_version_info microcode_version_info;
767 uint32_t ps_size;
768 struct pp_power_state *current_ps;
769 struct pp_power_state *request_ps;
770 struct pp_power_state *boot_ps;
771 struct pp_power_state *uvd_ps;
772 const struct amd_pp_display_configuration *display_config;
773 uint32_t feature_mask;
774 bool avfs_supported;
775
776 bool en_umd_pstate;
777 uint32_t power_profile_mode;
778 uint32_t default_power_profile_mode;
779 uint32_t pstate_sclk;
780 uint32_t pstate_mclk;
781 bool od_enabled;
782 uint32_t power_limit;
783 uint32_t default_power_limit;
784 uint32_t workload_mask;
785 uint32_t workload_prority[Workload_Policy_Max];
786 uint32_t workload_setting[Workload_Policy_Max];
787 bool gfxoff_state_changed_by_workload;
788};
789
790int hwmgr_early_init(struct pp_hwmgr *hwmgr);
791int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
792int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
793int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
794int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
795int hwmgr_suspend(struct pp_hwmgr *hwmgr);
796int hwmgr_resume(struct pp_hwmgr *hwmgr);
797
798int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
799 enum amd_pp_task task_id,
800 enum amd_pm_state_type *user_state);
801
802
803#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
804
805
806#endif
807
