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24#ifndef SMU11_DRIVER_IF_H
25#define SMU11_DRIVER_IF_H
26
27
28
29
30#define SMU11_DRIVER_IF_VERSION 0x13
31
32#define PPTABLE_V20_SMU_VERSION 3
33
34#define NUM_GFXCLK_DPM_LEVELS 16
35#define NUM_VCLK_DPM_LEVELS 8
36#define NUM_DCLK_DPM_LEVELS 8
37#define NUM_ECLK_DPM_LEVELS 8
38#define NUM_MP0CLK_DPM_LEVELS 2
39#define NUM_SOCCLK_DPM_LEVELS 8
40#define NUM_UCLK_DPM_LEVELS 4
41#define NUM_FCLK_DPM_LEVELS 8
42#define NUM_DCEFCLK_DPM_LEVELS 8
43#define NUM_DISPCLK_DPM_LEVELS 8
44#define NUM_PIXCLK_DPM_LEVELS 8
45#define NUM_PHYCLK_DPM_LEVELS 8
46#define NUM_LINK_LEVELS 2
47#define NUM_XGMI_LEVELS 2
48
49#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
50#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
51#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
52#define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1)
53#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
55#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
56#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
57#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
58#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
59#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
60#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
61#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
62#define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
63
64#define PPSMC_GeminiModeNone 0
65#define PPSMC_GeminiModeMaster 1
66#define PPSMC_GeminiModeSlave 2
67
68
69#define FEATURE_DPM_PREFETCHER_BIT 0
70#define FEATURE_DPM_GFXCLK_BIT 1
71#define FEATURE_DPM_UCLK_BIT 2
72#define FEATURE_DPM_SOCCLK_BIT 3
73#define FEATURE_DPM_UVD_BIT 4
74#define FEATURE_DPM_VCE_BIT 5
75#define FEATURE_ULV_BIT 6
76#define FEATURE_DPM_MP0CLK_BIT 7
77#define FEATURE_DPM_LINK_BIT 8
78#define FEATURE_DPM_DCEFCLK_BIT 9
79#define FEATURE_DS_GFXCLK_BIT 10
80#define FEATURE_DS_SOCCLK_BIT 11
81#define FEATURE_DS_LCLK_BIT 12
82#define FEATURE_PPT_BIT 13
83#define FEATURE_TDC_BIT 14
84#define FEATURE_THERMAL_BIT 15
85#define FEATURE_GFX_PER_CU_CG_BIT 16
86#define FEATURE_RM_BIT 17
87#define FEATURE_DS_DCEFCLK_BIT 18
88#define FEATURE_ACDC_BIT 19
89#define FEATURE_VR0HOT_BIT 20
90#define FEATURE_VR1HOT_BIT 21
91#define FEATURE_FW_CTF_BIT 22
92#define FEATURE_LED_DISPLAY_BIT 23
93#define FEATURE_FAN_CONTROL_BIT 24
94#define FEATURE_GFX_EDC_BIT 25
95#define FEATURE_GFXOFF_BIT 26
96#define FEATURE_CG_BIT 27
97#define FEATURE_DPM_FCLK_BIT 28
98#define FEATURE_DS_FCLK_BIT 29
99#define FEATURE_DS_MP1CLK_BIT 30
100#define FEATURE_DS_MP0CLK_BIT 31
101#define FEATURE_XGMI_BIT 32
102#define FEATURE_ECC_BIT 33
103#define FEATURE_SPARE_34_BIT 34
104#define FEATURE_SPARE_35_BIT 35
105#define FEATURE_SPARE_36_BIT 36
106#define FEATURE_SPARE_37_BIT 37
107#define FEATURE_SPARE_38_BIT 38
108#define FEATURE_SPARE_39_BIT 39
109#define FEATURE_SPARE_40_BIT 40
110#define FEATURE_SPARE_41_BIT 41
111#define FEATURE_SPARE_42_BIT 42
112#define FEATURE_SPARE_43_BIT 43
113#define FEATURE_SPARE_44_BIT 44
114#define FEATURE_SPARE_45_BIT 45
115#define FEATURE_SPARE_46_BIT 46
116#define FEATURE_SPARE_47_BIT 47
117#define FEATURE_SPARE_48_BIT 48
118#define FEATURE_SPARE_49_BIT 49
119#define FEATURE_SPARE_50_BIT 50
120#define FEATURE_SPARE_51_BIT 51
121#define FEATURE_SPARE_52_BIT 52
122#define FEATURE_SPARE_53_BIT 53
123#define FEATURE_SPARE_54_BIT 54
124#define FEATURE_SPARE_55_BIT 55
125#define FEATURE_SPARE_56_BIT 56
126#define FEATURE_SPARE_57_BIT 57
127#define FEATURE_SPARE_58_BIT 58
128#define FEATURE_SPARE_59_BIT 59
129#define FEATURE_SPARE_60_BIT 60
130#define FEATURE_SPARE_61_BIT 61
131#define FEATURE_SPARE_62_BIT 62
132#define FEATURE_SPARE_63_BIT 63
133
134#define NUM_FEATURES 64
135
136#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
137#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
138#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
139#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
140#define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
141#define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
142#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
143#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
144#define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
145#define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
146#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
147#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
148#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
149#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
150#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
151#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
152#define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
153#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT )
154#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
155#define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
156#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
157#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
158#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
159#define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
160#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
161#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
162#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT )
163#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT )
164#define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT )
165#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
166#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
167#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
168#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT )
169#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
170
171#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
172#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
173#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004
174#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008
175#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010
176#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020
177#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040
178#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080
179#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100
180#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200
181#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400
182#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800
183#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
184#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000
185#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000
186#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000
187#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
188#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000
189
190#define I2C_CONTROLLER_ENABLED 1
191#define I2C_CONTROLLER_DISABLED 0
192
193#define VR_MAPPING_VR_SELECT_MASK 0x01
194#define VR_MAPPING_VR_SELECT_SHIFT 0x00
195
196#define VR_MAPPING_PLANE_SELECT_MASK 0x02
197#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
198
199
200#define PSI_SEL_VR0_PLANE0_PSI0 0x01
201#define PSI_SEL_VR0_PLANE0_PSI1 0x02
202#define PSI_SEL_VR0_PLANE1_PSI0 0x04
203#define PSI_SEL_VR0_PLANE1_PSI1 0x08
204#define PSI_SEL_VR1_PLANE0_PSI0 0x10
205#define PSI_SEL_VR1_PLANE0_PSI1 0x20
206#define PSI_SEL_VR1_PLANE1_PSI0 0x40
207#define PSI_SEL_VR1_PLANE1_PSI1 0x80
208
209
210#define THROTTLER_STATUS_PADDING_BIT 0
211#define THROTTLER_STATUS_TEMP_EDGE_BIT 1
212#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
213#define THROTTLER_STATUS_TEMP_HBM_BIT 3
214#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
215#define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5
216#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
217#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
218#define THROTTLER_STATUS_TEMP_LIQUID_BIT 8
219#define THROTTLER_STATUS_TEMP_PLX_BIT 9
220#define THROTTLER_STATUS_TEMP_SKIN_BIT 10
221#define THROTTLER_STATUS_TDC_GFX_BIT 11
222#define THROTTLER_STATUS_TDC_SOC_BIT 12
223#define THROTTLER_STATUS_PPT_BIT 13
224#define THROTTLER_STATUS_FIT_BIT 14
225#define THROTTLER_STATUS_PPM_BIT 15
226
227
228#define TABLE_TRANSFER_OK 0x0
229#define TABLE_TRANSFER_FAILED 0xFF
230
231
232#define WORKLOAD_DEFAULT_BIT 0
233#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
234#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
235#define WORKLOAD_PPLIB_VIDEO_BIT 3
236#define WORKLOAD_PPLIB_VR_BIT 4
237#define WORKLOAD_PPLIB_COMPUTE_BIT 5
238#define WORKLOAD_PPLIB_CUSTOM_BIT 6
239#define WORKLOAD_PPLIB_COUNT 7
240
241
242#define XGMI_STATE_D0 1
243#define XGMI_STATE_D3 0
244
245typedef enum {
246 I2C_CONTROLLER_PORT_0 = 0,
247 I2C_CONTROLLER_PORT_1 = 1,
248} I2cControllerPort_e;
249
250typedef enum {
251 I2C_CONTROLLER_NAME_VR_GFX = 0,
252 I2C_CONTROLLER_NAME_VR_SOC,
253 I2C_CONTROLLER_NAME_VR_VDDCI,
254 I2C_CONTROLLER_NAME_VR_HBM,
255 I2C_CONTROLLER_NAME_LIQUID_0,
256 I2C_CONTROLLER_NAME_LIQUID_1,
257 I2C_CONTROLLER_NAME_PLX,
258 I2C_CONTROLLER_NAME_COUNT,
259} I2cControllerName_e;
260
261typedef enum {
262 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
263 I2C_CONTROLLER_THROTTLER_VR_GFX,
264 I2C_CONTROLLER_THROTTLER_VR_SOC,
265 I2C_CONTROLLER_THROTTLER_VR_VDDCI,
266 I2C_CONTROLLER_THROTTLER_VR_HBM,
267 I2C_CONTROLLER_THROTTLER_LIQUID_0,
268 I2C_CONTROLLER_THROTTLER_LIQUID_1,
269 I2C_CONTROLLER_THROTTLER_PLX,
270} I2cControllerThrottler_e;
271
272typedef enum {
273 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
274 I2C_CONTROLLER_PROTOCOL_VR_IR35217,
275 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
276 I2C_CONTROLLER_PROTOCOL_SPARE_0,
277 I2C_CONTROLLER_PROTOCOL_SPARE_1,
278 I2C_CONTROLLER_PROTOCOL_SPARE_2,
279} I2cControllerProtocol_e;
280
281typedef enum {
282 I2C_CONTROLLER_SPEED_SLOW = 0,
283 I2C_CONTROLLER_SPEED_FAST = 1,
284} I2cControllerSpeed_e;
285
286typedef struct {
287 uint32_t Enabled;
288 uint32_t SlaveAddress;
289 uint32_t ControllerPort;
290 uint32_t ControllerName;
291
292 uint32_t ThermalThrottler;
293 uint32_t I2cProtocol;
294 uint32_t I2cSpeed;
295} I2cControllerConfig_t;
296
297typedef struct {
298 uint32_t a;
299 uint32_t b;
300 uint32_t c;
301} QuadraticInt_t;
302
303typedef struct {
304 uint32_t m;
305 uint32_t b;
306} LinearInt_t;
307
308typedef struct {
309 uint32_t a;
310 uint32_t b;
311 uint32_t c;
312} DroopInt_t;
313
314typedef enum {
315 PPCLK_GFXCLK,
316 PPCLK_VCLK,
317 PPCLK_DCLK,
318 PPCLK_ECLK,
319 PPCLK_SOCCLK,
320 PPCLK_UCLK,
321 PPCLK_DCEFCLK,
322 PPCLK_DISPCLK,
323 PPCLK_PIXCLK,
324 PPCLK_PHYCLK,
325 PPCLK_FCLK,
326 PPCLK_COUNT,
327} PPCLK_e;
328
329typedef enum {
330 POWER_SOURCE_AC,
331 POWER_SOURCE_DC,
332 POWER_SOURCE_COUNT,
333} POWER_SOURCE_e;
334
335typedef enum {
336 VOLTAGE_MODE_AVFS = 0,
337 VOLTAGE_MODE_AVFS_SS,
338 VOLTAGE_MODE_SS,
339 VOLTAGE_MODE_COUNT,
340} VOLTAGE_MODE_e;
341
342
343typedef enum {
344 AVFS_VOLTAGE_GFX = 0,
345 AVFS_VOLTAGE_SOC,
346 AVFS_VOLTAGE_COUNT,
347} AVFS_VOLTAGE_TYPE_e;
348
349
350typedef struct {
351 uint8_t VoltageMode;
352 uint8_t SnapToDiscrete;
353 uint8_t NumDiscreteLevels;
354 uint8_t padding;
355 LinearInt_t ConversionToAvfsClk;
356 QuadraticInt_t SsCurve;
357} DpmDescriptor_t;
358
359typedef struct {
360 uint32_t Version;
361
362
363 uint32_t FeaturesToRun[2];
364
365
366 uint16_t SocketPowerLimitAc0;
367 uint16_t SocketPowerLimitAc0Tau;
368 uint16_t SocketPowerLimitAc1;
369 uint16_t SocketPowerLimitAc1Tau;
370 uint16_t SocketPowerLimitAc2;
371 uint16_t SocketPowerLimitAc2Tau;
372 uint16_t SocketPowerLimitAc3;
373 uint16_t SocketPowerLimitAc3Tau;
374 uint16_t SocketPowerLimitDc;
375 uint16_t SocketPowerLimitDcTau;
376 uint16_t TdcLimitSoc;
377 uint16_t TdcLimitSocTau;
378 uint16_t TdcLimitGfx;
379 uint16_t TdcLimitGfxTau;
380
381 uint16_t TedgeLimit;
382 uint16_t ThotspotLimit;
383 uint16_t ThbmLimit;
384 uint16_t Tvr_gfxLimit;
385 uint16_t Tvr_memLimit;
386 uint16_t Tliquid1Limit;
387 uint16_t Tliquid2Limit;
388 uint16_t TplxLimit;
389 uint32_t FitLimit;
390
391 uint16_t PpmPowerLimit;
392 uint16_t PpmTemperatureThreshold;
393
394 uint8_t MemoryOnPackage;
395 uint8_t padding8_limits;
396 uint16_t Tvr_SocLimit;
397
398 uint16_t UlvVoltageOffsetSoc;
399 uint16_t UlvVoltageOffsetGfx;
400
401 uint8_t UlvSmnclkDid;
402 uint8_t UlvMp1clkDid;
403 uint8_t UlvGfxclkBypass;
404 uint8_t Padding234;
405
406
407 uint16_t MinVoltageGfx;
408 uint16_t MinVoltageSoc;
409 uint16_t MaxVoltageGfx;
410 uint16_t MaxVoltageSoc;
411
412 uint16_t LoadLineResistanceGfx;
413 uint16_t LoadLineResistanceSoc;
414
415 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
416
417 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
418 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
419 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
420 uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ];
421 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
422 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
423 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
424 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
425 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
426 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
427 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
428
429 uint16_t DcModeMaxFreq [PPCLK_COUNT ];
430 uint16_t Padding8_Clks;
431
432 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
433 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
434
435
436 uint16_t GfxclkFidle;
437 uint16_t GfxclkSlewRate;
438 uint16_t CksEnableFreq;
439 uint16_t Padding789;
440 QuadraticInt_t CksVoltageOffset;
441 uint8_t Padding567[4];
442 uint16_t GfxclkDsMaxFreq;
443 uint8_t GfxclkSource;
444 uint8_t Padding456;
445
446 uint8_t LowestUclkReservedForUlv;
447 uint8_t Padding8_Uclk[3];
448
449
450 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
451 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
452 uint16_t LclkFreq[NUM_LINK_LEVELS];
453
454
455 uint16_t EnableTdpm;
456 uint16_t TdpmHighHystTemperature;
457 uint16_t TdpmLowHystTemperature;
458 uint16_t GfxclkFreqHighTempLimit;
459
460
461 uint16_t FanStopTemp;
462 uint16_t FanStartTemp;
463
464 uint16_t FanGainEdge;
465 uint16_t FanGainHotspot;
466 uint16_t FanGainLiquid;
467 uint16_t FanGainVrGfx;
468 uint16_t FanGainVrSoc;
469 uint16_t FanGainPlx;
470 uint16_t FanGainHbm;
471 uint16_t FanPwmMin;
472 uint16_t FanAcousticLimitRpm;
473 uint16_t FanThrottlingRpm;
474 uint16_t FanMaximumRpm;
475 uint16_t FanTargetTemperature;
476 uint16_t FanTargetGfxclk;
477 uint8_t FanZeroRpmEnable;
478 uint8_t FanTachEdgePerRev;
479
480
481
482 int16_t FuzzyFan_ErrorSetDelta;
483 int16_t FuzzyFan_ErrorRateSetDelta;
484 int16_t FuzzyFan_PwmSetDelta;
485 uint16_t FuzzyFan_Reserved;
486
487
488 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
489 uint8_t Padding8_Avfs[2];
490
491 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT];
492 DroopInt_t dBtcGbGfxCksOn;
493 DroopInt_t dBtcGbGfxCksOff;
494 DroopInt_t dBtcGbGfxAfll;
495 DroopInt_t dBtcGbSoc;
496 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT];
497
498 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
499
500 uint16_t DcTol[AVFS_VOLTAGE_COUNT];
501
502 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
503 uint8_t Padding8_GfxBtc[2];
504
505 int16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
506 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
507
508
509 uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS];
510 uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS];
511 uint16_t XgmiFclkFreq [NUM_XGMI_LEVELS];
512 uint16_t XgmiUclkFreq [NUM_XGMI_LEVELS];
513 uint16_t XgmiSocclkFreq [NUM_XGMI_LEVELS];
514 uint16_t XgmiSocVoltage [NUM_XGMI_LEVELS];
515
516 uint32_t DebugOverrides;
517 QuadraticInt_t ReservedEquation0;
518 QuadraticInt_t ReservedEquation1;
519 QuadraticInt_t ReservedEquation2;
520 QuadraticInt_t ReservedEquation3;
521
522 uint16_t MinVoltageUlvGfx;
523 uint16_t MinVoltageUlvSoc;
524
525 uint16_t MGpuFanBoostLimitRpm;
526 uint16_t padding16_Fan;
527
528 uint16_t FanGainVrMem0;
529 uint16_t FanGainVrMem1;
530
531 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
532
533 uint32_t Reserved[11];
534
535 uint32_t Padding32[3];
536
537 uint16_t MaxVoltageStepGfx;
538 uint16_t MaxVoltageStepSoc;
539
540 uint8_t VddGfxVrMapping;
541 uint8_t VddSocVrMapping;
542 uint8_t VddMem0VrMapping;
543 uint8_t VddMem1VrMapping;
544
545 uint8_t GfxUlvPhaseSheddingMask;
546 uint8_t SocUlvPhaseSheddingMask;
547 uint8_t ExternalSensorPresent;
548 uint8_t Padding8_V;
549
550
551 uint16_t GfxMaxCurrent;
552 int8_t GfxOffset;
553 uint8_t Padding_TelemetryGfx;
554
555 uint16_t SocMaxCurrent;
556 int8_t SocOffset;
557 uint8_t Padding_TelemetrySoc;
558
559 uint16_t Mem0MaxCurrent;
560 int8_t Mem0Offset;
561 uint8_t Padding_TelemetryMem0;
562
563 uint16_t Mem1MaxCurrent;
564 int8_t Mem1Offset;
565 uint8_t Padding_TelemetryMem1;
566
567
568 uint8_t AcDcGpio;
569 uint8_t AcDcPolarity;
570 uint8_t VR0HotGpio;
571 uint8_t VR0HotPolarity;
572
573 uint8_t VR1HotGpio;
574 uint8_t VR1HotPolarity;
575 uint8_t Padding1;
576 uint8_t Padding2;
577
578
579
580 uint8_t LedPin0;
581 uint8_t LedPin1;
582 uint8_t LedPin2;
583 uint8_t padding8_4;
584
585
586 uint8_t PllGfxclkSpreadEnabled;
587 uint8_t PllGfxclkSpreadPercent;
588 uint16_t PllGfxclkSpreadFreq;
589
590 uint8_t UclkSpreadEnabled;
591 uint8_t UclkSpreadPercent;
592 uint16_t UclkSpreadFreq;
593
594 uint8_t FclkSpreadEnabled;
595 uint8_t FclkSpreadPercent;
596 uint16_t FclkSpreadFreq;
597
598 uint8_t FllGfxclkSpreadEnabled;
599 uint8_t FllGfxclkSpreadPercent;
600 uint16_t FllGfxclkSpreadFreq;
601
602 I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
603
604 uint32_t BoardReserved[10];
605
606
607 uint32_t MmHubPadding[8];
608
609} PPTable_t;
610
611typedef struct {
612
613 uint16_t GfxclkAverageLpfTau;
614 uint16_t SocclkAverageLpfTau;
615 uint16_t UclkAverageLpfTau;
616 uint16_t GfxActivityLpfTau;
617 uint16_t UclkActivityLpfTau;
618 uint16_t SocketPowerLpfTau;
619
620
621 uint32_t MmHubPadding[8];
622} DriverSmuConfig_t;
623
624typedef struct {
625
626 uint16_t GfxclkFmin;
627 uint16_t GfxclkFmax;
628 uint16_t GfxclkFreq1;
629 uint16_t GfxclkVolt1;
630 uint16_t GfxclkFreq2;
631 uint16_t GfxclkVolt2;
632 uint16_t GfxclkFreq3;
633 uint16_t GfxclkVolt3;
634 uint16_t UclkFmax;
635 int16_t OverDrivePct;
636 uint16_t FanMaximumRpm;
637 uint16_t FanMinimumPwm;
638 uint16_t FanTargetTemperature;
639 uint16_t MaxOpTemp;
640 uint16_t FanZeroRpmEnable;
641 uint16_t Padding;
642
643} OverDriveTable_t;
644
645typedef struct {
646 uint16_t CurrClock[PPCLK_COUNT];
647 uint16_t AverageGfxclkFrequency;
648 uint16_t AverageSocclkFrequency;
649 uint16_t AverageUclkFrequency ;
650 uint16_t AverageGfxActivity ;
651 uint16_t AverageUclkActivity ;
652 uint8_t CurrSocVoltageOffset ;
653 uint8_t CurrGfxVoltageOffset ;
654 uint8_t CurrMemVidOffset ;
655 uint8_t Padding8 ;
656 uint16_t CurrSocketPower ;
657 uint16_t TemperatureEdge ;
658 uint16_t TemperatureHotspot ;
659 uint16_t TemperatureHBM ;
660 uint16_t TemperatureVrGfx ;
661 uint16_t TemperatureVrSoc ;
662 uint16_t TemperatureVrMem0 ;
663 uint16_t TemperatureVrMem1 ;
664 uint16_t TemperatureLiquid ;
665 uint16_t TemperaturePlx ;
666 uint32_t ThrottlerStatus ;
667
668 uint8_t LinkDpmLevel;
669 uint16_t AverageSocketPower;
670 uint8_t Padding;
671
672
673 uint32_t MmHubPadding[7];
674} SmuMetrics_t;
675
676typedef struct {
677 uint16_t MinClock;
678 uint16_t MaxClock;
679 uint16_t MinUclk;
680 uint16_t MaxUclk;
681
682 uint8_t WmSetting;
683 uint8_t Padding[3];
684} WatermarkRowGeneric_t;
685
686#define NUM_WM_RANGES 4
687
688typedef enum {
689 WM_SOCCLK = 0,
690 WM_DCEFCLK,
691 WM_COUNT_PP,
692} WM_CLOCK_e;
693
694typedef struct {
695
696 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
697
698 uint32_t MmHubPadding[7];
699} Watermarks_t;
700
701typedef struct {
702 uint16_t avgPsmCount[45];
703 uint16_t minPsmCount[45];
704 float avgPsmVoltage[45];
705 float minPsmVoltage[45];
706
707 uint16_t avgScsPsmCount;
708 uint16_t minScsPsmCount;
709 float avgScsPsmVoltage;
710 float minScsPsmVoltage;
711
712
713 uint32_t MmHubPadding[6];
714} AvfsDebugTable_t;
715
716typedef struct {
717 uint8_t AvfsVersion;
718 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
719
720 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
721 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
722
723 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
724 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
725 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
726 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
727
728 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT];
729 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT];
730 int32_t VFT0_b[AVFS_VOLTAGE_COUNT];
731
732 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT];
733 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT];
734 int32_t VFT1_b[AVFS_VOLTAGE_COUNT];
735
736 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT];
737 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT];
738 int32_t VFT2_b[AVFS_VOLTAGE_COUNT];
739
740 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT];
741 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT];
742 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];
743
744 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT];
745 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT];
746 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];
747
748 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
749 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
750 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
751
752 uint32_t VInversion[AVFS_VOLTAGE_COUNT];
753
754
755 int32_t P2V_m1[AVFS_VOLTAGE_COUNT];
756 int32_t P2V_m2[AVFS_VOLTAGE_COUNT];
757 int32_t P2V_b[AVFS_VOLTAGE_COUNT];
758
759 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];
760
761 uint32_t EnabledAvfsModules;
762
763 uint32_t MmHubPadding[7];
764} AvfsFuseOverride_t;
765
766typedef struct {
767
768 uint8_t Gfx_ActiveHystLimit;
769 uint8_t Gfx_IdleHystLimit;
770 uint8_t Gfx_FPS;
771 uint8_t Gfx_MinActiveFreqType;
772 uint8_t Gfx_BoosterFreqType;
773 uint8_t Gfx_UseRlcBusy;
774 uint16_t Gfx_MinActiveFreq;
775 uint16_t Gfx_BoosterFreq;
776 uint16_t Gfx_PD_Data_time_constant;
777 uint32_t Gfx_PD_Data_limit_a;
778 uint32_t Gfx_PD_Data_limit_b;
779 uint32_t Gfx_PD_Data_limit_c;
780 uint32_t Gfx_PD_Data_error_coeff;
781 uint32_t Gfx_PD_Data_error_rate_coeff;
782
783 uint8_t Soc_ActiveHystLimit;
784 uint8_t Soc_IdleHystLimit;
785 uint8_t Soc_FPS;
786 uint8_t Soc_MinActiveFreqType;
787 uint8_t Soc_BoosterFreqType;
788 uint8_t Soc_UseRlcBusy;
789 uint16_t Soc_MinActiveFreq;
790 uint16_t Soc_BoosterFreq;
791 uint16_t Soc_PD_Data_time_constant;
792 uint32_t Soc_PD_Data_limit_a;
793 uint32_t Soc_PD_Data_limit_b;
794 uint32_t Soc_PD_Data_limit_c;
795 uint32_t Soc_PD_Data_error_coeff;
796 uint32_t Soc_PD_Data_error_rate_coeff;
797
798 uint8_t Mem_ActiveHystLimit;
799 uint8_t Mem_IdleHystLimit;
800 uint8_t Mem_FPS;
801 uint8_t Mem_MinActiveFreqType;
802 uint8_t Mem_BoosterFreqType;
803 uint8_t Mem_UseRlcBusy;
804 uint16_t Mem_MinActiveFreq;
805 uint16_t Mem_BoosterFreq;
806 uint16_t Mem_PD_Data_time_constant;
807 uint32_t Mem_PD_Data_limit_a;
808 uint32_t Mem_PD_Data_limit_b;
809 uint32_t Mem_PD_Data_limit_c;
810 uint32_t Mem_PD_Data_error_coeff;
811 uint32_t Mem_PD_Data_error_rate_coeff;
812
813 uint8_t Fclk_ActiveHystLimit;
814 uint8_t Fclk_IdleHystLimit;
815 uint8_t Fclk_FPS;
816 uint8_t Fclk_MinActiveFreqType;
817 uint8_t Fclk_BoosterFreqType;
818 uint8_t Fclk_UseRlcBusy;
819 uint16_t Fclk_MinActiveFreq;
820 uint16_t Fclk_BoosterFreq;
821 uint16_t Fclk_PD_Data_time_constant;
822 uint32_t Fclk_PD_Data_limit_a;
823 uint32_t Fclk_PD_Data_limit_b;
824 uint32_t Fclk_PD_Data_limit_c;
825 uint32_t Fclk_PD_Data_error_coeff;
826 uint32_t Fclk_PD_Data_error_rate_coeff;
827
828} DpmActivityMonitorCoeffInt_t;
829
830#define TABLE_PPTABLE 0
831#define TABLE_WATERMARKS 1
832#define TABLE_AVFS 2
833#define TABLE_AVFS_PSM_DEBUG 3
834#define TABLE_AVFS_FUSE_OVERRIDE 4
835#define TABLE_PMSTATUSLOG 5
836#define TABLE_SMU_METRICS 6
837#define TABLE_DRIVER_SMU_CONFIG 7
838#define TABLE_ACTIVITY_MONITOR_COEFF 8
839#define TABLE_OVERDRIVE 9
840#define TABLE_COUNT 10
841
842
843#define UCLK_SWITCH_SLOW 0
844#define UCLK_SWITCH_FAST 1
845
846
847#define SQ_Enable_MASK 0x1
848#define SQ_IR_MASK 0x2
849#define SQ_PCC_MASK 0x4
850#define SQ_EDC_MASK 0x8
851
852#define TCP_Enable_MASK 0x100
853#define TCP_IR_MASK 0x200
854#define TCP_PCC_MASK 0x400
855#define TCP_EDC_MASK 0x800
856
857#define TD_Enable_MASK 0x10000
858#define TD_IR_MASK 0x20000
859#define TD_PCC_MASK 0x40000
860#define TD_EDC_MASK 0x80000
861
862#define DB_Enable_MASK 0x1000000
863#define DB_IR_MASK 0x2000000
864#define DB_PCC_MASK 0x4000000
865#define DB_EDC_MASK 0x8000000
866
867#define SQ_Enable_SHIFT 0
868#define SQ_IR_SHIFT 1
869#define SQ_PCC_SHIFT 2
870#define SQ_EDC_SHIFT 3
871
872#define TCP_Enable_SHIFT 8
873#define TCP_IR_SHIFT 9
874#define TCP_PCC_SHIFT 10
875#define TCP_EDC_SHIFT 11
876
877#define TD_Enable_SHIFT 16
878#define TD_IR_SHIFT 17
879#define TD_PCC_SHIFT 18
880#define TD_EDC_SHIFT 19
881
882#define DB_Enable_SHIFT 24
883#define DB_IR_SHIFT 25
884#define DB_PCC_SHIFT 26
885#define DB_EDC_SHIFT 27
886
887#define REMOVE_FMAX_MARGIN_BIT 0x0
888#define REMOVE_DCTOL_MARGIN_BIT 0x1
889#define REMOVE_PLATFORM_MARGIN_BIT 0x2
890
891#endif
892
