1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU72_DISCRETE_H 25#define SMU72_DISCRETE_H 26 27#include "smu72.h" 28 29#if !defined(SMC_MICROCODE) 30#pragma pack(push, 1) 31#endif 32 33struct SMIO_Pattern { 34 uint16_t Voltage; 35 uint8_t Smio; 36 uint8_t padding; 37}; 38 39typedef struct SMIO_Pattern SMIO_Pattern; 40 41struct SMIO_Table { 42 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 43}; 44 45typedef struct SMIO_Table SMIO_Table; 46 47struct SMU72_Discrete_GraphicsLevel { 48 SMU_VoltageLevel MinVoltage; 49 50 uint32_t SclkFrequency; 51 52 uint8_t pcieDpmLevel; 53 uint8_t DeepSleepDivId; 54 uint16_t ActivityLevel; 55 56 uint32_t CgSpllFuncCntl3; 57 uint32_t CgSpllFuncCntl4; 58 uint32_t SpllSpreadSpectrum; 59 uint32_t SpllSpreadSpectrum2; 60 uint32_t CcPwrDynRm; 61 uint32_t CcPwrDynRm1; 62 uint8_t SclkDid; 63 uint8_t DisplayWatermark; 64 uint8_t EnabledForActivity; 65 uint8_t EnabledForThrottle; 66 uint8_t UpHyst; 67 uint8_t DownHyst; 68 uint8_t VoltageDownHyst; 69 uint8_t PowerThrottle; 70}; 71 72typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel; 73 74struct SMU72_Discrete_ACPILevel { 75 uint32_t Flags; 76 SMU_VoltageLevel MinVoltage; 77 uint32_t SclkFrequency; 78 uint8_t SclkDid; 79 uint8_t DisplayWatermark; 80 uint8_t DeepSleepDivId; 81 uint8_t padding; 82 uint32_t CgSpllFuncCntl; 83 uint32_t CgSpllFuncCntl2; 84 uint32_t CgSpllFuncCntl3; 85 uint32_t CgSpllFuncCntl4; 86 uint32_t SpllSpreadSpectrum; 87 uint32_t SpllSpreadSpectrum2; 88 uint32_t CcPwrDynRm; 89 uint32_t CcPwrDynRm1; 90}; 91 92typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel; 93 94struct SMU72_Discrete_Ulv { 95 uint32_t CcPwrDynRm; 96 uint32_t CcPwrDynRm1; 97 uint16_t VddcOffset; 98 uint8_t VddcOffsetVid; 99 uint8_t VddcPhase; 100 uint32_t Reserved; 101}; 102 103typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv; 104 105struct SMU72_Discrete_MemoryLevel { 106 SMU_VoltageLevel MinVoltage; 107 uint32_t MinMvdd; 108 109 uint32_t MclkFrequency; 110 111 uint8_t EdcReadEnable; 112 uint8_t EdcWriteEnable; 113 uint8_t RttEnable; 114 uint8_t StutterEnable; 115 116 uint8_t StrobeEnable; 117 uint8_t StrobeRatio; 118 uint8_t EnabledForThrottle; 119 uint8_t EnabledForActivity; 120 121 uint8_t UpHyst; 122 uint8_t DownHyst; 123 uint8_t VoltageDownHyst; 124 uint8_t padding; 125 126 uint16_t ActivityLevel; 127 uint8_t DisplayWatermark; 128 uint8_t padding1; 129 130 uint32_t MpllFuncCntl; 131 uint32_t MpllFuncCntl_1; 132 uint32_t MpllFuncCntl_2; 133 uint32_t MpllAdFuncCntl; 134 uint32_t MpllDqFuncCntl; 135 uint32_t MclkPwrmgtCntl; 136 uint32_t DllCntl; 137 uint32_t MpllSs1; 138 uint32_t MpllSs2; 139}; 140 141typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel; 142 143struct SMU72_Discrete_LinkLevel { 144 uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ 145 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ 146 uint8_t EnabledForActivity; 147 uint8_t SPC; 148 uint32_t DownThreshold; 149 uint32_t UpThreshold; 150 uint32_t Reserved; 151}; 152 153typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel; 154 155/* MC ARB DRAM Timing registers. */ 156struct SMU72_Discrete_MCArbDramTimingTableEntry { 157 uint32_t McArbDramTiming; 158 uint32_t McArbDramTiming2; 159 uint8_t McArbBurstTime; 160 uint8_t padding[3]; 161}; 162 163typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry; 164 165struct SMU72_Discrete_MCArbDramTimingTable { 166 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 167}; 168 169typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable; 170 171/* UVD VCLK/DCLK state (level) definition. */ 172struct SMU72_Discrete_UvdLevel { 173 uint32_t VclkFrequency; 174 uint32_t DclkFrequency; 175 SMU_VoltageLevel MinVoltage; 176 uint8_t VclkDivider; 177 uint8_t DclkDivider; 178 uint8_t padding[2]; 179}; 180 181typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel; 182 183/* Clocks for other external blocks (VCE, ACP, SAMU). */ 184struct SMU72_Discrete_ExtClkLevel { 185 uint32_t Frequency; 186 SMU_VoltageLevel MinVoltage; 187 uint8_t Divider; 188 uint8_t padding[3]; 189}; 190 191typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel; 192 193struct SMU72_Discrete_StateInfo { 194 uint32_t SclkFrequency; 195 uint32_t MclkFrequency; 196 uint32_t VclkFrequency; 197 uint32_t DclkFrequency; 198 uint32_t SamclkFrequency; 199 uint32_t AclkFrequency; 200 uint32_t EclkFrequency; 201 uint16_t MvddVoltage; 202 uint16_t padding16; 203 uint8_t DisplayWatermark; 204 uint8_t McArbIndex; 205 uint8_t McRegIndex; 206 uint8_t SeqIndex; 207 uint8_t SclkDid; 208 int8_t SclkIndex; 209 int8_t MclkIndex; 210 uint8_t PCIeGen; 211 212}; 213 214typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo; 215 216struct SMU72_Discrete_DpmTable { 217 /* Multi-DPM controller settings */ 218 SMU72_PIDController GraphicsPIDController; 219 SMU72_PIDController MemoryPIDController; 220 SMU72_PIDController LinkPIDController; 221 222 uint32_t SystemFlags; 223 224 /* SMIO masks for voltage and phase controls */ 225 uint32_t VRConfig; 226 uint32_t SmioMask1; 227 uint32_t SmioMask2; 228 SMIO_Table SmioTable1; 229 SMIO_Table SmioTable2; 230 231 uint32_t VddcLevelCount; 232 uint32_t VddciLevelCount; 233 uint32_t VddGfxLevelCount; 234 uint32_t MvddLevelCount; 235 236 uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC]; 237 uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX]; 238 uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI]; 239 240 uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX]; 241 uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX]; 242 uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX]; 243 244 uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC]; 245 uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC]; 246 uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC]; 247 248 uint8_t GraphicsDpmLevelCount; 249 uint8_t MemoryDpmLevelCount; 250 uint8_t LinkLevelCount; 251 uint8_t MasterDeepSleepControl; 252 253 uint8_t UvdLevelCount; 254 uint8_t VceLevelCount; 255 uint8_t AcpLevelCount; 256 uint8_t SamuLevelCount; 257 258 uint8_t ThermOutGpio; 259 uint8_t ThermOutPolarity; 260 uint8_t ThermOutMode; 261 uint8_t DPMFreezeAndForced; 262 uint32_t Reserved[4]; 263 264 /* State table entries for each DPM state */ 265 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; 266 SMU72_Discrete_MemoryLevel MemoryACPILevel; 267 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; 268 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; 269 SMU72_Discrete_ACPILevel ACPILevel; 270 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; 271 SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; 272 SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP]; 273 SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; 274 SMU72_Discrete_Ulv Ulv; 275 276 uint32_t SclkStepSize; 277 uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; 278 279 uint8_t UvdBootLevel; 280 uint8_t VceBootLevel; 281 uint8_t AcpBootLevel; 282 uint8_t SamuBootLevel; 283 284 uint8_t GraphicsBootLevel; 285 uint8_t GraphicsVoltageChangeEnable; 286 uint8_t GraphicsThermThrottleEnable; 287 uint8_t GraphicsInterval; 288 289 uint8_t VoltageInterval; 290 uint8_t ThermalInterval; 291 uint16_t TemperatureLimitHigh; 292 293 uint16_t TemperatureLimitLow; 294 uint8_t MemoryBootLevel; 295 uint8_t MemoryVoltageChangeEnable; 296 297 uint16_t BootMVdd; 298 uint8_t MemoryInterval; 299 uint8_t MemoryThermThrottleEnable; 300 301 uint16_t VoltageResponseTime; 302 uint16_t PhaseResponseTime; 303 304 uint8_t PCIeBootLinkLevel; 305 uint8_t PCIeGenInterval; 306 uint8_t DTEInterval; 307 uint8_t DTEMode; 308 309 uint8_t SVI2Enable; 310 uint8_t VRHotGpio; 311 uint8_t AcDcGpio; 312 uint8_t ThermGpio; 313 314 uint16_t PPM_PkgPwrLimit; 315 uint16_t PPM_TemperatureLimit; 316 317 uint16_t DefaultTdp; 318 uint16_t TargetTdp; 319 320 uint16_t FpsHighThreshold; 321 uint16_t FpsLowThreshold; 322 323 uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 324 uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 325 326 uint8_t DTEAmbientTempBase; 327 uint8_t DTETjOffset; 328 uint8_t GpuTjMax; 329 uint8_t GpuTjHyst; 330 331 SMU_VoltageLevel BootVoltage; 332 333 uint32_t BAPM_TEMP_GRADIENT; 334 335 uint32_t LowSclkInterruptThreshold; 336 uint32_t VddGfxReChkWait; 337 338 uint8_t ClockStretcherAmount; 339 340 uint8_t Sclk_CKS_masterEn0_7; 341 uint8_t Sclk_CKS_masterEn8_15; 342 uint8_t padding[1]; 343 344 uint8_t Sclk_voltageOffset[8]; 345 346 SMU_ClockStretcherDataTable ClockStretcherDataTable; 347 SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 348}; 349 350typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable; 351 352/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */ 353#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 354#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */ 355 356struct SMU72_Discrete_MCRegisterAddress { 357 uint16_t s0; 358 uint16_t s1; 359}; 360 361typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress; 362 363struct SMU72_Discrete_MCRegisterSet { 364 uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 365}; 366 367typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet; 368 369struct SMU72_Discrete_MCRegisters { 370 uint8_t last; 371 uint8_t reserved[3]; 372 SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 373 SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 374}; 375 376typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters; 377 378 379/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */ 380 381struct SMU72_Discrete_FanTable { 382 uint16_t FdoMode; 383 int16_t TempMin; 384 int16_t TempMed; 385 int16_t TempMax; 386 int16_t Slope1; 387 int16_t Slope2; 388 int16_t FdoMin; 389 int16_t HystUp; 390 int16_t HystDown; 391 int16_t HystSlope; 392 int16_t TempRespLim; 393 int16_t TempCurr; 394 int16_t SlopeCurr; 395 int16_t PwmCurr; 396 uint32_t RefreshPeriod; 397 int16_t FdoMax; 398 uint8_t TempSrc; 399 int8_t FanControl_GL_Flag; 400}; 401 402typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable; 403 404#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 405#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 406 407struct SMU7_MclkDpmScoreboard { 408 409 uint32_t PercentageBusy; 410 411 int32_t PIDError; 412 int32_t PIDIntegral; 413 int32_t PIDOutput; 414 415 uint32_t SigmaDeltaAccum; 416 uint32_t SigmaDeltaOutput; 417 uint32_t SigmaDeltaLevel; 418 419 uint32_t UtilizationSetpoint; 420 421 uint8_t TdpClampMode; 422 uint8_t TdcClampMode; 423 uint8_t ThermClampMode; 424 uint8_t VoltageBusy; 425 426 int8_t CurrLevel; 427 int8_t TargLevel; 428 uint8_t LevelChangeInProgress; 429 uint8_t UpHyst; 430 431 uint8_t DownHyst; 432 uint8_t VoltageDownHyst; 433 uint8_t DpmEnable; 434 uint8_t DpmRunning; 435 436 uint8_t DpmForce; 437 uint8_t DpmForceLevel; 438 uint8_t DisplayWatermark; 439 uint8_t McArbIndex; 440 441 uint32_t MinimumPerfMclk; 442 443 uint8_t AcpiReq; 444 uint8_t AcpiAck; 445 uint8_t MclkSwitchInProgress; 446 uint8_t MclkSwitchCritical; 447 448 uint8_t IgnoreVBlank; 449 uint8_t TargetMclkIndex; 450 uint8_t TargetMvddIndex; 451 uint8_t MclkSwitchResult; 452 453 uint16_t VbiFailureCount; 454 uint8_t VbiWaitCounter; 455 uint8_t EnabledLevelsChange; 456 457 uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY]; 458 uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY]; 459 460 void (*TargetStateCalculator)(uint8_t); 461 void (*SavedTargetStateCalculator)(uint8_t); 462 463 uint16_t AutoDpmInterval; 464 uint16_t AutoDpmRange; 465 466 uint16_t VbiTimeoutCount; 467 uint16_t MclkSwitchingTime; 468 469 uint8_t fastSwitch; 470 uint8_t Save_PIC_VDDGFX_EXIT; 471 uint8_t Save_PIC_VDDGFX_ENTER; 472 uint8_t padding; 473 474}; 475 476typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 477 478struct SMU7_UlvScoreboard { 479 uint8_t EnterUlv; 480 uint8_t ExitUlv; 481 uint8_t UlvActive; 482 uint8_t WaitingForUlv; 483 uint8_t UlvEnable; 484 uint8_t UlvRunning; 485 uint8_t UlvMasterEnable; 486 uint8_t padding; 487 uint32_t UlvAbortedCount; 488 uint32_t UlvTimeStamp; 489}; 490 491typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 492 493struct VddgfxSavedRegisters { 494 uint32_t GPU_DBG[3]; 495 uint32_t MEC_BaseAddress_Hi; 496 uint32_t MEC_BaseAddress_Lo; 497 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 498 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 499 uint32_t CP_INT_CNTL; 500}; 501 502typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 503 504struct SMU7_VddGfxScoreboard { 505 uint8_t VddGfxEnable; 506 uint8_t VddGfxActive; 507 uint8_t VPUResetOccured; 508 uint8_t padding; 509 510 uint32_t VddGfxEnteredCount; 511 uint32_t VddGfxAbortedCount; 512 513 uint32_t VddGfxVid; 514 515 VddgfxSavedRegisters SavedRegisters; 516}; 517 518typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 519 520struct SMU7_TdcLimitScoreboard { 521 uint8_t Enable; 522 uint8_t Running; 523 uint16_t Alpha; 524 uint32_t FilteredIddc; 525 uint32_t IddcLimit; 526 uint32_t IddcHyst; 527 SMU7_HystController_Data HystControllerData; 528}; 529 530typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 531 532struct SMU7_PkgPwrLimitScoreboard { 533 uint8_t Enable; 534 uint8_t Running; 535 uint16_t Alpha; 536 uint32_t FilteredPkgPwr; 537 uint32_t Limit; 538 uint32_t Hyst; 539 uint32_t LimitFromDriver; 540 SMU7_HystController_Data HystControllerData; 541}; 542 543typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 544 545struct SMU7_BapmScoreboard { 546 uint32_t source_powers[SMU72_DTE_SOURCES]; 547 uint32_t source_powers_last[SMU72_DTE_SOURCES]; 548 int32_t entity_temperatures[SMU72_NUM_GPU_TES]; 549 int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES]; 550 int32_t Limit; 551 int32_t Hyst; 552 int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2]; 553 int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; 554 uint16_t ConfigTDPPowerScalar; 555 uint16_t FanSpeedPowerScalar; 556 uint16_t OverDrivePowerScalar; 557 uint16_t OverDriveLimitScalar; 558 uint16_t FinalPowerScalar; 559 uint8_t VariantID; 560 uint8_t spare997; 561 562 SMU7_HystController_Data HystControllerData; 563 564 int32_t temperature_gradient_slope; 565 int32_t temperature_gradient; 566 uint32_t measured_temperature; 567}; 568 569 570typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 571 572struct SMU7_AcpiScoreboard { 573 uint32_t SavedInterruptMask[2]; 574 uint8_t LastACPIRequest; 575 uint8_t CgBifResp; 576 uint8_t RequestType; 577 uint8_t Padding; 578 SMU72_Discrete_ACPILevel D0Level; 579}; 580 581typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 582 583struct SMU72_Discrete_PmFuses { 584 /* dw1 */ 585 uint8_t SviLoadLineEn; 586 uint8_t SviLoadLineVddC; 587 uint8_t SviLoadLineTrimVddC; 588 uint8_t SviLoadLineOffsetVddC; 589 590 /* dw2 */ 591 uint16_t TDC_VDDC_PkgLimit; 592 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 593 uint8_t TDC_MAWt; 594 595 /* dw3 */ 596 uint8_t TdcWaterfallCtl; 597 uint8_t LPMLTemperatureMin; 598 uint8_t LPMLTemperatureMax; 599 uint8_t Reserved; 600 601 /* dw4-dw7 */ 602 uint8_t LPMLTemperatureScaler[16]; 603 604 /* dw8-dw9 */ 605 int16_t FuzzyFan_ErrorSetDelta; 606 int16_t FuzzyFan_ErrorRateSetDelta; 607 int16_t FuzzyFan_PwmSetDelta; 608 uint16_t Reserved6; 609 610 /* dw10-dw14 */ 611 uint8_t GnbLPML[16]; 612 613 /* dw15 */ 614 uint8_t GnbLPMLMaxVid; 615 uint8_t GnbLPMLMinVid; 616 uint8_t Reserved1[2]; 617 618 /* dw16 */ 619 uint16_t BapmVddCBaseLeakageHiSidd; 620 uint16_t BapmVddCBaseLeakageLoSidd; 621}; 622 623typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses; 624 625struct SMU7_Discrete_Log_Header_Table { 626 uint32_t version; 627 uint32_t asic_id; 628 uint16_t flags; 629 uint16_t entry_size; 630 uint32_t total_size; 631 uint32_t num_of_entries; 632 uint8_t type; 633 uint8_t mode; 634 uint8_t filler_0[2]; 635 uint32_t filler_1[2]; 636}; 637 638typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 639 640struct SMU7_Discrete_Log_Cntl { 641 uint8_t Enabled; 642 uint8_t Type; 643 uint8_t padding[2]; 644 uint32_t BufferSize; 645 uint32_t SamplesLogged; 646 uint32_t SampleSize; 647 uint32_t AddrL; 648 uint32_t AddrH; 649}; 650 651typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 652 653#define CAC_ACC_NW_NUM_OF_SIGNALS 87 654 655struct SMU7_Discrete_Cac_Collection_Table { 656 uint32_t temperature; 657 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 658}; 659 660typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 661 662struct SMU7_Discrete_Cac_Verification_Table { 663 uint32_t VddcTotalPower; 664 uint32_t VddcLeakagePower; 665 uint32_t VddcConstantPower; 666 uint32_t VddcGfxDynamicPower; 667 uint32_t VddcUvdDynamicPower; 668 uint32_t VddcVceDynamicPower; 669 uint32_t VddcAcpDynamicPower; 670 uint32_t VddcPcieDynamicPower; 671 uint32_t VddcDceDynamicPower; 672 uint32_t VddcCurrent; 673 uint32_t VddcVoltage; 674 uint32_t VddciTotalPower; 675 uint32_t VddciLeakagePower; 676 uint32_t VddciConstantPower; 677 uint32_t VddciDynamicPower; 678 uint32_t Vddr1TotalPower; 679 uint32_t Vddr1LeakagePower; 680 uint32_t Vddr1ConstantPower; 681 uint32_t Vddr1DynamicPower; 682 uint32_t spare[4]; 683 uint32_t temperature; 684}; 685 686typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 687 688struct SMU7_Discrete_Pm_Status_Table { 689 /* Thermal entities */ 690 int32_t T_meas_max; 691 int32_t T_meas_acc; 692 int32_t T_calc_max; 693 int32_t T_calc_acc; 694 uint32_t P_scalar_acc; 695 uint32_t P_calc_max; 696 uint32_t P_calc_acc; 697 698 /*Voltage domains */ 699 uint32_t I_calc_max; 700 uint32_t I_calc_acc; 701 uint32_t I_calc_acc_vddci; 702 uint32_t V_calc_noload_acc; 703 uint32_t V_calc_load_acc; 704 uint32_t V_calc_noload_acc_vddci; 705 uint32_t P_meas_acc; 706 uint32_t V_meas_noload_acc; 707 uint32_t V_meas_load_acc; 708 uint32_t I_meas_acc; 709 uint32_t P_meas_acc_vddci; 710 uint32_t V_meas_noload_acc_vddci; 711 uint32_t V_meas_load_acc_vddci; 712 uint32_t I_meas_acc_vddci; 713 714 /*Frequency */ 715 uint16_t Sclk_dpm_residency[8]; 716 uint16_t Uvd_dpm_residency[8]; 717 uint16_t Vce_dpm_residency[8]; 718 uint16_t Mclk_dpm_residency[4]; 719 720 /*Chip */ 721 uint32_t P_vddci_acc; 722 uint32_t P_vddr1_acc; 723 uint32_t P_nte1_acc; 724 uint32_t PkgPwr_max; 725 uint32_t PkgPwr_acc; 726 uint32_t MclkSwitchingTime_max; 727 uint32_t MclkSwitchingTime_acc; 728 uint32_t FanPwm_acc; 729 uint32_t FanRpm_acc; 730 731 uint32_t AccCnt; 732}; 733 734typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 735 736/*FIXME THESE NEED TO BE UPDATED */ 737#define SMU7_SCLK_CAC 0x561 738#define SMU7_MCLK_CAC 0xF9 739#define SMU7_VCLK_CAC 0x2DE 740#define SMU7_DCLK_CAC 0x2DE 741#define SMU7_ECLK_CAC 0x25E 742#define SMU7_ACLK_CAC 0x25E 743#define SMU7_SAMCLK_CAC 0x25E 744#define SMU7_DISPCLK_CAC 0x100 745#define SMU7_CAC_CONSTANT 0x2EE3430 746#define SMU7_CAC_CONSTANT_SHIFT 18 747 748#define SMU7_VDDCI_MCLK_CONST 1765 749#define SMU7_VDDCI_MCLK_CONST_SHIFT 16 750#define SMU7_VDDCI_VDDCI_CONST 50958 751#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 752#define SMU7_VDDCI_CONST 11781 753 754#define SMU7_12C_VDDCI_MCLK_CONST 1623 755#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15 756#define SMU7_12C_VDDCI_VDDCI_CONST 40088 757#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13 758#define SMU7_12C_VDDCI_CONST 20856 759 760#define SMU7_VDDCI_STROBE_PWR 1331 761 762#define SMU7_VDDR1_CONST 693 763#define SMU7_VDDR1_CAC_WEIGHT 20 764#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 765#define SMU7_VDDR1_STROBE_PWR 512 766 767#define SMU7_AREA_COEFF_UVD 0xA78 768#define SMU7_AREA_COEFF_VCE 0x190A 769#define SMU7_AREA_COEFF_ACP 0x22D1 770#define SMU7_AREA_COEFF_SAMU 0x534 771 772/*ThermOutMode values */ 773#define SMU7_THERM_OUT_MODE_DISABLE 0x0 774#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 775#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 776 777#if !defined(SMC_MICROCODE) 778#pragma pack(pop) 779#endif 780 781 782#endif 783 784