LXR linux/drivers/gpu/drm/amd/powerplay/smumgr/smu10

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/pci.h>
  25
  26#include "smumgr.h"
  27#include "smu10_inc.h"
  28#include "soc15_common.h"
  29#include "smu10_smumgr.h"
  30#include "ppatomctrl.h"
  31#include "rv_ppsmc.h"
  32#include "smu10_driver_if.h"
  33#include "smu10.h"
  34#include "pp_debug.h"
  35
  36
  37#define BUFFER_SIZE                 80000
  38#define MAX_STRING_SIZE             15
  39#define BUFFER_SIZETWO              131072
  40
  41#define MP0_Public                  0x03800000
  42#define MP0_SRAM                    0x03900000
  43#define MP1_Public                  0x03b00000
  44#define MP1_SRAM                    0x03c00004
  45
  46#define smnMP1_FIRMWARE_FLAGS       0x3010028
  47
  48
  49static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
  50{
  51        struct amdgpu_device *adev = hwmgr->adev;
  52        uint32_t reg;
  53
  54        reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  55
  56        phm_wait_for_register_unequal(hwmgr, reg,
  57                        0, MP1_C2PMSG_90__CONTENT_MASK);
  58
  59        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  60}
  61
  62static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  63                uint16_t msg)
  64{
  65        struct amdgpu_device *adev = hwmgr->adev;
  66
  67        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  68
  69        return 0;
  70}
  71
  72static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
  73{
  74        struct amdgpu_device *adev = hwmgr->adev;
  75
  76        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  77}
  78
  79static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
  80{
  81        struct amdgpu_device *adev = hwmgr->adev;
  82
  83        smu10_wait_for_response(hwmgr);
  84
  85        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
  86
  87        smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
  88
  89        if (smu10_wait_for_response(hwmgr) == 0)
  90                printk("Failed to send Message %x.\n", msg);
  91
  92        return 0;
  93}
  94
  95
  96static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
  97                uint16_t msg, uint32_t parameter)
  98{
  99        struct amdgpu_device *adev = hwmgr->adev;
 100
 101        smu10_wait_for_response(hwmgr);
 102
 103        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 104
 105        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 106
 107        smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
 108
 109
 110        if (smu10_wait_for_response(hwmgr) == 0)
 111                printk("Failed to send Message %x.\n", msg);
 112
 113        return 0;
 114}
 115
 116static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
 117                uint8_t *table, int16_t table_id)
 118{
 119        struct smu10_smumgr *priv =
 120                        (struct smu10_smumgr *)(hwmgr->smu_backend);
 121
 122        PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 123                        "Invalid SMU Table ID!", return -EINVAL;);
 124        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 125                        "Invalid SMU Table version!", return -EINVAL;);
 126        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 127                        "Invalid SMU Table Length!", return -EINVAL;);
 128        smu10_send_msg_to_smc_with_parameter(hwmgr,
 129                        PPSMC_MSG_SetDriverDramAddrHigh,
 130                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 131        smu10_send_msg_to_smc_with_parameter(hwmgr,
 132                        PPSMC_MSG_SetDriverDramAddrLow,
 133                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 134        smu10_send_msg_to_smc_with_parameter(hwmgr,
 135                        PPSMC_MSG_TransferTableSmu2Dram,
 136                        priv->smu_tables.entry[table_id].table_id);
 137
 138        memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
 139                        priv->smu_tables.entry[table_id].size);
 140
 141        return 0;
 142}
 143
 144static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 145                uint8_t *table, int16_t table_id)
 146{
 147        struct smu10_smumgr *priv =
 148                        (struct smu10_smumgr *)(hwmgr->smu_backend);
 149
 150        PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 151                        "Invalid SMU Table ID!", return -EINVAL;);
 152        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 153                        "Invalid SMU Table version!", return -EINVAL;);
 154        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 155                        "Invalid SMU Table Length!", return -EINVAL;);
 156
 157        memcpy(priv->smu_tables.entry[table_id].table, table,
 158                        priv->smu_tables.entry[table_id].size);
 159
 160        smu10_send_msg_to_smc_with_parameter(hwmgr,
 161                        PPSMC_MSG_SetDriverDramAddrHigh,
 162                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 163        smu10_send_msg_to_smc_with_parameter(hwmgr,
 164                        PPSMC_MSG_SetDriverDramAddrLow,
 165                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
 166        smu10_send_msg_to_smc_with_parameter(hwmgr,
 167                        PPSMC_MSG_TransferTableDram2Smu,
 168                        priv->smu_tables.entry[table_id].table_id);
 169
 170        return 0;
 171}
 172
 173static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
 174{
 175        uint32_t smc_driver_if_version;
 176
 177        smu10_send_msg_to_smc(hwmgr,
 178                        PPSMC_MSG_GetDriverIfVersion);
 179        smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
 180
 181        if ((smc_driver_if_version != SMU10_DRIVER_IF_VERSION) &&
 182            (smc_driver_if_version != SMU10_DRIVER_IF_VERSION + 1)) {
 183                pr_err("Attempt to read SMC IF Version Number Failed!\n");
 184                return -EINVAL;
 185        }
 186
 187        return 0;
 188}
 189
 190static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
 191{
 192        struct smu10_smumgr *priv =
 193                        (struct smu10_smumgr *)(hwmgr->smu_backend);
 194
 195        if (priv) {
 196                amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
 197                                        &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 198                                        &priv->smu_tables.entry[SMU10_WMTABLE].table);
 199                amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
 200                                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
 201                                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
 202                kfree(hwmgr->smu_backend);
 203                hwmgr->smu_backend = NULL;
 204        }
 205
 206        return 0;
 207}
 208
 209static int smu10_start_smu(struct pp_hwmgr *hwmgr)
 210{
 211        struct amdgpu_device *adev = hwmgr->adev;
 212
 213        smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 214        hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
 215        adev->pm.fw_version = hwmgr->smu_version >> 8;
 216
 217        if (adev->rev_id < 0x8 && adev->pdev->device != 0x15d8 &&
 218            adev->pm.fw_version < 0x1e45)
 219                adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 220
 221        if (smu10_verify_smc_interface(hwmgr))
 222                return -EINVAL;
 223
 224        return 0;
 225}
 226
 227static int smu10_smu_init(struct pp_hwmgr *hwmgr)
 228{
 229        struct smu10_smumgr *priv;
 230        int r;
 231
 232        priv = kzalloc(sizeof(struct smu10_smumgr), GFP_KERNEL);
 233
 234        if (!priv)
 235                return -ENOMEM;
 236
 237        hwmgr->smu_backend = priv;
 238
 239        /* allocate space for watermarks table */
 240        r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 241                        sizeof(Watermarks_t),
 242                        PAGE_SIZE,
 243                        AMDGPU_GEM_DOMAIN_VRAM,
 244                        &priv->smu_tables.entry[SMU10_WMTABLE].handle,
 245                        &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 246                        &priv->smu_tables.entry[SMU10_WMTABLE].table);
 247
 248        if (r)
 249                goto err0;
 250
 251        priv->smu_tables.entry[SMU10_WMTABLE].version = 0x01;
 252        priv->smu_tables.entry[SMU10_WMTABLE].size = sizeof(Watermarks_t);
 253        priv->smu_tables.entry[SMU10_WMTABLE].table_id = TABLE_WATERMARKS;
 254
 255        /* allocate space for watermarks table */
 256        r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 257                        sizeof(DpmClocks_t),
 258                        PAGE_SIZE,
 259                        AMDGPU_GEM_DOMAIN_VRAM,
 260                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
 261                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
 262                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
 263
 264        if (r)
 265                goto err1;
 266
 267        priv->smu_tables.entry[SMU10_CLOCKTABLE].version = 0x01;
 268        priv->smu_tables.entry[SMU10_CLOCKTABLE].size = sizeof(DpmClocks_t);
 269        priv->smu_tables.entry[SMU10_CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
 270
 271        return 0;
 272
 273err1:
 274        amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
 275                                &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 276                                &priv->smu_tables.entry[SMU10_WMTABLE].table);
 277err0:
 278        kfree(priv);
 279        return -EINVAL;
 280}
 281
 282static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
 283{
 284        int ret;
 285
 286        if (rw)
 287                ret = smu10_copy_table_from_smc(hwmgr, table, table_id);
 288        else
 289                ret = smu10_copy_table_to_smc(hwmgr, table, table_id);
 290
 291        return ret;
 292}
 293
 294
 295const struct pp_smumgr_func smu10_smu_funcs = {
 296        .name = "smu10_smu",
 297        .smu_init = &smu10_smu_init,
 298        .smu_fini = &smu10_smu_fini,
 299        .start_smu = &smu10_start_smu,
 300        .request_smu_load_specific_fw = NULL,
 301        .send_msg_to_smc = &smu10_send_msg_to_smc,
 302        .send_msg_to_smc_with_parameter = &smu10_send_msg_to_smc_with_parameter,
 303        .download_pptable_settings = NULL,
 304        .upload_pptable_settings = NULL,
 305        .get_argument = smu10_read_arg_from_smc,
 306        .smc_table_manager = smu10_smc_table_manager,
 307};
 308
 309
 310