LXR linux/drivers/gpu/drm/amd/powerplay/smumgr/vega20

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include "smumgr.h"
  25#include "vega20_inc.h"
  26#include "soc15_common.h"
  27#include "vega20_smumgr.h"
  28#include "vega20_ppsmc.h"
  29#include "smu11_driver_if.h"
  30#include "ppatomctrl.h"
  31#include "pp_debug.h"
  32#include "smu_ucode_xfer_vi.h"
  33#include "smu7_smumgr.h"
  34#include "vega20_hwmgr.h"
  35
  36/* MP Apertures */
  37#define MP0_Public                      0x03800000
  38#define MP0_SRAM                        0x03900000
  39#define MP1_Public                      0x03b00000
  40#define MP1_SRAM                        0x03c00004
  41
  42/* address block */
  43#define smnMP1_FIRMWARE_FLAGS           0x3010024
  44#define smnMP0_FW_INTF                  0x30101c0
  45#define smnMP1_PUB_CTRL                 0x3010b14
  46
  47static bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  48{
  49        struct amdgpu_device *adev = hwmgr->adev;
  50        uint32_t mp1_fw_flags;
  51
  52        mp1_fw_flags = RREG32_PCIE(MP1_Public |
  53                                   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
  54
  55        if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
  56            MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
  57                return true;
  58
  59        return false;
  60}
  61
  62/*
  63 * Check if SMC has responded to previous message.
  64 *
  65 * @param    smumgr  the address of the powerplay hardware manager.
  66 * @return   TRUE    SMC has responded, FALSE otherwise.
  67 */
  68static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr)
  69{
  70        struct amdgpu_device *adev = hwmgr->adev;
  71        uint32_t reg;
  72
  73        reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  74
  75        phm_wait_for_register_unequal(hwmgr, reg,
  76                        0, MP1_C2PMSG_90__CONTENT_MASK);
  77
  78        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  79}
  80
  81/*
  82 * Send a message to the SMC, and do not wait for its response.
  83 * @param    smumgr  the address of the powerplay hardware manager.
  84 * @param    msg the message to send.
  85 * @return   Always return 0.
  86 */
  87static int vega20_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  88                uint16_t msg)
  89{
  90        struct amdgpu_device *adev = hwmgr->adev;
  91
  92        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  93
  94        return 0;
  95}
  96
  97/*
  98 * Send a message to the SMC, and wait for its response.
  99 * @param    hwmgr  the address of the powerplay hardware manager.
 100 * @param    msg the message to send.
 101 * @return   Always return 0.
 102 */
 103static int vega20_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 104{
 105        struct amdgpu_device *adev = hwmgr->adev;
 106        int ret = 0;
 107
 108        vega20_wait_for_response(hwmgr);
 109
 110        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 111
 112        vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
 113
 114        ret = vega20_wait_for_response(hwmgr);
 115        if (ret != PPSMC_Result_OK)
 116                pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
 117
 118        return (ret == PPSMC_Result_OK) ? 0 : -EIO;
 119}
 120
 121/*
 122 * Send a message to the SMC with parameter
 123 * @param    hwmgr:  the address of the powerplay hardware manager.
 124 * @param    msg: the message to send.
 125 * @param    parameter: the parameter to send
 126 * @return   Always return 0.
 127 */
 128static int vega20_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 129                uint16_t msg, uint32_t parameter)
 130{
 131        struct amdgpu_device *adev = hwmgr->adev;
 132        int ret = 0;
 133
 134        vega20_wait_for_response(hwmgr);
 135
 136        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 137
 138        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 139
 140        vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
 141
 142        ret = vega20_wait_for_response(hwmgr);
 143        if (ret != PPSMC_Result_OK)
 144                pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
 145
 146        return (ret == PPSMC_Result_OK) ? 0 : -EIO;
 147}
 148
 149static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
 150{
 151        struct amdgpu_device *adev = hwmgr->adev;
 152
 153        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 154}
 155
 156/*
 157 * Copy table from SMC into driver FB
 158 * @param   hwmgr    the address of the HW manager
 159 * @param   table_id    the driver's table ID to copy from
 160 */
 161static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
 162                                      uint8_t *table, int16_t table_id)
 163{
 164        struct vega20_smumgr *priv =
 165                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 166        int ret = 0;
 167
 168        PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
 169                        "Invalid SMU Table ID!", return -EINVAL);
 170        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 171                        "Invalid SMU Table version!", return -EINVAL);
 172        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 173                        "Invalid SMU Table Length!", return -EINVAL);
 174
 175        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 176                        PPSMC_MSG_SetDriverDramAddrHigh,
 177                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 178                        "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!",
 179                        return ret);
 180        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 181                        PPSMC_MSG_SetDriverDramAddrLow,
 182                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 183                        "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
 184                        return ret);
 185        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 186                        PPSMC_MSG_TransferTableSmu2Dram, table_id)) == 0,
 187                        "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
 188                        return ret);
 189
 190        memcpy(table, priv->smu_tables.entry[table_id].table,
 191                        priv->smu_tables.entry[table_id].size);
 192
 193        return 0;
 194}
 195
 196/*
 197 * Copy table from Driver FB into SMC
 198 * @param   hwmgr    the address of the HW manager
 199 * @param   table_id    the table to copy from
 200 */
 201static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 202                                    uint8_t *table, int16_t table_id)
 203{
 204        struct vega20_smumgr *priv =
 205                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 206        int ret = 0;
 207
 208        PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
 209                        "Invalid SMU Table ID!", return -EINVAL);
 210        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 211                        "Invalid SMU Table version!", return -EINVAL);
 212        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 213                        "Invalid SMU Table Length!", return -EINVAL);
 214
 215        memcpy(priv->smu_tables.entry[table_id].table, table,
 216                        priv->smu_tables.entry[table_id].size);
 217
 218        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 219                        PPSMC_MSG_SetDriverDramAddrHigh,
 220                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 221                        "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
 222                        return ret);
 223        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 224                        PPSMC_MSG_SetDriverDramAddrLow,
 225                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
 226                        "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
 227                        return ret);
 228        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 229                        PPSMC_MSG_TransferTableDram2Smu, table_id)) == 0,
 230                        "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
 231                        return ret);
 232
 233        return 0;
 234}
 235
 236int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
 237                uint8_t *table, uint16_t workload_type)
 238{
 239        struct vega20_smumgr *priv =
 240                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 241        int ret = 0;
 242
 243        memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table,
 244                        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
 245
 246        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 247                        PPSMC_MSG_SetDriverDramAddrHigh,
 248                        upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 249                        "[SetActivityMonitor] Attempt to Set Dram Addr High Failed!",
 250                        return ret);
 251        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 252                        PPSMC_MSG_SetDriverDramAddrLow,
 253                        lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 254                        "[SetActivityMonitor] Attempt to Set Dram Addr Low Failed!",
 255                        return ret);
 256        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 257                        PPSMC_MSG_TransferTableDram2Smu, TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16))) == 0,
 258                        "[SetActivityMonitor] Attempt to Transfer Table To SMU Failed!",
 259                        return ret);
 260
 261        return 0;
 262}
 263
 264int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
 265                uint8_t *table, uint16_t workload_type)
 266{
 267        struct vega20_smumgr *priv =
 268                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 269        int ret = 0;
 270
 271        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 272                        PPSMC_MSG_SetDriverDramAddrHigh,
 273                        upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 274                        "[GetActivityMonitor] Attempt to Set Dram Addr High Failed!",
 275                        return ret);
 276        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 277                        PPSMC_MSG_SetDriverDramAddrLow,
 278                        lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
 279                        "[GetActivityMonitor] Attempt to Set Dram Addr Low Failed!",
 280                        return ret);
 281        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 282                        PPSMC_MSG_TransferTableSmu2Dram,
 283                        TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16))) == 0,
 284                        "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!",
 285                        return ret);
 286
 287        memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
 288                        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
 289
 290        return 0;
 291}
 292
 293int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
 294                bool enable, uint64_t feature_mask)
 295{
 296        uint32_t smu_features_low, smu_features_high;
 297        int ret = 0;
 298
 299        smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
 300        smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
 301
 302        if (enable) {
 303                PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 304                                PPSMC_MSG_EnableSmuFeaturesLow, smu_features_low)) == 0,
 305                                "[EnableDisableSMCFeatures] Attemp to enable SMU features Low failed!",
 306                                return ret);
 307                PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 308                                PPSMC_MSG_EnableSmuFeaturesHigh, smu_features_high)) == 0,
 309                                "[EnableDisableSMCFeatures] Attemp to enable SMU features High failed!",
 310                                return ret);
 311        } else {
 312                PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 313                                PPSMC_MSG_DisableSmuFeaturesLow, smu_features_low)) == 0,
 314                                "[EnableDisableSMCFeatures] Attemp to disable SMU features Low failed!",
 315                                return ret);
 316                PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 317                                PPSMC_MSG_DisableSmuFeaturesHigh, smu_features_high)) == 0,
 318                                "[EnableDisableSMCFeatures] Attemp to disable SMU features High failed!",
 319                                return ret);
 320        }
 321
 322        return 0;
 323}
 324
 325int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
 326                uint64_t *features_enabled)
 327{
 328        uint32_t smc_features_low, smc_features_high;
 329        int ret = 0;
 330
 331        if (features_enabled == NULL)
 332                return -EINVAL;
 333
 334        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
 335                        PPSMC_MSG_GetEnabledSmuFeaturesLow)) == 0,
 336                        "[GetEnabledSMCFeatures] Attemp to get SMU features Low failed!",
 337                        return ret);
 338        smc_features_low = vega20_get_argument(hwmgr);
 339        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
 340                        PPSMC_MSG_GetEnabledSmuFeaturesHigh)) == 0,
 341                        "[GetEnabledSMCFeatures] Attemp to get SMU features High failed!",
 342                        return ret);
 343        smc_features_high = vega20_get_argument(hwmgr);
 344
 345        *features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
 346                        (((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
 347
 348        return 0;
 349}
 350
 351static int vega20_set_tools_address(struct pp_hwmgr *hwmgr)
 352{
 353        struct vega20_smumgr *priv =
 354                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 355        int ret = 0;
 356
 357        if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr) {
 358                ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 359                                PPSMC_MSG_SetToolsDramAddrHigh,
 360                                upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
 361                if (!ret)
 362                        ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 363                                        PPSMC_MSG_SetToolsDramAddrLow,
 364                                        lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
 365        }
 366
 367        return ret;
 368}
 369
 370int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr)
 371{
 372        struct vega20_smumgr *priv =
 373                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 374        int ret = 0;
 375
 376        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 377                        PPSMC_MSG_SetDriverDramAddrHigh,
 378                        upper_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr))) == 0,
 379                        "[SetPPtabeDriverAddress] Attempt to Set Dram Addr High Failed!",
 380                        return ret);
 381        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
 382                        PPSMC_MSG_SetDriverDramAddrLow,
 383                        lower_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr))) == 0,
 384                        "[SetPPtabeDriverAddress] Attempt to Set Dram Addr Low Failed!",
 385                        return ret);
 386
 387        return ret;
 388}
 389
 390static int vega20_smu_init(struct pp_hwmgr *hwmgr)
 391{
 392        struct vega20_smumgr *priv;
 393        unsigned long tools_size = 0x19000;
 394        int ret = 0;
 395
 396        struct cgs_firmware_info info = {0};
 397
 398        ret = cgs_get_firmware_info(hwmgr->device,
 399                                smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
 400                                &info);
 401        if (ret || !info.kptr)
 402                return -EINVAL;
 403
 404        priv = kzalloc(sizeof(struct vega20_smumgr), GFP_KERNEL);
 405        if (!priv)
 406                return -ENOMEM;
 407
 408        hwmgr->smu_backend = priv;
 409
 410        /* allocate space for pptable */
 411        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 412                        sizeof(PPTable_t),
 413                        PAGE_SIZE,
 414                        AMDGPU_GEM_DOMAIN_VRAM,
 415                        &priv->smu_tables.entry[TABLE_PPTABLE].handle,
 416                        &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 417                        &priv->smu_tables.entry[TABLE_PPTABLE].table);
 418        if (ret)
 419                goto free_backend;
 420
 421        priv->smu_tables.entry[TABLE_PPTABLE].version = 0x01;
 422        priv->smu_tables.entry[TABLE_PPTABLE].size = sizeof(PPTable_t);
 423
 424        /* allocate space for watermarks table */
 425        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 426                        sizeof(Watermarks_t),
 427                        PAGE_SIZE,
 428                        AMDGPU_GEM_DOMAIN_VRAM,
 429                        &priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 430                        &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 431                        &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 432        if (ret)
 433                goto err0;
 434
 435        priv->smu_tables.entry[TABLE_WATERMARKS].version = 0x01;
 436        priv->smu_tables.entry[TABLE_WATERMARKS].size = sizeof(Watermarks_t);
 437
 438        /* allocate space for pmstatuslog table */
 439        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 440                        tools_size,
 441                        PAGE_SIZE,
 442                        AMDGPU_GEM_DOMAIN_VRAM,
 443                        &priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 444                        &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 445                        &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 446        if (ret)
 447                goto err1;
 448
 449        priv->smu_tables.entry[TABLE_PMSTATUSLOG].version = 0x01;
 450        priv->smu_tables.entry[TABLE_PMSTATUSLOG].size = tools_size;
 451
 452        /* allocate space for OverDrive table */
 453        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 454                        sizeof(OverDriveTable_t),
 455                        PAGE_SIZE,
 456                        AMDGPU_GEM_DOMAIN_VRAM,
 457                        &priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 458                        &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 459                        &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 460        if (ret)
 461                goto err2;
 462
 463        priv->smu_tables.entry[TABLE_OVERDRIVE].version = 0x01;
 464        priv->smu_tables.entry[TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t);
 465
 466        /* allocate space for SmuMetrics table */
 467        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 468                        sizeof(SmuMetrics_t),
 469                        PAGE_SIZE,
 470                        AMDGPU_GEM_DOMAIN_VRAM,
 471                        &priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 472                        &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 473                        &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 474        if (ret)
 475                goto err3;
 476
 477        priv->smu_tables.entry[TABLE_SMU_METRICS].version = 0x01;
 478        priv->smu_tables.entry[TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t);
 479
 480        /* allocate space for ActivityMonitor table */
 481        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 482                        sizeof(DpmActivityMonitorCoeffInt_t),
 483                        PAGE_SIZE,
 484                        AMDGPU_GEM_DOMAIN_VRAM,
 485                        &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
 486                        &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
 487                        &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
 488        if (ret)
 489                goto err4;
 490
 491        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].version = 0x01;
 492        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t);
 493
 494        return 0;
 495
 496err4:
 497        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 498                        &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 499                        &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 500err3:
 501        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 502                        &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 503                        &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 504err2:
 505        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 506                        &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 507                        &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 508err1:
 509        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 510                        &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 511                        &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 512err0:
 513        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
 514                        &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 515                        &priv->smu_tables.entry[TABLE_PPTABLE].table);
 516free_backend:
 517        kfree(hwmgr->smu_backend);
 518
 519        return -EINVAL;
 520}
 521
 522static int vega20_smu_fini(struct pp_hwmgr *hwmgr)
 523{
 524        struct vega20_smumgr *priv =
 525                        (struct vega20_smumgr *)(hwmgr->smu_backend);
 526
 527        if (priv) {
 528                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
 529                                &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
 530                                &priv->smu_tables.entry[TABLE_PPTABLE].table);
 531                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
 532                                &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
 533                                &priv->smu_tables.entry[TABLE_WATERMARKS].table);
 534                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
 535                                &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
 536                                &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
 537                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
 538                                &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
 539                                &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
 540                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
 541                                &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
 542                                &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
 543                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
 544                                &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
 545                                &priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
 546                kfree(hwmgr->smu_backend);
 547                hwmgr->smu_backend = NULL;
 548        }
 549        return 0;
 550}
 551
 552static int vega20_start_smu(struct pp_hwmgr *hwmgr)
 553{
 554        int ret;
 555
 556        ret = vega20_is_smc_ram_running(hwmgr);
 557        PP_ASSERT_WITH_CODE(ret,
 558                        "[Vega20StartSmu] SMC is not running!",
 559                        return -EINVAL);
 560
 561        ret = vega20_set_tools_address(hwmgr);
 562        PP_ASSERT_WITH_CODE(!ret,
 563                        "[Vega20StartSmu] Failed to set tools address!",
 564                        return ret);
 565
 566        return 0;
 567}
 568
 569static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
 570{
 571        uint64_t features_enabled = 0;
 572
 573        vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 574
 575        if (features_enabled & SMC_DPM_FEATURES)
 576                return true;
 577        else
 578                return false;
 579}
 580
 581static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
 582                                    uint16_t table_id, bool rw)
 583{
 584        int ret;
 585
 586        if (rw)
 587                ret = vega20_copy_table_from_smc(hwmgr, table, table_id);
 588        else
 589                ret = vega20_copy_table_to_smc(hwmgr, table, table_id);
 590
 591        return ret;
 592}
 593
 594const struct pp_smumgr_func vega20_smu_funcs = {
 595        .name = "vega20_smu",
 596        .smu_init = &vega20_smu_init,
 597        .smu_fini = &vega20_smu_fini,
 598        .start_smu = &vega20_start_smu,
 599        .request_smu_load_specific_fw = NULL,
 600        .send_msg_to_smc = &vega20_send_msg_to_smc,
 601        .send_msg_to_smc_with_parameter = &vega20_send_msg_to_smc_with_parameter,
 602        .download_pptable_settings = NULL,
 603        .upload_pptable_settings = NULL,
 604        .is_dpm_running = vega20_is_dpm_running,
 605        .get_argument = vega20_get_argument,
 606        .smc_table_manager = vega20_smc_table_manager,
 607};
 608