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24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include "amdgpu.h"
27#include "amdgpu_smu.h"
28#include "atomfirmware.h"
29#include "amdgpu_atomfirmware.h"
30#include "smu_v11_0.h"
31#include "smu11_driver_if.h"
32#include "soc15_common.h"
33#include "atom.h"
34#include "power_state.h"
35#include "vega20_ppt.h"
36#include "vega20_pptable.h"
37#include "vega20_ppsmc.h"
38#include "nbio/nbio_7_4_sh_mask.h"
39#include "asic_reg/thm/thm_11_0_2_offset.h"
40#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
41
42#define smnPCIE_LC_SPEED_CNTL 0x11140290
43#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
44
45#define CTF_OFFSET_EDGE 5
46#define CTF_OFFSET_HOTSPOT 5
47#define CTF_OFFSET_HBM 5
48
49#define MSG_MAP(msg) \
50 [SMU_MSG_##msg] = PPSMC_MSG_##msg
51
52#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
53 FEATURE_DPM_GFXCLK_MASK | \
54 FEATURE_DPM_UCLK_MASK | \
55 FEATURE_DPM_SOCCLK_MASK | \
56 FEATURE_DPM_UVD_MASK | \
57 FEATURE_DPM_VCE_MASK | \
58 FEATURE_DPM_MP0CLK_MASK | \
59 FEATURE_DPM_LINK_MASK | \
60 FEATURE_DPM_DCEFCLK_MASK)
61
62static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
63 MSG_MAP(TestMessage),
64 MSG_MAP(GetSmuVersion),
65 MSG_MAP(GetDriverIfVersion),
66 MSG_MAP(SetAllowedFeaturesMaskLow),
67 MSG_MAP(SetAllowedFeaturesMaskHigh),
68 MSG_MAP(EnableAllSmuFeatures),
69 MSG_MAP(DisableAllSmuFeatures),
70 MSG_MAP(EnableSmuFeaturesLow),
71 MSG_MAP(EnableSmuFeaturesHigh),
72 MSG_MAP(DisableSmuFeaturesLow),
73 MSG_MAP(DisableSmuFeaturesHigh),
74 MSG_MAP(GetEnabledSmuFeaturesLow),
75 MSG_MAP(GetEnabledSmuFeaturesHigh),
76 MSG_MAP(SetWorkloadMask),
77 MSG_MAP(SetPptLimit),
78 MSG_MAP(SetDriverDramAddrHigh),
79 MSG_MAP(SetDriverDramAddrLow),
80 MSG_MAP(SetToolsDramAddrHigh),
81 MSG_MAP(SetToolsDramAddrLow),
82 MSG_MAP(TransferTableSmu2Dram),
83 MSG_MAP(TransferTableDram2Smu),
84 MSG_MAP(UseDefaultPPTable),
85 MSG_MAP(UseBackupPPTable),
86 MSG_MAP(RunBtc),
87 MSG_MAP(RequestI2CBus),
88 MSG_MAP(ReleaseI2CBus),
89 MSG_MAP(SetFloorSocVoltage),
90 MSG_MAP(SoftReset),
91 MSG_MAP(StartBacoMonitor),
92 MSG_MAP(CancelBacoMonitor),
93 MSG_MAP(EnterBaco),
94 MSG_MAP(SetSoftMinByFreq),
95 MSG_MAP(SetSoftMaxByFreq),
96 MSG_MAP(SetHardMinByFreq),
97 MSG_MAP(SetHardMaxByFreq),
98 MSG_MAP(GetMinDpmFreq),
99 MSG_MAP(GetMaxDpmFreq),
100 MSG_MAP(GetDpmFreqByIndex),
101 MSG_MAP(GetDpmClockFreq),
102 MSG_MAP(GetSsVoltageByDpm),
103 MSG_MAP(SetMemoryChannelConfig),
104 MSG_MAP(SetGeminiMode),
105 MSG_MAP(SetGeminiApertureHigh),
106 MSG_MAP(SetGeminiApertureLow),
107 MSG_MAP(SetMinLinkDpmByIndex),
108 MSG_MAP(OverridePcieParameters),
109 MSG_MAP(OverDriveSetPercentage),
110 MSG_MAP(SetMinDeepSleepDcefclk),
111 MSG_MAP(ReenableAcDcInterrupt),
112 MSG_MAP(NotifyPowerSource),
113 MSG_MAP(SetUclkFastSwitch),
114 MSG_MAP(SetUclkDownHyst),
115 MSG_MAP(GetCurrentRpm),
116 MSG_MAP(SetVideoFps),
117 MSG_MAP(SetTjMax),
118 MSG_MAP(SetFanTemperatureTarget),
119 MSG_MAP(PrepareMp1ForUnload),
120 MSG_MAP(DramLogSetDramAddrHigh),
121 MSG_MAP(DramLogSetDramAddrLow),
122 MSG_MAP(DramLogSetDramSize),
123 MSG_MAP(SetFanMaxRpm),
124 MSG_MAP(SetFanMinPwm),
125 MSG_MAP(ConfigureGfxDidt),
126 MSG_MAP(NumOfDisplays),
127 MSG_MAP(RemoveMargins),
128 MSG_MAP(ReadSerialNumTop32),
129 MSG_MAP(ReadSerialNumBottom32),
130 MSG_MAP(SetSystemVirtualDramAddrHigh),
131 MSG_MAP(SetSystemVirtualDramAddrLow),
132 MSG_MAP(WaflTest),
133 MSG_MAP(SetFclkGfxClkRatio),
134 MSG_MAP(AllowGfxOff),
135 MSG_MAP(DisallowGfxOff),
136 MSG_MAP(GetPptLimit),
137 MSG_MAP(GetDcModeMaxDpmFreq),
138 MSG_MAP(GetDebugData),
139 MSG_MAP(SetXgmiMode),
140 MSG_MAP(RunAfllBtc),
141 MSG_MAP(ExitBaco),
142 MSG_MAP(PrepareMp1ForReset),
143 MSG_MAP(PrepareMp1ForShutdown),
144 MSG_MAP(SetMGpuFanBoostLimitRpm),
145 MSG_MAP(GetAVFSVoltageByDpm),
146};
147
148static int vega20_clk_map[SMU_CLK_COUNT] = {
149 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
150 CLK_MAP(VCLK, PPCLK_VCLK),
151 CLK_MAP(DCLK, PPCLK_DCLK),
152 CLK_MAP(ECLK, PPCLK_ECLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(UCLK, PPCLK_UCLK),
155 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
156 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
157 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
158 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
159 CLK_MAP(FCLK, PPCLK_FCLK),
160};
161
162static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
163 FEA_MAP(DPM_PREFETCHER),
164 FEA_MAP(DPM_GFXCLK),
165 FEA_MAP(DPM_UCLK),
166 FEA_MAP(DPM_SOCCLK),
167 FEA_MAP(DPM_UVD),
168 FEA_MAP(DPM_VCE),
169 FEA_MAP(ULV),
170 FEA_MAP(DPM_MP0CLK),
171 FEA_MAP(DPM_LINK),
172 FEA_MAP(DPM_DCEFCLK),
173 FEA_MAP(DS_GFXCLK),
174 FEA_MAP(DS_SOCCLK),
175 FEA_MAP(DS_LCLK),
176 FEA_MAP(PPT),
177 FEA_MAP(TDC),
178 FEA_MAP(THERMAL),
179 FEA_MAP(GFX_PER_CU_CG),
180 FEA_MAP(RM),
181 FEA_MAP(DS_DCEFCLK),
182 FEA_MAP(ACDC),
183 FEA_MAP(VR0HOT),
184 FEA_MAP(VR1HOT),
185 FEA_MAP(FW_CTF),
186 FEA_MAP(LED_DISPLAY),
187 FEA_MAP(FAN_CONTROL),
188 FEA_MAP(GFX_EDC),
189 FEA_MAP(GFXOFF),
190 FEA_MAP(CG),
191 FEA_MAP(DPM_FCLK),
192 FEA_MAP(DS_FCLK),
193 FEA_MAP(DS_MP1CLK),
194 FEA_MAP(DS_MP0CLK),
195 FEA_MAP(XGMI),
196};
197
198static int vega20_table_map[SMU_TABLE_COUNT] = {
199 TAB_MAP(PPTABLE),
200 TAB_MAP(WATERMARKS),
201 TAB_MAP(AVFS),
202 TAB_MAP(AVFS_PSM_DEBUG),
203 TAB_MAP(AVFS_FUSE_OVERRIDE),
204 TAB_MAP(PMSTATUSLOG),
205 TAB_MAP(SMU_METRICS),
206 TAB_MAP(DRIVER_SMU_CONFIG),
207 TAB_MAP(ACTIVITY_MONITOR_COEFF),
208 TAB_MAP(OVERDRIVE),
209};
210
211static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
212 PWR_MAP(AC),
213 PWR_MAP(DC),
214};
215
216static int vega20_workload_map[] = {
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
224};
225
226static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
227{
228 int val;
229 if (index >= SMU_TABLE_COUNT)
230 return -EINVAL;
231
232 val = vega20_table_map[index];
233 if (val >= TABLE_COUNT)
234 return -EINVAL;
235
236 return val;
237}
238
239static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
240{
241 int val;
242 if (index >= SMU_POWER_SOURCE_COUNT)
243 return -EINVAL;
244
245 val = vega20_pwr_src_map[index];
246 if (val >= POWER_SOURCE_COUNT)
247 return -EINVAL;
248
249 return val;
250}
251
252static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
253{
254 int val;
255 if (index >= SMU_FEATURE_COUNT)
256 return -EINVAL;
257
258 val = vega20_feature_mask_map[index];
259 if (val > 64)
260 return -EINVAL;
261
262 return val;
263}
264
265static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
266{
267 int val;
268 if (index >= SMU_CLK_COUNT)
269 return -EINVAL;
270
271 val = vega20_clk_map[index];
272 if (val >= PPCLK_COUNT)
273 return -EINVAL;
274
275 return val;
276}
277
278static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
279{
280 int val;
281
282 if (index >= SMU_MSG_MAX_COUNT)
283 return -EINVAL;
284
285 val = vega20_message_map[index];
286 if (val > PPSMC_Message_Count)
287 return -EINVAL;
288
289 return val;
290}
291
292static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
293{
294 int val;
295 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
296 return -EINVAL;
297
298 val = vega20_workload_map[profile];
299
300 return val;
301}
302
303static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
304{
305 struct smu_table_context *smu_table = &smu->smu_table;
306
307 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
308 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
309 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
310 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
311 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
312 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
313 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
314 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
315 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
317 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
318 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
319 AMDGPU_GEM_DOMAIN_VRAM);
320
321 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
322 if (!smu_table->metrics_table)
323 return -ENOMEM;
324 smu_table->metrics_time = 0;
325
326 return 0;
327}
328
329static int vega20_allocate_dpm_context(struct smu_context *smu)
330{
331 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
332
333 if (smu_dpm->dpm_context)
334 return -EINVAL;
335
336 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
337 GFP_KERNEL);
338 if (!smu_dpm->dpm_context)
339 return -ENOMEM;
340
341 if (smu_dpm->golden_dpm_context)
342 return -EINVAL;
343
344 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
345 GFP_KERNEL);
346 if (!smu_dpm->golden_dpm_context)
347 return -ENOMEM;
348
349 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
350
351 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
352 GFP_KERNEL);
353 if (!smu_dpm->dpm_current_power_state)
354 return -ENOMEM;
355
356 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
357 GFP_KERNEL);
358 if (!smu_dpm->dpm_request_power_state)
359 return -ENOMEM;
360
361 return 0;
362}
363
364static int vega20_setup_od8_information(struct smu_context *smu)
365{
366 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
369
370 uint32_t od_feature_count, od_feature_array_size,
371 od_setting_count, od_setting_array_size;
372
373 if (!table_context->power_play_table)
374 return -EINVAL;
375
376 powerplay_table = table_context->power_play_table;
377
378 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
379
380
381 od_feature_count =
382 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
383 ATOM_VEGA20_ODFEATURE_COUNT) ?
384 ATOM_VEGA20_ODFEATURE_COUNT :
385 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
386
387 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
388
389 if (od8_settings->od_feature_capabilities)
390 return -EINVAL;
391
392 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
393 od_feature_array_size,
394 GFP_KERNEL);
395 if (!od8_settings->od_feature_capabilities)
396 return -ENOMEM;
397
398
399
400 od_setting_count =
401 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
402 ATOM_VEGA20_ODSETTING_COUNT) ?
403 ATOM_VEGA20_ODSETTING_COUNT :
404 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
405
406 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
407
408 if (od8_settings->od_settings_max)
409 return -EINVAL;
410
411 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
412 od_setting_array_size,
413 GFP_KERNEL);
414
415 if (!od8_settings->od_settings_max) {
416 kfree(od8_settings->od_feature_capabilities);
417 od8_settings->od_feature_capabilities = NULL;
418 return -ENOMEM;
419 }
420
421 if (od8_settings->od_settings_min)
422 return -EINVAL;
423
424 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
425 od_setting_array_size,
426 GFP_KERNEL);
427
428 if (!od8_settings->od_settings_min) {
429 kfree(od8_settings->od_feature_capabilities);
430 od8_settings->od_feature_capabilities = NULL;
431 kfree(od8_settings->od_settings_max);
432 od8_settings->od_settings_max = NULL;
433 return -ENOMEM;
434 }
435 }
436
437 return 0;
438}
439
440static int vega20_store_powerplay_table(struct smu_context *smu)
441{
442 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
443 struct smu_table_context *table_context = &smu->smu_table;
444
445 if (!table_context->power_play_table)
446 return -EINVAL;
447
448 powerplay_table = table_context->power_play_table;
449
450 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
451 sizeof(PPTable_t));
452
453 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
454 table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
455
456 return 0;
457}
458
459static int vega20_append_powerplay_table(struct smu_context *smu)
460{
461 struct smu_table_context *table_context = &smu->smu_table;
462 PPTable_t *smc_pptable = table_context->driver_pptable;
463 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
464 int index, i, ret;
465
466 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
467 smc_dpm_info);
468
469 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
470 (uint8_t **)&smc_dpm_table);
471 if (ret)
472 return ret;
473
474 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
475 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
476
477 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
478 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
479 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
480 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
481
482 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
483 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
484 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
485
486 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
487 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
488 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
489
490 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
491 smc_pptable->SocOffset = smc_dpm_table->socoffset;
492 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
493
494 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
495 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
496 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
497
498 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
499 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
500 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
501
502 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
503 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
504 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
505 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
506
507 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
508 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
509 smc_pptable->Padding1 = smc_dpm_table->padding1;
510 smc_pptable->Padding2 = smc_dpm_table->padding2;
511
512 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
513 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
514 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
515
516 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
517 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
518 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
519
520 smc_pptable->UclkSpreadEnabled = 0;
521 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
522 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
523
524 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
525 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
526 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
527
528 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
529 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
530 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
531
532 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
533 smc_pptable->I2cControllers[i].Enabled =
534 smc_dpm_table->i2ccontrollers[i].enabled;
535 smc_pptable->I2cControllers[i].SlaveAddress =
536 smc_dpm_table->i2ccontrollers[i].slaveaddress;
537 smc_pptable->I2cControllers[i].ControllerPort =
538 smc_dpm_table->i2ccontrollers[i].controllerport;
539 smc_pptable->I2cControllers[i].ThermalThrottler =
540 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
541 smc_pptable->I2cControllers[i].I2cProtocol =
542 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
543 smc_pptable->I2cControllers[i].I2cSpeed =
544 smc_dpm_table->i2ccontrollers[i].i2cspeed;
545 }
546
547 return 0;
548}
549
550static int vega20_check_powerplay_table(struct smu_context *smu)
551{
552 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
553 struct smu_table_context *table_context = &smu->smu_table;
554
555 powerplay_table = table_context->power_play_table;
556
557 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
558 pr_err("Unsupported PPTable format!");
559 return -EINVAL;
560 }
561
562 if (!powerplay_table->sHeader.structuresize) {
563 pr_err("Invalid PowerPlay Table!");
564 return -EINVAL;
565 }
566
567 return 0;
568}
569
570static int vega20_run_btc_afll(struct smu_context *smu)
571{
572 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
573}
574
575#define FEATURE_MASK(feature) (1ULL << feature)
576static int
577vega20_get_allowed_feature_mask(struct smu_context *smu,
578 uint32_t *feature_mask, uint32_t num)
579{
580 if (num > 2)
581 return -EINVAL;
582
583 memset(feature_mask, 0, sizeof(uint32_t) * num);
584
585 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
586 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
587 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
588 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
589 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
590 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
591 | FEATURE_MASK(FEATURE_ULV_BIT)
592 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
593 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
594 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
595 | FEATURE_MASK(FEATURE_PPT_BIT)
596 | FEATURE_MASK(FEATURE_TDC_BIT)
597 | FEATURE_MASK(FEATURE_THERMAL_BIT)
598 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
599 | FEATURE_MASK(FEATURE_RM_BIT)
600 | FEATURE_MASK(FEATURE_ACDC_BIT)
601 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
602 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
603 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
604 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
605 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
606 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
607 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
608 | FEATURE_MASK(FEATURE_CG_BIT)
609 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
610 | FEATURE_MASK(FEATURE_XGMI_BIT);
611 return 0;
612}
613
614static enum
615amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
616{
617 enum amd_pm_state_type pm_type;
618 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
619
620 if (!smu_dpm_ctx->dpm_context ||
621 !smu_dpm_ctx->dpm_current_power_state)
622 return -EINVAL;
623
624 mutex_lock(&(smu->mutex));
625 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
626 case SMU_STATE_UI_LABEL_BATTERY:
627 pm_type = POWER_STATE_TYPE_BATTERY;
628 break;
629 case SMU_STATE_UI_LABEL_BALLANCED:
630 pm_type = POWER_STATE_TYPE_BALANCED;
631 break;
632 case SMU_STATE_UI_LABEL_PERFORMANCE:
633 pm_type = POWER_STATE_TYPE_PERFORMANCE;
634 break;
635 default:
636 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
637 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
638 else
639 pm_type = POWER_STATE_TYPE_DEFAULT;
640 break;
641 }
642 mutex_unlock(&(smu->mutex));
643
644 return pm_type;
645}
646
647static int
648vega20_set_single_dpm_table(struct smu_context *smu,
649 struct vega20_single_dpm_table *single_dpm_table,
650 PPCLK_e clk_id)
651{
652 int ret = 0;
653 uint32_t i, num_of_levels = 0, clk;
654
655 ret = smu_send_smc_msg_with_param(smu,
656 SMU_MSG_GetDpmFreqByIndex,
657 (clk_id << 16 | 0xFF));
658 if (ret) {
659 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
660 return ret;
661 }
662
663 smu_read_smc_arg(smu, &num_of_levels);
664 if (!num_of_levels) {
665 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
666 return -EINVAL;
667 }
668
669 single_dpm_table->count = num_of_levels;
670
671 for (i = 0; i < num_of_levels; i++) {
672 ret = smu_send_smc_msg_with_param(smu,
673 SMU_MSG_GetDpmFreqByIndex,
674 (clk_id << 16 | i));
675 if (ret) {
676 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
677 return ret;
678 }
679 smu_read_smc_arg(smu, &clk);
680 if (!clk) {
681 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
682 return -EINVAL;
683 }
684 single_dpm_table->dpm_levels[i].value = clk;
685 single_dpm_table->dpm_levels[i].enabled = true;
686 }
687 return 0;
688}
689
690static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
691{
692 dpm_state->soft_min_level = 0x0;
693 dpm_state->soft_max_level = 0xffff;
694 dpm_state->hard_min_level = 0x0;
695 dpm_state->hard_max_level = 0xffff;
696}
697
698static int vega20_set_default_dpm_table(struct smu_context *smu)
699{
700 int ret;
701
702 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
703 struct vega20_dpm_table *dpm_table = NULL;
704 struct vega20_single_dpm_table *single_dpm_table;
705
706 dpm_table = smu_dpm->dpm_context;
707
708
709 single_dpm_table = &(dpm_table->soc_table);
710
711 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
712 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
713 PPCLK_SOCCLK);
714 if (ret) {
715 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
716 return ret;
717 }
718 } else {
719 single_dpm_table->count = 1;
720 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
721 }
722 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
723
724
725 single_dpm_table = &(dpm_table->gfx_table);
726
727 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
728 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
729 PPCLK_GFXCLK);
730 if (ret) {
731 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
732 return ret;
733 }
734 } else {
735 single_dpm_table->count = 1;
736 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
737 }
738 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
739
740
741 single_dpm_table = &(dpm_table->mem_table);
742
743 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
744 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
745 PPCLK_UCLK);
746 if (ret) {
747 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
748 return ret;
749 }
750 } else {
751 single_dpm_table->count = 1;
752 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
753 }
754 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
755
756
757 single_dpm_table = &(dpm_table->eclk_table);
758
759 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
760 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
761 if (ret) {
762 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
763 return ret;
764 }
765 } else {
766 single_dpm_table->count = 1;
767 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
768 }
769 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
770
771
772 single_dpm_table = &(dpm_table->vclk_table);
773
774 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
775 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
776 if (ret) {
777 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
778 return ret;
779 }
780 } else {
781 single_dpm_table->count = 1;
782 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
783 }
784 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
785
786
787 single_dpm_table = &(dpm_table->dclk_table);
788
789 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
790 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
791 if (ret) {
792 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
793 return ret;
794 }
795 } else {
796 single_dpm_table->count = 1;
797 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
798 }
799 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
800
801
802 single_dpm_table = &(dpm_table->dcef_table);
803
804 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
805 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
806 PPCLK_DCEFCLK);
807 if (ret) {
808 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
809 return ret;
810 }
811 } else {
812 single_dpm_table->count = 1;
813 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
814 }
815 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
816
817
818 single_dpm_table = &(dpm_table->pixel_table);
819
820 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
821 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
822 PPCLK_PIXCLK);
823 if (ret) {
824 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
825 return ret;
826 }
827 } else {
828 single_dpm_table->count = 0;
829 }
830 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
831
832
833 single_dpm_table = &(dpm_table->display_table);
834
835 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
836 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
837 PPCLK_DISPCLK);
838 if (ret) {
839 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
840 return ret;
841 }
842 } else {
843 single_dpm_table->count = 0;
844 }
845 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
846
847
848 single_dpm_table = &(dpm_table->phy_table);
849
850 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
851 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
852 PPCLK_PHYCLK);
853 if (ret) {
854 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
855 return ret;
856 }
857 } else {
858 single_dpm_table->count = 0;
859 }
860 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
861
862
863 single_dpm_table = &(dpm_table->fclk_table);
864
865 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
866 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
867 PPCLK_FCLK);
868 if (ret) {
869 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
870 return ret;
871 }
872 } else {
873 single_dpm_table->count = 0;
874 }
875 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
876
877 memcpy(smu_dpm->golden_dpm_context, dpm_table,
878 sizeof(struct vega20_dpm_table));
879
880 return 0;
881}
882
883static int vega20_populate_umd_state_clk(struct smu_context *smu)
884{
885 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
886 struct vega20_dpm_table *dpm_table = NULL;
887 struct vega20_single_dpm_table *gfx_table = NULL;
888 struct vega20_single_dpm_table *mem_table = NULL;
889
890 dpm_table = smu_dpm->dpm_context;
891 gfx_table = &(dpm_table->gfx_table);
892 mem_table = &(dpm_table->mem_table);
893
894 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
895 smu->pstate_mclk = mem_table->dpm_levels[0].value;
896
897 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
898 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
899 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
900 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
901 }
902
903 smu->pstate_sclk = smu->pstate_sclk * 100;
904 smu->pstate_mclk = smu->pstate_mclk * 100;
905
906 return 0;
907}
908
909static int vega20_get_clk_table(struct smu_context *smu,
910 struct pp_clock_levels_with_latency *clocks,
911 struct vega20_single_dpm_table *dpm_table)
912{
913 int i, count;
914
915 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
916 clocks->num_levels = count;
917
918 for (i = 0; i < count; i++) {
919 clocks->data[i].clocks_in_khz =
920 dpm_table->dpm_levels[i].value * 1000;
921 clocks->data[i].latency_in_us = 0;
922 }
923
924 return 0;
925}
926
927static int vega20_print_clk_levels(struct smu_context *smu,
928 enum smu_clk_type type, char *buf)
929{
930 int i, now, size = 0;
931 int ret = 0;
932 uint32_t gen_speed, lane_width;
933 struct amdgpu_device *adev = smu->adev;
934 struct pp_clock_levels_with_latency clocks;
935 struct vega20_single_dpm_table *single_dpm_table;
936 struct smu_table_context *table_context = &smu->smu_table;
937 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
938 struct vega20_dpm_table *dpm_table = NULL;
939 struct vega20_od8_settings *od8_settings =
940 (struct vega20_od8_settings *)smu->od_settings;
941 OverDriveTable_t *od_table =
942 (OverDriveTable_t *)(table_context->overdrive_table);
943 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
944
945 dpm_table = smu_dpm->dpm_context;
946
947 switch (type) {
948 case SMU_SCLK:
949 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
950 if (ret) {
951 pr_err("Attempt to get current gfx clk Failed!");
952 return ret;
953 }
954
955 single_dpm_table = &(dpm_table->gfx_table);
956 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
957 if (ret) {
958 pr_err("Attempt to get gfx clk levels Failed!");
959 return ret;
960 }
961
962 for (i = 0; i < clocks.num_levels; i++)
963 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
964 clocks.data[i].clocks_in_khz / 1000,
965 (clocks.data[i].clocks_in_khz == now * 10)
966 ? "*" : "");
967 break;
968
969 case SMU_MCLK:
970 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
971 if (ret) {
972 pr_err("Attempt to get current mclk Failed!");
973 return ret;
974 }
975
976 single_dpm_table = &(dpm_table->mem_table);
977 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
978 if (ret) {
979 pr_err("Attempt to get memory clk levels Failed!");
980 return ret;
981 }
982
983 for (i = 0; i < clocks.num_levels; i++)
984 size += sprintf(buf + size, "%d: %uMhz %s\n",
985 i, clocks.data[i].clocks_in_khz / 1000,
986 (clocks.data[i].clocks_in_khz == now * 10)
987 ? "*" : "");
988 break;
989
990 case SMU_SOCCLK:
991 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
992 if (ret) {
993 pr_err("Attempt to get current socclk Failed!");
994 return ret;
995 }
996
997 single_dpm_table = &(dpm_table->soc_table);
998 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
999 if (ret) {
1000 pr_err("Attempt to get socclk levels Failed!");
1001 return ret;
1002 }
1003
1004 for (i = 0; i < clocks.num_levels; i++)
1005 size += sprintf(buf + size, "%d: %uMhz %s\n",
1006 i, clocks.data[i].clocks_in_khz / 1000,
1007 (clocks.data[i].clocks_in_khz == now * 10)
1008 ? "*" : "");
1009 break;
1010
1011 case SMU_FCLK:
1012 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1013 if (ret) {
1014 pr_err("Attempt to get current fclk Failed!");
1015 return ret;
1016 }
1017
1018 single_dpm_table = &(dpm_table->fclk_table);
1019 for (i = 0; i < single_dpm_table->count; i++)
1020 size += sprintf(buf + size, "%d: %uMhz %s\n",
1021 i, single_dpm_table->dpm_levels[i].value,
1022 (single_dpm_table->dpm_levels[i].value == now / 100)
1023 ? "*" : "");
1024 break;
1025
1026 case SMU_DCEFCLK:
1027 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1028 if (ret) {
1029 pr_err("Attempt to get current dcefclk Failed!");
1030 return ret;
1031 }
1032
1033 single_dpm_table = &(dpm_table->dcef_table);
1034 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1035 if (ret) {
1036 pr_err("Attempt to get dcefclk levels Failed!");
1037 return ret;
1038 }
1039
1040 for (i = 0; i < clocks.num_levels; i++)
1041 size += sprintf(buf + size, "%d: %uMhz %s\n",
1042 i, clocks.data[i].clocks_in_khz / 1000,
1043 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1044 break;
1045
1046 case SMU_PCIE:
1047 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1048 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1049 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1050 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1051 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1052 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1053 for (i = 0; i < NUM_LINK_LEVELS; i++)
1054 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1055 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1056 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1057 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1058 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1059 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1060 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1061 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1062 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1063 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1064 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1065 pptable->LclkFreq[i],
1066 (gen_speed == pptable->PcieGenSpeed[i]) &&
1067 (lane_width == pptable->PcieLaneCount[i]) ?
1068 "*" : "");
1069 break;
1070
1071 case SMU_OD_SCLK:
1072 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1073 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1074 size = sprintf(buf, "%s:\n", "OD_SCLK");
1075 size += sprintf(buf + size, "0: %10uMhz\n",
1076 od_table->GfxclkFmin);
1077 size += sprintf(buf + size, "1: %10uMhz\n",
1078 od_table->GfxclkFmax);
1079 }
1080
1081 break;
1082
1083 case SMU_OD_MCLK:
1084 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1085 size = sprintf(buf, "%s:\n", "OD_MCLK");
1086 size += sprintf(buf + size, "1: %10uMhz\n",
1087 od_table->UclkFmax);
1088 }
1089
1090 break;
1091
1092 case SMU_OD_VDDC_CURVE:
1093 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1094 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1095 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1096 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1097 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1098 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1099 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1100 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1101 od_table->GfxclkFreq1,
1102 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1103 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1104 od_table->GfxclkFreq2,
1105 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1106 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1107 od_table->GfxclkFreq3,
1108 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1109 }
1110
1111 break;
1112
1113 case SMU_OD_RANGE:
1114 size = sprintf(buf, "%s:\n", "OD_RANGE");
1115
1116 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1117 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1118 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1119 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1120 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1121 }
1122
1123 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1124 single_dpm_table = &(dpm_table->mem_table);
1125 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1126 if (ret) {
1127 pr_err("Attempt to get memory clk levels Failed!");
1128 return ret;
1129 }
1130
1131 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1132 clocks.data[0].clocks_in_khz / 1000,
1133 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1134 }
1135
1136 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1138 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1139 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1141 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1142 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1143 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1144 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1145 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1146 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1147 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1148 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1149 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1150 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1151 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1154 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1157 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1158 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1159 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1160 }
1161
1162 break;
1163
1164 default:
1165 break;
1166 }
1167 return size;
1168}
1169
1170static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1171 uint32_t feature_mask)
1172{
1173 struct vega20_dpm_table *dpm_table;
1174 struct vega20_single_dpm_table *single_dpm_table;
1175 uint32_t freq;
1176 int ret = 0;
1177
1178 dpm_table = smu->smu_dpm.dpm_context;
1179
1180 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1181 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1182 single_dpm_table = &(dpm_table->gfx_table);
1183 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1184 single_dpm_table->dpm_state.soft_min_level;
1185 ret = smu_send_smc_msg_with_param(smu,
1186 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1187 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1188 if (ret) {
1189 pr_err("Failed to set soft %s gfxclk !\n",
1190 max ? "max" : "min");
1191 return ret;
1192 }
1193 }
1194
1195 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1196 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1197 single_dpm_table = &(dpm_table->mem_table);
1198 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1199 single_dpm_table->dpm_state.soft_min_level;
1200 ret = smu_send_smc_msg_with_param(smu,
1201 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1202 (PPCLK_UCLK << 16) | (freq & 0xffff));
1203 if (ret) {
1204 pr_err("Failed to set soft %s memclk !\n",
1205 max ? "max" : "min");
1206 return ret;
1207 }
1208 }
1209
1210 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1211 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1212 single_dpm_table = &(dpm_table->soc_table);
1213 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1214 single_dpm_table->dpm_state.soft_min_level;
1215 ret = smu_send_smc_msg_with_param(smu,
1216 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1217 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1218 if (ret) {
1219 pr_err("Failed to set soft %s socclk !\n",
1220 max ? "max" : "min");
1221 return ret;
1222 }
1223 }
1224
1225 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1226 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1227 single_dpm_table = &(dpm_table->fclk_table);
1228 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1229 single_dpm_table->dpm_state.soft_min_level;
1230 ret = smu_send_smc_msg_with_param(smu,
1231 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1232 (PPCLK_FCLK << 16) | (freq & 0xffff));
1233 if (ret) {
1234 pr_err("Failed to set soft %s fclk !\n",
1235 max ? "max" : "min");
1236 return ret;
1237 }
1238 }
1239
1240 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1241 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1242 single_dpm_table = &(dpm_table->dcef_table);
1243 freq = single_dpm_table->dpm_state.hard_min_level;
1244 if (!max) {
1245 ret = smu_send_smc_msg_with_param(smu,
1246 SMU_MSG_SetHardMinByFreq,
1247 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1248 if (ret) {
1249 pr_err("Failed to set hard min dcefclk !\n");
1250 return ret;
1251 }
1252 }
1253 }
1254
1255 return ret;
1256}
1257
1258static int vega20_force_clk_levels(struct smu_context *smu,
1259 enum smu_clk_type clk_type, uint32_t mask)
1260{
1261 struct vega20_dpm_table *dpm_table;
1262 struct vega20_single_dpm_table *single_dpm_table;
1263 uint32_t soft_min_level, soft_max_level, hard_min_level;
1264 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1265 int ret = 0;
1266
1267 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1268 pr_info("force clock level is for dpm manual mode only.\n");
1269 return -EINVAL;
1270 }
1271
1272 mutex_lock(&(smu->mutex));
1273
1274 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1275 soft_max_level = mask ? (fls(mask) - 1) : 0;
1276
1277 dpm_table = smu->smu_dpm.dpm_context;
1278
1279 switch (clk_type) {
1280 case SMU_SCLK:
1281 single_dpm_table = &(dpm_table->gfx_table);
1282
1283 if (soft_max_level >= single_dpm_table->count) {
1284 pr_err("Clock level specified %d is over max allowed %d\n",
1285 soft_max_level, single_dpm_table->count - 1);
1286 ret = -EINVAL;
1287 break;
1288 }
1289
1290 single_dpm_table->dpm_state.soft_min_level =
1291 single_dpm_table->dpm_levels[soft_min_level].value;
1292 single_dpm_table->dpm_state.soft_max_level =
1293 single_dpm_table->dpm_levels[soft_max_level].value;
1294
1295 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1296 if (ret) {
1297 pr_err("Failed to upload boot level to lowest!\n");
1298 break;
1299 }
1300
1301 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1302 if (ret)
1303 pr_err("Failed to upload dpm max level to highest!\n");
1304
1305 break;
1306
1307 case SMU_MCLK:
1308 single_dpm_table = &(dpm_table->mem_table);
1309
1310 if (soft_max_level >= single_dpm_table->count) {
1311 pr_err("Clock level specified %d is over max allowed %d\n",
1312 soft_max_level, single_dpm_table->count - 1);
1313 ret = -EINVAL;
1314 break;
1315 }
1316
1317 single_dpm_table->dpm_state.soft_min_level =
1318 single_dpm_table->dpm_levels[soft_min_level].value;
1319 single_dpm_table->dpm_state.soft_max_level =
1320 single_dpm_table->dpm_levels[soft_max_level].value;
1321
1322 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1323 if (ret) {
1324 pr_err("Failed to upload boot level to lowest!\n");
1325 break;
1326 }
1327
1328 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1329 if (ret)
1330 pr_err("Failed to upload dpm max level to highest!\n");
1331
1332 break;
1333
1334 case SMU_SOCCLK:
1335 single_dpm_table = &(dpm_table->soc_table);
1336
1337 if (soft_max_level >= single_dpm_table->count) {
1338 pr_err("Clock level specified %d is over max allowed %d\n",
1339 soft_max_level, single_dpm_table->count - 1);
1340 ret = -EINVAL;
1341 break;
1342 }
1343
1344 single_dpm_table->dpm_state.soft_min_level =
1345 single_dpm_table->dpm_levels[soft_min_level].value;
1346 single_dpm_table->dpm_state.soft_max_level =
1347 single_dpm_table->dpm_levels[soft_max_level].value;
1348
1349 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1350 if (ret) {
1351 pr_err("Failed to upload boot level to lowest!\n");
1352 break;
1353 }
1354
1355 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1356 if (ret)
1357 pr_err("Failed to upload dpm max level to highest!\n");
1358
1359 break;
1360
1361 case SMU_FCLK:
1362 single_dpm_table = &(dpm_table->fclk_table);
1363
1364 if (soft_max_level >= single_dpm_table->count) {
1365 pr_err("Clock level specified %d is over max allowed %d\n",
1366 soft_max_level, single_dpm_table->count - 1);
1367 ret = -EINVAL;
1368 break;
1369 }
1370
1371 single_dpm_table->dpm_state.soft_min_level =
1372 single_dpm_table->dpm_levels[soft_min_level].value;
1373 single_dpm_table->dpm_state.soft_max_level =
1374 single_dpm_table->dpm_levels[soft_max_level].value;
1375
1376 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1377 if (ret) {
1378 pr_err("Failed to upload boot level to lowest!\n");
1379 break;
1380 }
1381
1382 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1383 if (ret)
1384 pr_err("Failed to upload dpm max level to highest!\n");
1385
1386 break;
1387
1388 case SMU_DCEFCLK:
1389 hard_min_level = soft_min_level;
1390 single_dpm_table = &(dpm_table->dcef_table);
1391
1392 if (hard_min_level >= single_dpm_table->count) {
1393 pr_err("Clock level specified %d is over max allowed %d\n",
1394 hard_min_level, single_dpm_table->count - 1);
1395 ret = -EINVAL;
1396 break;
1397 }
1398
1399 single_dpm_table->dpm_state.hard_min_level =
1400 single_dpm_table->dpm_levels[hard_min_level].value;
1401
1402 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1403 if (ret)
1404 pr_err("Failed to upload boot level to lowest!\n");
1405
1406 break;
1407
1408 case SMU_PCIE:
1409 if (soft_min_level >= NUM_LINK_LEVELS ||
1410 soft_max_level >= NUM_LINK_LEVELS) {
1411 ret = -EINVAL;
1412 break;
1413 }
1414
1415 ret = smu_send_smc_msg_with_param(smu,
1416 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1417 if (ret)
1418 pr_err("Failed to set min link dpm level!\n");
1419
1420 break;
1421
1422 default:
1423 break;
1424 }
1425
1426 mutex_unlock(&(smu->mutex));
1427 return ret;
1428}
1429
1430static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1431 enum smu_clk_type clk_type,
1432 struct pp_clock_levels_with_latency *clocks)
1433{
1434 int ret;
1435 struct vega20_single_dpm_table *single_dpm_table;
1436 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1437 struct vega20_dpm_table *dpm_table = NULL;
1438
1439 dpm_table = smu_dpm->dpm_context;
1440
1441 mutex_lock(&smu->mutex);
1442
1443 switch (clk_type) {
1444 case SMU_GFXCLK:
1445 single_dpm_table = &(dpm_table->gfx_table);
1446 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1447 break;
1448 case SMU_MCLK:
1449 single_dpm_table = &(dpm_table->mem_table);
1450 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1451 break;
1452 case SMU_DCEFCLK:
1453 single_dpm_table = &(dpm_table->dcef_table);
1454 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1455 break;
1456 case SMU_SOCCLK:
1457 single_dpm_table = &(dpm_table->soc_table);
1458 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1459 break;
1460 default:
1461 ret = -EINVAL;
1462 }
1463
1464 mutex_unlock(&smu->mutex);
1465 return ret;
1466}
1467
1468static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1469 uint32_t *voltage,
1470 uint32_t freq)
1471{
1472 int ret;
1473
1474 ret = smu_send_smc_msg_with_param(smu,
1475 SMU_MSG_GetAVFSVoltageByDpm,
1476 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1477 if (ret) {
1478 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1479 return ret;
1480 }
1481
1482 smu_read_smc_arg(smu, voltage);
1483 *voltage = *voltage / VOLTAGE_SCALE;
1484
1485 return 0;
1486}
1487
1488static int vega20_set_default_od8_setttings(struct smu_context *smu)
1489{
1490 struct smu_table_context *table_context = &smu->smu_table;
1491 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1492 struct vega20_od8_settings *od8_settings = NULL;
1493 PPTable_t *smc_pptable = table_context->driver_pptable;
1494 int i, ret;
1495
1496 if (smu->od_settings)
1497 return -EINVAL;
1498
1499 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1500
1501 if (!od8_settings)
1502 return -ENOMEM;
1503
1504 smu->od_settings = (void *)od8_settings;
1505
1506 ret = vega20_setup_od8_information(smu);
1507 if (ret) {
1508 pr_err("Retrieve board OD limits failed!\n");
1509 return ret;
1510 }
1511
1512 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1513 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1514 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1515 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1516 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1517 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1518 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1519 OD8_GFXCLK_LIMITS;
1520 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1521 OD8_GFXCLK_LIMITS;
1522 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1523 od_table->GfxclkFmin;
1524 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1525 od_table->GfxclkFmax;
1526 }
1527
1528 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1529 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1530 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1531 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1532 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1533 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1534 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1535 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1536 OD8_GFXCLK_CURVE;
1537 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1538 OD8_GFXCLK_CURVE;
1539 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1540 OD8_GFXCLK_CURVE;
1541 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1542 OD8_GFXCLK_CURVE;
1543 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1544 OD8_GFXCLK_CURVE;
1545 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1546 OD8_GFXCLK_CURVE;
1547
1548 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1549 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1550 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1551 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1552 od_table->GfxclkFreq1;
1553 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1554 od_table->GfxclkFreq2;
1555 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1556 od_table->GfxclkFreq3;
1557
1558 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1559 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1560 od_table->GfxclkFreq1);
1561 if (ret)
1562 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1563 od_table->GfxclkVolt1 =
1564 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1565 * VOLTAGE_SCALE;
1566 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1567 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1568 od_table->GfxclkFreq2);
1569 if (ret)
1570 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1571 od_table->GfxclkVolt2 =
1572 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1573 * VOLTAGE_SCALE;
1574 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1575 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1576 od_table->GfxclkFreq3);
1577 if (ret)
1578 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1579 od_table->GfxclkVolt3 =
1580 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1581 * VOLTAGE_SCALE;
1582 }
1583 }
1584
1585 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1586 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1587 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1588 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1589 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1590 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1591 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1592 OD8_UCLK_MAX;
1593 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1594 od_table->UclkFmax;
1595 }
1596 }
1597
1598 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1599 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1600 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1601 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1602 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1603 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1604 OD8_POWER_LIMIT;
1605 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1606 od_table->OverDrivePct;
1607 }
1608
1609 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1610 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1611 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1612 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1614 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1615 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1616 OD8_ACOUSTIC_LIMIT_SCLK;
1617 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1618 od_table->FanMaximumRpm;
1619 }
1620
1621 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1622 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1623 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1625 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1626 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1627 OD8_FAN_SPEED_MIN;
1628 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1629 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1630 }
1631 }
1632
1633 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1634 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1635 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1636 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1638 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1639 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1640 OD8_TEMPERATURE_FAN;
1641 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1642 od_table->FanTargetTemperature;
1643 }
1644
1645 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1646 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1647 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1649 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1650 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1651 OD8_TEMPERATURE_SYSTEM;
1652 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1653 od_table->MaxOpTemp;
1654 }
1655 }
1656
1657 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1658 if (od8_settings->od8_settings_array[i].feature_id) {
1659 od8_settings->od8_settings_array[i].min_value =
1660 od8_settings->od_settings_min[i];
1661 od8_settings->od8_settings_array[i].max_value =
1662 od8_settings->od_settings_max[i];
1663 od8_settings->od8_settings_array[i].current_value =
1664 od8_settings->od8_settings_array[i].default_value;
1665 } else {
1666 od8_settings->od8_settings_array[i].min_value = 0;
1667 od8_settings->od8_settings_array[i].max_value = 0;
1668 od8_settings->od8_settings_array[i].current_value = 0;
1669 }
1670 }
1671
1672 return 0;
1673}
1674
1675static int vega20_get_metrics_table(struct smu_context *smu,
1676 SmuMetrics_t *metrics_table)
1677{
1678 struct smu_table_context *smu_table= &smu->smu_table;
1679 int ret = 0;
1680
1681 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1682 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1683 (void *)smu_table->metrics_table, false);
1684 if (ret) {
1685 pr_info("Failed to export SMU metrics table!\n");
1686 return ret;
1687 }
1688 smu_table->metrics_time = jiffies;
1689 }
1690
1691 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1692
1693 return ret;
1694}
1695
1696static int vega20_set_default_od_settings(struct smu_context *smu,
1697 bool initialize)
1698{
1699 struct smu_table_context *table_context = &smu->smu_table;
1700 int ret;
1701
1702 if (initialize) {
1703 if (table_context->overdrive_table)
1704 return -EINVAL;
1705
1706 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1707
1708 if (!table_context->overdrive_table)
1709 return -ENOMEM;
1710
1711 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1712 table_context->overdrive_table, false);
1713 if (ret) {
1714 pr_err("Failed to export over drive table!\n");
1715 return ret;
1716 }
1717
1718 ret = vega20_set_default_od8_setttings(smu);
1719 if (ret)
1720 return ret;
1721 }
1722
1723 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1724 table_context->overdrive_table, true);
1725 if (ret) {
1726 pr_err("Failed to import over drive table!\n");
1727 return ret;
1728 }
1729
1730 return 0;
1731}
1732
1733static int vega20_get_od_percentage(struct smu_context *smu,
1734 enum smu_clk_type clk_type)
1735{
1736 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1737 struct vega20_dpm_table *dpm_table = NULL;
1738 struct vega20_dpm_table *golden_table = NULL;
1739 struct vega20_single_dpm_table *single_dpm_table;
1740 struct vega20_single_dpm_table *golden_dpm_table;
1741 int value, golden_value;
1742
1743 dpm_table = smu_dpm->dpm_context;
1744 golden_table = smu_dpm->golden_dpm_context;
1745
1746 switch (clk_type) {
1747 case SMU_OD_SCLK:
1748 single_dpm_table = &(dpm_table->gfx_table);
1749 golden_dpm_table = &(golden_table->gfx_table);
1750 break;
1751 case SMU_OD_MCLK:
1752 single_dpm_table = &(dpm_table->mem_table);
1753 golden_dpm_table = &(golden_table->mem_table);
1754 break;
1755 default:
1756 return -EINVAL;
1757 break;
1758 }
1759
1760 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1761 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1762
1763 value -= golden_value;
1764 value = DIV_ROUND_UP(value * 100, golden_value);
1765
1766 return value;
1767}
1768
1769static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1770{
1771 DpmActivityMonitorCoeffInt_t activity_monitor;
1772 uint32_t i, size = 0;
1773 uint16_t workload_type = 0;
1774 static const char *profile_name[] = {
1775 "BOOTUP_DEFAULT",
1776 "3D_FULL_SCREEN",
1777 "POWER_SAVING",
1778 "VIDEO",
1779 "VR",
1780 "COMPUTE",
1781 "CUSTOM"};
1782 static const char *title[] = {
1783 "PROFILE_INDEX(NAME)",
1784 "CLOCK_TYPE(NAME)",
1785 "FPS",
1786 "UseRlcBusy",
1787 "MinActiveFreqType",
1788 "MinActiveFreq",
1789 "BoosterFreqType",
1790 "BoosterFreq",
1791 "PD_Data_limit_c",
1792 "PD_Data_error_coeff",
1793 "PD_Data_error_rate_coeff"};
1794 int result = 0;
1795
1796 if (!smu->pm_enabled || !buf)
1797 return -EINVAL;
1798
1799 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1800 title[0], title[1], title[2], title[3], title[4], title[5],
1801 title[6], title[7], title[8], title[9], title[10]);
1802
1803 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1804
1805 workload_type = smu_workload_get_type(smu, i);
1806 result = smu_update_table(smu,
1807 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1808 (void *)(&activity_monitor), false);
1809 if (result) {
1810 pr_err("[%s] Failed to get activity monitor!", __func__);
1811 return result;
1812 }
1813
1814 size += sprintf(buf + size, "%2d %14s%s:\n",
1815 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1816
1817 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1818 " ",
1819 0,
1820 "GFXCLK",
1821 activity_monitor.Gfx_FPS,
1822 activity_monitor.Gfx_UseRlcBusy,
1823 activity_monitor.Gfx_MinActiveFreqType,
1824 activity_monitor.Gfx_MinActiveFreq,
1825 activity_monitor.Gfx_BoosterFreqType,
1826 activity_monitor.Gfx_BoosterFreq,
1827 activity_monitor.Gfx_PD_Data_limit_c,
1828 activity_monitor.Gfx_PD_Data_error_coeff,
1829 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1830
1831 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1832 " ",
1833 1,
1834 "SOCCLK",
1835 activity_monitor.Soc_FPS,
1836 activity_monitor.Soc_UseRlcBusy,
1837 activity_monitor.Soc_MinActiveFreqType,
1838 activity_monitor.Soc_MinActiveFreq,
1839 activity_monitor.Soc_BoosterFreqType,
1840 activity_monitor.Soc_BoosterFreq,
1841 activity_monitor.Soc_PD_Data_limit_c,
1842 activity_monitor.Soc_PD_Data_error_coeff,
1843 activity_monitor.Soc_PD_Data_error_rate_coeff);
1844
1845 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1846 " ",
1847 2,
1848 "UCLK",
1849 activity_monitor.Mem_FPS,
1850 activity_monitor.Mem_UseRlcBusy,
1851 activity_monitor.Mem_MinActiveFreqType,
1852 activity_monitor.Mem_MinActiveFreq,
1853 activity_monitor.Mem_BoosterFreqType,
1854 activity_monitor.Mem_BoosterFreq,
1855 activity_monitor.Mem_PD_Data_limit_c,
1856 activity_monitor.Mem_PD_Data_error_coeff,
1857 activity_monitor.Mem_PD_Data_error_rate_coeff);
1858
1859 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1860 " ",
1861 3,
1862 "FCLK",
1863 activity_monitor.Fclk_FPS,
1864 activity_monitor.Fclk_UseRlcBusy,
1865 activity_monitor.Fclk_MinActiveFreqType,
1866 activity_monitor.Fclk_MinActiveFreq,
1867 activity_monitor.Fclk_BoosterFreqType,
1868 activity_monitor.Fclk_BoosterFreq,
1869 activity_monitor.Fclk_PD_Data_limit_c,
1870 activity_monitor.Fclk_PD_Data_error_coeff,
1871 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1872 }
1873
1874 return size;
1875}
1876
1877static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1878{
1879 DpmActivityMonitorCoeffInt_t activity_monitor;
1880 int workload_type = 0, ret = 0;
1881
1882 smu->power_profile_mode = input[size];
1883
1884 if (!smu->pm_enabled)
1885 return ret;
1886 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1887 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1888 return -EINVAL;
1889 }
1890
1891 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1892 ret = smu_update_table(smu,
1893 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1894 (void *)(&activity_monitor), false);
1895 if (ret) {
1896 pr_err("[%s] Failed to get activity monitor!", __func__);
1897 return ret;
1898 }
1899
1900 switch (input[0]) {
1901 case 0:
1902 activity_monitor.Gfx_FPS = input[1];
1903 activity_monitor.Gfx_UseRlcBusy = input[2];
1904 activity_monitor.Gfx_MinActiveFreqType = input[3];
1905 activity_monitor.Gfx_MinActiveFreq = input[4];
1906 activity_monitor.Gfx_BoosterFreqType = input[5];
1907 activity_monitor.Gfx_BoosterFreq = input[6];
1908 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1909 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1910 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1911 break;
1912 case 1:
1913 activity_monitor.Soc_FPS = input[1];
1914 activity_monitor.Soc_UseRlcBusy = input[2];
1915 activity_monitor.Soc_MinActiveFreqType = input[3];
1916 activity_monitor.Soc_MinActiveFreq = input[4];
1917 activity_monitor.Soc_BoosterFreqType = input[5];
1918 activity_monitor.Soc_BoosterFreq = input[6];
1919 activity_monitor.Soc_PD_Data_limit_c = input[7];
1920 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1921 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1922 break;
1923 case 2:
1924 activity_monitor.Mem_FPS = input[1];
1925 activity_monitor.Mem_UseRlcBusy = input[2];
1926 activity_monitor.Mem_MinActiveFreqType = input[3];
1927 activity_monitor.Mem_MinActiveFreq = input[4];
1928 activity_monitor.Mem_BoosterFreqType = input[5];
1929 activity_monitor.Mem_BoosterFreq = input[6];
1930 activity_monitor.Mem_PD_Data_limit_c = input[7];
1931 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1932 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1933 break;
1934 case 3:
1935 activity_monitor.Fclk_FPS = input[1];
1936 activity_monitor.Fclk_UseRlcBusy = input[2];
1937 activity_monitor.Fclk_MinActiveFreqType = input[3];
1938 activity_monitor.Fclk_MinActiveFreq = input[4];
1939 activity_monitor.Fclk_BoosterFreqType = input[5];
1940 activity_monitor.Fclk_BoosterFreq = input[6];
1941 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1942 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1943 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1944 break;
1945 }
1946
1947 ret = smu_update_table(smu,
1948 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1949 (void *)(&activity_monitor), true);
1950 if (ret) {
1951 pr_err("[%s] Failed to set activity monitor!", __func__);
1952 return ret;
1953 }
1954 }
1955
1956
1957 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1958 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1959 1 << workload_type);
1960
1961 return ret;
1962}
1963
1964static int
1965vega20_get_profiling_clk_mask(struct smu_context *smu,
1966 enum amd_dpm_forced_level level,
1967 uint32_t *sclk_mask,
1968 uint32_t *mclk_mask,
1969 uint32_t *soc_mask)
1970{
1971 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1972 struct vega20_single_dpm_table *gfx_dpm_table;
1973 struct vega20_single_dpm_table *mem_dpm_table;
1974 struct vega20_single_dpm_table *soc_dpm_table;
1975
1976 if (!smu->smu_dpm.dpm_context)
1977 return -EINVAL;
1978
1979 gfx_dpm_table = &dpm_table->gfx_table;
1980 mem_dpm_table = &dpm_table->mem_table;
1981 soc_dpm_table = &dpm_table->soc_table;
1982
1983 *sclk_mask = 0;
1984 *mclk_mask = 0;
1985 *soc_mask = 0;
1986
1987 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1988 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1989 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1990 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1991 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1992 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1993 }
1994
1995 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1996 *sclk_mask = 0;
1997 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1998 *mclk_mask = 0;
1999 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2000 *sclk_mask = gfx_dpm_table->count - 1;
2001 *mclk_mask = mem_dpm_table->count - 1;
2002 *soc_mask = soc_dpm_table->count - 1;
2003 }
2004
2005 return 0;
2006}
2007
2008static int
2009vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2010 struct vega20_single_dpm_table *dpm_table)
2011{
2012 int ret = 0;
2013 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2014 if (!smu_dpm_ctx->dpm_context)
2015 return -EINVAL;
2016
2017 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2018 if (dpm_table->count <= 0) {
2019 pr_err("[%s] Dpm table has no entry!", __func__);
2020 return -EINVAL;
2021 }
2022
2023 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2024 pr_err("[%s] Dpm table has too many entries!", __func__);
2025 return -EINVAL;
2026 }
2027
2028 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2029 ret = smu_send_smc_msg_with_param(smu,
2030 SMU_MSG_SetHardMinByFreq,
2031 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2032 if (ret) {
2033 pr_err("[%s] Set hard min uclk failed!", __func__);
2034 return ret;
2035 }
2036 }
2037
2038 return ret;
2039}
2040
2041static int vega20_pre_display_config_changed(struct smu_context *smu)
2042{
2043 int ret = 0;
2044 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2045
2046 if (!smu->smu_dpm.dpm_context)
2047 return -EINVAL;
2048
2049 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2050 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2051 &dpm_table->mem_table);
2052 if (ret)
2053 pr_err("Failed to set uclk to highest dpm level");
2054 return ret;
2055}
2056
2057static int vega20_display_config_changed(struct smu_context *smu)
2058{
2059 int ret = 0;
2060
2061 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2062 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2063 ret = smu_write_watermarks_table(smu);
2064 if (ret) {
2065 pr_err("Failed to update WMTABLE!");
2066 return ret;
2067 }
2068 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2069 }
2070
2071 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2072 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2073 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2074 smu_send_smc_msg_with_param(smu,
2075 SMU_MSG_NumOfDisplays,
2076 smu->display_config->num_display);
2077 }
2078
2079 return ret;
2080}
2081
2082static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2083{
2084 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2085 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2086 struct vega20_single_dpm_table *dpm_table;
2087 bool vblank_too_short = false;
2088 bool disable_mclk_switching;
2089 uint32_t i, latency;
2090
2091 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2092 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2093 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2094
2095
2096 dpm_table = &(dpm_ctx->gfx_table);
2097 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2098 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2099 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2100 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2101
2102 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2103 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2104 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2105 }
2106
2107 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2108 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2109 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2110 }
2111
2112 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2113 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2114 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2115 }
2116
2117
2118 dpm_table = &(dpm_ctx->mem_table);
2119 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2120 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2121 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2122 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2123
2124 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2125 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2126 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2127 }
2128
2129 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2130 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2131 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2132 }
2133
2134 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2135 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2136 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2137 }
2138
2139
2140 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2141 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2142
2143
2144 if (disable_mclk_switching) {
2145 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2146 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2147 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2148 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2149 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2150 break;
2151 }
2152 }
2153 }
2154 }
2155
2156 if (smu->display_config->nb_pstate_switch_disable)
2157 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2158
2159
2160 dpm_table = &(dpm_ctx->vclk_table);
2161 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2162 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2163 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2164 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2165
2166 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2167 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2168 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2169 }
2170
2171 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2172 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2173 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2174 }
2175
2176
2177 dpm_table = &(dpm_ctx->dclk_table);
2178 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2179 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2180 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2181 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2182
2183 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2184 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2185 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2186 }
2187
2188 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2189 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2190 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2191 }
2192
2193
2194 dpm_table = &(dpm_ctx->soc_table);
2195 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2196 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2197 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2198 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2199
2200 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2201 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2202 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2203 }
2204
2205 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2206 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2207 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2208 }
2209
2210
2211 dpm_table = &(dpm_ctx->eclk_table);
2212 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2213 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2214 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2215 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2216
2217 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2218 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2219 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2220 }
2221
2222 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2223 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2224 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2225 }
2226 return 0;
2227}
2228
2229static int
2230vega20_notify_smc_dispaly_config(struct smu_context *smu)
2231{
2232 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2233 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2234 struct smu_clocks min_clocks = {0};
2235 struct pp_display_clock_request clock_req;
2236 int ret = 0;
2237
2238 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2239 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2240 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2241
2242 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2243 clock_req.clock_type = amd_pp_dcef_clock;
2244 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2245 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2246 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2247 ret = smu_send_smc_msg_with_param(smu,
2248 SMU_MSG_SetMinDeepSleepDcefclk,
2249 min_clocks.dcef_clock_in_sr/100);
2250 if (ret) {
2251 pr_err("Attempt to set divider for DCEFCLK Failed!");
2252 return ret;
2253 }
2254 }
2255 } else {
2256 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2257 }
2258 }
2259
2260 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2261 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2262 ret = smu_send_smc_msg_with_param(smu,
2263 SMU_MSG_SetHardMinByFreq,
2264 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2265 if (ret) {
2266 pr_err("[%s] Set hard min uclk failed!", __func__);
2267 return ret;
2268 }
2269 }
2270
2271 return 0;
2272}
2273
2274static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2275{
2276 uint32_t i;
2277
2278 for (i = 0; i < table->count; i++) {
2279 if (table->dpm_levels[i].enabled)
2280 break;
2281 }
2282 if (i >= table->count) {
2283 i = 0;
2284 table->dpm_levels[i].enabled = true;
2285 }
2286
2287 return i;
2288}
2289
2290static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2291{
2292 int i = 0;
2293
2294 if (!table) {
2295 pr_err("[%s] DPM Table does not exist!", __func__);
2296 return 0;
2297 }
2298 if (table->count <= 0) {
2299 pr_err("[%s] DPM Table has no entry!", __func__);
2300 return 0;
2301 }
2302 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2303 pr_err("[%s] DPM Table has too many entries!", __func__);
2304 return MAX_REGULAR_DPM_NUMBER - 1;
2305 }
2306
2307 for (i = table->count - 1; i >= 0; i--) {
2308 if (table->dpm_levels[i].enabled)
2309 break;
2310 }
2311 if (i < 0) {
2312 i = 0;
2313 table->dpm_levels[i].enabled = true;
2314 }
2315
2316 return i;
2317}
2318
2319static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2320{
2321 uint32_t soft_level;
2322 int ret = 0;
2323 struct vega20_dpm_table *dpm_table =
2324 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2325
2326 if (highest)
2327 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2328 else
2329 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2330
2331 dpm_table->gfx_table.dpm_state.soft_min_level =
2332 dpm_table->gfx_table.dpm_state.soft_max_level =
2333 dpm_table->gfx_table.dpm_levels[soft_level].value;
2334
2335 if (highest)
2336 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2337 else
2338 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2339
2340 dpm_table->mem_table.dpm_state.soft_min_level =
2341 dpm_table->mem_table.dpm_state.soft_max_level =
2342 dpm_table->mem_table.dpm_levels[soft_level].value;
2343
2344 if (highest)
2345 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2346 else
2347 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2348
2349 dpm_table->soc_table.dpm_state.soft_min_level =
2350 dpm_table->soc_table.dpm_state.soft_max_level =
2351 dpm_table->soc_table.dpm_levels[soft_level].value;
2352
2353 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2354 if (ret) {
2355 pr_err("Failed to upload boot level to %s!\n",
2356 highest ? "highest" : "lowest");
2357 return ret;
2358 }
2359
2360 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2361 if (ret) {
2362 pr_err("Failed to upload dpm max level to %s!\n!",
2363 highest ? "highest" : "lowest");
2364 return ret;
2365 }
2366
2367 return ret;
2368}
2369
2370static int vega20_unforce_dpm_levels(struct smu_context *smu)
2371{
2372 uint32_t soft_min_level, soft_max_level;
2373 int ret = 0;
2374 struct vega20_dpm_table *dpm_table =
2375 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2376
2377 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2378 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2379 dpm_table->gfx_table.dpm_state.soft_min_level =
2380 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2381 dpm_table->gfx_table.dpm_state.soft_max_level =
2382 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2383
2384 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2385 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2386 dpm_table->mem_table.dpm_state.soft_min_level =
2387 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2388 dpm_table->mem_table.dpm_state.soft_max_level =
2389 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2390
2391 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2392 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2393 dpm_table->soc_table.dpm_state.soft_min_level =
2394 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2395 dpm_table->soc_table.dpm_state.soft_max_level =
2396 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2397
2398 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2399 if (ret) {
2400 pr_err("Failed to upload DPM Bootup Levels!");
2401 return ret;
2402 }
2403
2404 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2405 if (ret) {
2406 pr_err("Failed to upload DPM Max Levels!");
2407 return ret;
2408 }
2409
2410 return ret;
2411}
2412
2413static int vega20_update_specified_od8_value(struct smu_context *smu,
2414 uint32_t index,
2415 uint32_t value)
2416{
2417 struct smu_table_context *table_context = &smu->smu_table;
2418 OverDriveTable_t *od_table =
2419 (OverDriveTable_t *)(table_context->overdrive_table);
2420 struct vega20_od8_settings *od8_settings =
2421 (struct vega20_od8_settings *)smu->od_settings;
2422
2423 switch (index) {
2424 case OD8_SETTING_GFXCLK_FMIN:
2425 od_table->GfxclkFmin = (uint16_t)value;
2426 break;
2427
2428 case OD8_SETTING_GFXCLK_FMAX:
2429 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2430 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2431 return -EINVAL;
2432 od_table->GfxclkFmax = (uint16_t)value;
2433 break;
2434
2435 case OD8_SETTING_GFXCLK_FREQ1:
2436 od_table->GfxclkFreq1 = (uint16_t)value;
2437 break;
2438
2439 case OD8_SETTING_GFXCLK_VOLTAGE1:
2440 od_table->GfxclkVolt1 = (uint16_t)value;
2441 break;
2442
2443 case OD8_SETTING_GFXCLK_FREQ2:
2444 od_table->GfxclkFreq2 = (uint16_t)value;
2445 break;
2446
2447 case OD8_SETTING_GFXCLK_VOLTAGE2:
2448 od_table->GfxclkVolt2 = (uint16_t)value;
2449 break;
2450
2451 case OD8_SETTING_GFXCLK_FREQ3:
2452 od_table->GfxclkFreq3 = (uint16_t)value;
2453 break;
2454
2455 case OD8_SETTING_GFXCLK_VOLTAGE3:
2456 od_table->GfxclkVolt3 = (uint16_t)value;
2457 break;
2458
2459 case OD8_SETTING_UCLK_FMAX:
2460 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2461 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2462 return -EINVAL;
2463 od_table->UclkFmax = (uint16_t)value;
2464 break;
2465
2466 case OD8_SETTING_POWER_PERCENTAGE:
2467 od_table->OverDrivePct = (int16_t)value;
2468 break;
2469
2470 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2471 od_table->FanMaximumRpm = (uint16_t)value;
2472 break;
2473
2474 case OD8_SETTING_FAN_MIN_SPEED:
2475 od_table->FanMinimumPwm = (uint16_t)value;
2476 break;
2477
2478 case OD8_SETTING_FAN_TARGET_TEMP:
2479 od_table->FanTargetTemperature = (uint16_t)value;
2480 break;
2481
2482 case OD8_SETTING_OPERATING_TEMP_MAX:
2483 od_table->MaxOpTemp = (uint16_t)value;
2484 break;
2485 }
2486
2487 return 0;
2488}
2489
2490static int vega20_update_od8_settings(struct smu_context *smu,
2491 uint32_t index,
2492 uint32_t value)
2493{
2494 struct smu_table_context *table_context = &smu->smu_table;
2495 int ret;
2496
2497 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2498 table_context->overdrive_table, false);
2499 if (ret) {
2500 pr_err("Failed to export over drive table!\n");
2501 return ret;
2502 }
2503
2504 ret = vega20_update_specified_od8_value(smu, index, value);
2505 if (ret)
2506 return ret;
2507
2508 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2509 table_context->overdrive_table, true);
2510 if (ret) {
2511 pr_err("Failed to import over drive table!\n");
2512 return ret;
2513 }
2514
2515 return 0;
2516}
2517
2518static int vega20_set_od_percentage(struct smu_context *smu,
2519 enum smu_clk_type clk_type,
2520 uint32_t value)
2521{
2522 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2523 struct vega20_dpm_table *dpm_table = NULL;
2524 struct vega20_dpm_table *golden_table = NULL;
2525 struct vega20_single_dpm_table *single_dpm_table;
2526 struct vega20_single_dpm_table *golden_dpm_table;
2527 uint32_t od_clk, index;
2528 int ret = 0;
2529 int feature_enabled;
2530 PPCLK_e clk_id;
2531
2532 mutex_lock(&(smu->mutex));
2533
2534 dpm_table = smu_dpm->dpm_context;
2535 golden_table = smu_dpm->golden_dpm_context;
2536
2537 switch (clk_type) {
2538 case SMU_OD_SCLK:
2539 single_dpm_table = &(dpm_table->gfx_table);
2540 golden_dpm_table = &(golden_table->gfx_table);
2541 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2542 clk_id = PPCLK_GFXCLK;
2543 index = OD8_SETTING_GFXCLK_FMAX;
2544 break;
2545 case SMU_OD_MCLK:
2546 single_dpm_table = &(dpm_table->mem_table);
2547 golden_dpm_table = &(golden_table->mem_table);
2548 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2549 clk_id = PPCLK_UCLK;
2550 index = OD8_SETTING_UCLK_FMAX;
2551 break;
2552 default:
2553 ret = -EINVAL;
2554 break;
2555 }
2556
2557 if (ret)
2558 goto set_od_failed;
2559
2560 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2561 od_clk /= 100;
2562 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2563
2564 ret = vega20_update_od8_settings(smu, index, od_clk);
2565 if (ret) {
2566 pr_err("[Setoverdrive] failed to set od clk!\n");
2567 goto set_od_failed;
2568 }
2569
2570 if (feature_enabled) {
2571 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2572 clk_id);
2573 if (ret) {
2574 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2575 goto set_od_failed;
2576 }
2577 } else {
2578 single_dpm_table->count = 1;
2579 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2580 }
2581
2582 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2583 AMD_PP_TASK_READJUST_POWER_STATE);
2584
2585set_od_failed:
2586 mutex_unlock(&(smu->mutex));
2587
2588 return ret;
2589}
2590
2591static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2592 enum PP_OD_DPM_TABLE_COMMAND type,
2593 long *input, uint32_t size)
2594{
2595 struct smu_table_context *table_context = &smu->smu_table;
2596 OverDriveTable_t *od_table =
2597 (OverDriveTable_t *)(table_context->overdrive_table);
2598 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2599 struct vega20_dpm_table *dpm_table = NULL;
2600 struct vega20_single_dpm_table *single_dpm_table;
2601 struct vega20_od8_settings *od8_settings =
2602 (struct vega20_od8_settings *)smu->od_settings;
2603 struct pp_clock_levels_with_latency clocks;
2604 int32_t input_index, input_clk, input_vol, i;
2605 int od8_id;
2606 int ret = 0;
2607
2608 dpm_table = smu_dpm->dpm_context;
2609
2610 if (!input) {
2611 pr_warn("NULL user input for clock and voltage\n");
2612 return -EINVAL;
2613 }
2614
2615 switch (type) {
2616 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2617 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2618 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2619 pr_info("Sclk min/max frequency overdrive not supported\n");
2620 return -EOPNOTSUPP;
2621 }
2622
2623 for (i = 0; i < size; i += 2) {
2624 if (i + 2 > size) {
2625 pr_info("invalid number of input parameters %d\n", size);
2626 return -EINVAL;
2627 }
2628
2629 input_index = input[i];
2630 input_clk = input[i + 1];
2631
2632 if (input_index != 0 && input_index != 1) {
2633 pr_info("Invalid index %d\n", input_index);
2634 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2635 return -EINVAL;
2636 }
2637
2638 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2639 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2640 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2641 input_clk,
2642 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2643 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2644 return -EINVAL;
2645 }
2646
2647 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2648 od_table->GfxclkFmin = input_clk;
2649 od8_settings->od_gfxclk_update = true;
2650 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2651 od_table->GfxclkFmax = input_clk;
2652 od8_settings->od_gfxclk_update = true;
2653 }
2654 }
2655
2656 break;
2657
2658 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2659 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2660 pr_info("Mclk max frequency overdrive not supported\n");
2661 return -EOPNOTSUPP;
2662 }
2663
2664 single_dpm_table = &(dpm_table->mem_table);
2665 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2666 if (ret) {
2667 pr_err("Attempt to get memory clk levels Failed!");
2668 return ret;
2669 }
2670
2671 for (i = 0; i < size; i += 2) {
2672 if (i + 2 > size) {
2673 pr_info("invalid number of input parameters %d\n",
2674 size);
2675 return -EINVAL;
2676 }
2677
2678 input_index = input[i];
2679 input_clk = input[i + 1];
2680
2681 if (input_index != 1) {
2682 pr_info("Invalid index %d\n", input_index);
2683 pr_info("Support max Mclk frequency setting only which index by 1\n");
2684 return -EINVAL;
2685 }
2686
2687 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2688 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2689 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2690 input_clk,
2691 clocks.data[0].clocks_in_khz / 1000,
2692 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2693 return -EINVAL;
2694 }
2695
2696 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2697 od8_settings->od_gfxclk_update = true;
2698 od_table->UclkFmax = input_clk;
2699 }
2700 }
2701
2702 break;
2703
2704 case PP_OD_EDIT_VDDC_CURVE:
2705 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2706 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2707 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2708 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2709 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2710 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2711 pr_info("Voltage curve calibrate not supported\n");
2712 return -EOPNOTSUPP;
2713 }
2714
2715 for (i = 0; i < size; i += 3) {
2716 if (i + 3 > size) {
2717 pr_info("invalid number of input parameters %d\n",
2718 size);
2719 return -EINVAL;
2720 }
2721
2722 input_index = input[i];
2723 input_clk = input[i + 1];
2724 input_vol = input[i + 2];
2725
2726 if (input_index > 2) {
2727 pr_info("Setting for point %d is not supported\n",
2728 input_index + 1);
2729 pr_info("Three supported points index by 0, 1, 2\n");
2730 return -EINVAL;
2731 }
2732
2733 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2734 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2735 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2736 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2737 input_clk,
2738 od8_settings->od8_settings_array[od8_id].min_value,
2739 od8_settings->od8_settings_array[od8_id].max_value);
2740 return -EINVAL;
2741 }
2742
2743 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2744 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2745 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2746 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2747 input_vol,
2748 od8_settings->od8_settings_array[od8_id].min_value,
2749 od8_settings->od8_settings_array[od8_id].max_value);
2750 return -EINVAL;
2751 }
2752
2753 switch (input_index) {
2754 case 0:
2755 od_table->GfxclkFreq1 = input_clk;
2756 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2757 break;
2758 case 1:
2759 od_table->GfxclkFreq2 = input_clk;
2760 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2761 break;
2762 case 2:
2763 od_table->GfxclkFreq3 = input_clk;
2764 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2765 break;
2766 }
2767 }
2768
2769 break;
2770
2771 case PP_OD_RESTORE_DEFAULT_TABLE:
2772 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2773 if (ret) {
2774 pr_err("Failed to export over drive table!\n");
2775 return ret;
2776 }
2777
2778 break;
2779
2780 case PP_OD_COMMIT_DPM_TABLE:
2781 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2782 if (ret) {
2783 pr_err("Failed to import over drive table!\n");
2784 return ret;
2785 }
2786
2787
2788 if (od8_settings->od_gfxclk_update) {
2789 od8_settings->od_gfxclk_update = false;
2790 single_dpm_table = &(dpm_table->gfx_table);
2791
2792 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2793 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2794 PPCLK_GFXCLK);
2795 if (ret) {
2796 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2797 return ret;
2798 }
2799 } else {
2800 single_dpm_table->count = 1;
2801 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2802 }
2803 }
2804
2805 break;
2806
2807 default:
2808 return -EINVAL;
2809 }
2810
2811 if (type == PP_OD_COMMIT_DPM_TABLE) {
2812 mutex_lock(&(smu->mutex));
2813 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2814 AMD_PP_TASK_READJUST_POWER_STATE);
2815 mutex_unlock(&(smu->mutex));
2816 }
2817
2818 return ret;
2819}
2820
2821static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2822{
2823 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2824 return 0;
2825
2826 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2827 return 0;
2828
2829 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2830}
2831
2832static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2833{
2834 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2835 return 0;
2836
2837 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2838 return 0;
2839
2840 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2841}
2842
2843static int vega20_get_enabled_smc_features(struct smu_context *smu,
2844 uint64_t *features_enabled)
2845{
2846 uint32_t feature_mask[2] = {0, 0};
2847 int ret = 0;
2848
2849 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2850 if (ret)
2851 return ret;
2852
2853 *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2854 (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2855
2856 return ret;
2857}
2858
2859static int vega20_enable_smc_features(struct smu_context *smu,
2860 bool enable, uint64_t feature_mask)
2861{
2862 uint32_t smu_features_low, smu_features_high;
2863 int ret = 0;
2864
2865 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2866 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2867
2868 if (enable) {
2869 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2870 smu_features_low);
2871 if (ret)
2872 return ret;
2873 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2874 smu_features_high);
2875 if (ret)
2876 return ret;
2877 } else {
2878 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2879 smu_features_low);
2880 if (ret)
2881 return ret;
2882 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2883 smu_features_high);
2884 if (ret)
2885 return ret;
2886 }
2887
2888 return 0;
2889
2890}
2891
2892static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2893{
2894 static const char *ppfeature_name[] = {
2895 "DPM_PREFETCHER",
2896 "GFXCLK_DPM",
2897 "UCLK_DPM",
2898 "SOCCLK_DPM",
2899 "UVD_DPM",
2900 "VCE_DPM",
2901 "ULV",
2902 "MP0CLK_DPM",
2903 "LINK_DPM",
2904 "DCEFCLK_DPM",
2905 "GFXCLK_DS",
2906 "SOCCLK_DS",
2907 "LCLK_DS",
2908 "PPT",
2909 "TDC",
2910 "THERMAL",
2911 "GFX_PER_CU_CG",
2912 "RM",
2913 "DCEFCLK_DS",
2914 "ACDC",
2915 "VR0HOT",
2916 "VR1HOT",
2917 "FW_CTF",
2918 "LED_DISPLAY",
2919 "FAN_CONTROL",
2920 "GFX_EDC",
2921 "GFXOFF",
2922 "CG",
2923 "FCLK_DPM",
2924 "FCLK_DS",
2925 "MP1CLK_DS",
2926 "MP0CLK_DS",
2927 "XGMI",
2928 "ECC"};
2929 static const char *output_title[] = {
2930 "FEATURES",
2931 "BITMASK",
2932 "ENABLEMENT"};
2933 uint64_t features_enabled;
2934 int i;
2935 int ret = 0;
2936 int size = 0;
2937
2938 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2939 if (ret)
2940 return ret;
2941
2942 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2943 size += sprintf(buf + size, "%-19s %-22s %s\n",
2944 output_title[0],
2945 output_title[1],
2946 output_title[2]);
2947 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2948 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2949 ppfeature_name[i],
2950 1ULL << i,
2951 (features_enabled & (1ULL << i)) ? "Y" : "N");
2952 }
2953
2954 return size;
2955}
2956
2957static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2958{
2959 uint64_t features_enabled;
2960 uint64_t features_to_enable;
2961 uint64_t features_to_disable;
2962 int ret = 0;
2963
2964 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2965 return -EINVAL;
2966
2967 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2968 if (ret)
2969 return ret;
2970
2971 features_to_disable =
2972 features_enabled & ~new_ppfeature_masks;
2973 features_to_enable =
2974 ~features_enabled & new_ppfeature_masks;
2975
2976 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2977 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2978
2979 if (features_to_disable) {
2980 ret = vega20_enable_smc_features(smu, false, features_to_disable);
2981 if (ret)
2982 return ret;
2983 }
2984
2985 if (features_to_enable) {
2986 ret = vega20_enable_smc_features(smu, true, features_to_enable);
2987 if (ret)
2988 return ret;
2989 }
2990
2991 return 0;
2992}
2993
2994static bool vega20_is_dpm_running(struct smu_context *smu)
2995{
2996 int ret = 0;
2997 uint32_t feature_mask[2];
2998 unsigned long feature_enabled;
2999 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
3000 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
3001 ((uint64_t)feature_mask[1] << 32));
3002 return !!(feature_enabled & SMC_DPM_FEATURE);
3003}
3004
3005static int vega20_set_thermal_fan_table(struct smu_context *smu)
3006{
3007 int ret;
3008 struct smu_table_context *table_context = &smu->smu_table;
3009 PPTable_t *pptable = table_context->driver_pptable;
3010
3011 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
3012 (uint32_t)pptable->FanTargetTemperature);
3013
3014 return ret;
3015}
3016
3017static int vega20_get_fan_speed_rpm(struct smu_context *smu,
3018 uint32_t *speed)
3019{
3020 int ret;
3021
3022 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
3023
3024 if (ret) {
3025 pr_err("Attempt to get current RPM from SMC Failed!\n");
3026 return ret;
3027 }
3028
3029 smu_read_smc_arg(smu, speed);
3030
3031 return 0;
3032}
3033
3034static int vega20_get_fan_speed_percent(struct smu_context *smu,
3035 uint32_t *speed)
3036{
3037 int ret = 0;
3038 uint32_t current_rpm = 0, percent = 0;
3039 PPTable_t *pptable = smu->smu_table.driver_pptable;
3040
3041 ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm);
3042 if (ret)
3043 return ret;
3044
3045 percent = current_rpm * 100 / pptable->FanMaximumRpm;
3046 *speed = percent > 100 ? 100 : percent;
3047
3048 return 0;
3049}
3050
3051static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
3052{
3053 uint32_t smu_version;
3054 int ret = 0;
3055 SmuMetrics_t metrics;
3056
3057 if (!value)
3058 return -EINVAL;
3059
3060 ret = vega20_get_metrics_table(smu, &metrics);
3061 if (ret)
3062 return ret;
3063
3064 ret = smu_get_smc_version(smu, NULL, &smu_version);
3065 if (ret)
3066 return ret;
3067
3068
3069 if (smu_version == 0x282e00)
3070 *value = metrics.AverageSocketPower << 8;
3071 else
3072 *value = metrics.CurrSocketPower << 8;
3073
3074 return 0;
3075}
3076
3077static int vega20_get_current_activity_percent(struct smu_context *smu,
3078 enum amd_pp_sensors sensor,
3079 uint32_t *value)
3080{
3081 int ret = 0;
3082 SmuMetrics_t metrics;
3083
3084 if (!value)
3085 return -EINVAL;
3086
3087 ret = vega20_get_metrics_table(smu, &metrics);
3088 if (ret)
3089 return ret;
3090
3091 switch (sensor) {
3092 case AMDGPU_PP_SENSOR_GPU_LOAD:
3093 *value = metrics.AverageGfxActivity;
3094 break;
3095 case AMDGPU_PP_SENSOR_MEM_LOAD:
3096 *value = metrics.AverageUclkActivity;
3097 break;
3098 default:
3099 pr_err("Invalid sensor for retrieving clock activity\n");
3100 return -EINVAL;
3101 }
3102
3103 return 0;
3104}
3105
3106static int vega20_thermal_get_temperature(struct smu_context *smu,
3107 enum amd_pp_sensors sensor,
3108 uint32_t *value)
3109{
3110 struct amdgpu_device *adev = smu->adev;
3111 SmuMetrics_t metrics;
3112 uint32_t temp = 0;
3113 int ret = 0;
3114
3115 if (!value)
3116 return -EINVAL;
3117
3118 ret = vega20_get_metrics_table(smu, &metrics);
3119 if (ret)
3120 return ret;
3121
3122 switch (sensor) {
3123 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3124 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
3125 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
3126 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
3127
3128 temp = temp & 0x1ff;
3129 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3130
3131 *value = temp;
3132 break;
3133 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3134 *value = metrics.TemperatureEdge *
3135 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3136 break;
3137 case AMDGPU_PP_SENSOR_MEM_TEMP:
3138 *value = metrics.TemperatureHBM *
3139 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3140 break;
3141 default:
3142 pr_err("Invalid sensor for retrieving temp\n");
3143 return -EINVAL;
3144 }
3145
3146 return 0;
3147}
3148static int vega20_read_sensor(struct smu_context *smu,
3149 enum amd_pp_sensors sensor,
3150 void *data, uint32_t *size)
3151{
3152 int ret = 0;
3153 struct smu_table_context *table_context = &smu->smu_table;
3154 PPTable_t *pptable = table_context->driver_pptable;
3155
3156 switch (sensor) {
3157 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3158 *(uint32_t *)data = pptable->FanMaximumRpm;
3159 *size = 4;
3160 break;
3161 case AMDGPU_PP_SENSOR_MEM_LOAD:
3162 case AMDGPU_PP_SENSOR_GPU_LOAD:
3163 ret = vega20_get_current_activity_percent(smu,
3164 sensor,
3165 (uint32_t *)data);
3166 *size = 4;
3167 break;
3168 case AMDGPU_PP_SENSOR_GPU_POWER:
3169 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3170 *size = 4;
3171 break;
3172 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3173 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3174 case AMDGPU_PP_SENSOR_MEM_TEMP:
3175 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3176 *size = 4;
3177 break;
3178 default:
3179 return -EINVAL;
3180 }
3181
3182 return ret;
3183}
3184
3185static int vega20_set_watermarks_table(struct smu_context *smu,
3186 void *watermarks, struct
3187 dm_pp_wm_sets_with_clock_ranges_soc15
3188 *clock_ranges)
3189{
3190 int i;
3191 Watermarks_t *table = watermarks;
3192
3193 if (!table || !clock_ranges)
3194 return -EINVAL;
3195
3196 if (clock_ranges->num_wm_dmif_sets > 4 ||
3197 clock_ranges->num_wm_mcif_sets > 4)
3198 return -EINVAL;
3199
3200 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3201 table->WatermarkRow[1][i].MinClock =
3202 cpu_to_le16((uint16_t)
3203 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3204 1000));
3205 table->WatermarkRow[1][i].MaxClock =
3206 cpu_to_le16((uint16_t)
3207 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3208 1000));
3209 table->WatermarkRow[1][i].MinUclk =
3210 cpu_to_le16((uint16_t)
3211 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3212 1000));
3213 table->WatermarkRow[1][i].MaxUclk =
3214 cpu_to_le16((uint16_t)
3215 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3216 1000));
3217 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3218 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3219 }
3220
3221 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3222 table->WatermarkRow[0][i].MinClock =
3223 cpu_to_le16((uint16_t)
3224 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3225 1000));
3226 table->WatermarkRow[0][i].MaxClock =
3227 cpu_to_le16((uint16_t)
3228 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3229 1000));
3230 table->WatermarkRow[0][i].MinUclk =
3231 cpu_to_le16((uint16_t)
3232 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3233 1000));
3234 table->WatermarkRow[0][i].MaxUclk =
3235 cpu_to_le16((uint16_t)
3236 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3237 1000));
3238 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3239 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3240 }
3241
3242 return 0;
3243}
3244
3245static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3246 struct smu_temperature_range *range)
3247{
3248 struct smu_table_context *table_context = &smu->smu_table;
3249 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3250 PPTable_t *pptable = smu->smu_table.driver_pptable;
3251
3252 if (!range || !powerplay_table)
3253 return -EINVAL;
3254
3255
3256 range->min = 0;
3257 range->max = powerplay_table->usSoftwareShutdownTemp;
3258 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE);
3259 range->hotspot_crit_max = pptable->ThotspotLimit;
3260 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT);
3261 range->mem_crit_max = pptable->ThbmLimit;
3262 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM);
3263
3264
3265 return 0;
3266}
3267
3268static const struct pptable_funcs vega20_ppt_funcs = {
3269 .tables_init = vega20_tables_init,
3270 .alloc_dpm_context = vega20_allocate_dpm_context,
3271 .store_powerplay_table = vega20_store_powerplay_table,
3272 .check_powerplay_table = vega20_check_powerplay_table,
3273 .append_powerplay_table = vega20_append_powerplay_table,
3274 .get_smu_msg_index = vega20_get_smu_msg_index,
3275 .get_smu_clk_index = vega20_get_smu_clk_index,
3276 .get_smu_feature_index = vega20_get_smu_feature_index,
3277 .get_smu_table_index = vega20_get_smu_table_index,
3278 .get_smu_power_index = vega20_get_pwr_src_index,
3279 .get_workload_type = vega20_get_workload_type,
3280 .run_afll_btc = vega20_run_btc_afll,
3281 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3282 .get_current_power_state = vega20_get_current_power_state,
3283 .set_default_dpm_table = vega20_set_default_dpm_table,
3284 .set_power_state = NULL,
3285 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3286 .print_clk_levels = vega20_print_clk_levels,
3287 .force_clk_levels = vega20_force_clk_levels,
3288 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3289 .get_od_percentage = vega20_get_od_percentage,
3290 .get_power_profile_mode = vega20_get_power_profile_mode,
3291 .set_power_profile_mode = vega20_set_power_profile_mode,
3292 .set_od_percentage = vega20_set_od_percentage,
3293 .set_default_od_settings = vega20_set_default_od_settings,
3294 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3295 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3296 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3297 .read_sensor = vega20_read_sensor,
3298 .pre_display_config_changed = vega20_pre_display_config_changed,
3299 .display_config_changed = vega20_display_config_changed,
3300 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3301 .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3302 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3303 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3304 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3305 .set_ppfeature_status = vega20_set_ppfeature_status,
3306 .get_ppfeature_status = vega20_get_ppfeature_status,
3307 .is_dpm_running = vega20_is_dpm_running,
3308 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3309 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3310 .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3311 .set_watermarks_table = vega20_set_watermarks_table,
3312 .get_thermal_temperature_range = vega20_get_thermal_temperature_range
3313};
3314
3315void vega20_set_ppt_funcs(struct smu_context *smu)
3316{
3317 struct smu_table_context *smu_table = &smu->smu_table;
3318
3319 smu->ppt_funcs = &vega20_ppt_funcs;
3320 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3321 smu_table->table_count = TABLE_COUNT;
3322}
3323
