linux/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef __DW_HDMI_H__
   7#define __DW_HDMI_H__
   8
   9/* Identification Registers */
  10#define HDMI_DESIGN_ID                          0x0000
  11#define HDMI_REVISION_ID                        0x0001
  12#define HDMI_PRODUCT_ID0                        0x0002
  13#define HDMI_PRODUCT_ID1                        0x0003
  14#define HDMI_CONFIG0_ID                         0x0004
  15#define HDMI_CONFIG1_ID                         0x0005
  16#define HDMI_CONFIG2_ID                         0x0006
  17#define HDMI_CONFIG3_ID                         0x0007
  18
  19/* Interrupt Registers */
  20#define HDMI_IH_FC_STAT0                        0x0100
  21#define HDMI_IH_FC_STAT1                        0x0101
  22#define HDMI_IH_FC_STAT2                        0x0102
  23#define HDMI_IH_AS_STAT0                        0x0103
  24#define HDMI_IH_PHY_STAT0                       0x0104
  25#define HDMI_IH_I2CM_STAT0                      0x0105
  26#define HDMI_IH_CEC_STAT0                       0x0106
  27#define HDMI_IH_VP_STAT0                        0x0107
  28#define HDMI_IH_I2CMPHY_STAT0                   0x0108
  29#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
  30
  31#define HDMI_IH_MUTE_FC_STAT0                   0x0180
  32#define HDMI_IH_MUTE_FC_STAT1                   0x0181
  33#define HDMI_IH_MUTE_FC_STAT2                   0x0182
  34#define HDMI_IH_MUTE_AS_STAT0                   0x0183
  35#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
  36#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
  37#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
  38#define HDMI_IH_MUTE_VP_STAT0                   0x0187
  39#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
  40#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
  41#define HDMI_IH_MUTE                            0x01FF
  42
  43/* Video Sample Registers */
  44#define HDMI_TX_INVID0                          0x0200
  45#define HDMI_TX_INSTUFFING                      0x0201
  46#define HDMI_TX_GYDATA0                         0x0202
  47#define HDMI_TX_GYDATA1                         0x0203
  48#define HDMI_TX_RCRDATA0                        0x0204
  49#define HDMI_TX_RCRDATA1                        0x0205
  50#define HDMI_TX_BCBDATA0                        0x0206
  51#define HDMI_TX_BCBDATA1                        0x0207
  52
  53/* Video Packetizer Registers */
  54#define HDMI_VP_STATUS                          0x0800
  55#define HDMI_VP_PR_CD                           0x0801
  56#define HDMI_VP_STUFF                           0x0802
  57#define HDMI_VP_REMAP                           0x0803
  58#define HDMI_VP_CONF                            0x0804
  59#define HDMI_VP_STAT                            0x0805
  60#define HDMI_VP_INT                             0x0806
  61#define HDMI_VP_MASK                            0x0807
  62#define HDMI_VP_POL                             0x0808
  63
  64/* Frame Composer Registers */
  65#define HDMI_FC_INVIDCONF                       0x1000
  66#define HDMI_FC_INHACTV0                        0x1001
  67#define HDMI_FC_INHACTV1                        0x1002
  68#define HDMI_FC_INHBLANK0                       0x1003
  69#define HDMI_FC_INHBLANK1                       0x1004
  70#define HDMI_FC_INVACTV0                        0x1005
  71#define HDMI_FC_INVACTV1                        0x1006
  72#define HDMI_FC_INVBLANK                        0x1007
  73#define HDMI_FC_HSYNCINDELAY0                   0x1008
  74#define HDMI_FC_HSYNCINDELAY1                   0x1009
  75#define HDMI_FC_HSYNCINWIDTH0                   0x100A
  76#define HDMI_FC_HSYNCINWIDTH1                   0x100B
  77#define HDMI_FC_VSYNCINDELAY                    0x100C
  78#define HDMI_FC_VSYNCINWIDTH                    0x100D
  79#define HDMI_FC_INFREQ0                         0x100E
  80#define HDMI_FC_INFREQ1                         0x100F
  81#define HDMI_FC_INFREQ2                         0x1010
  82#define HDMI_FC_CTRLDUR                         0x1011
  83#define HDMI_FC_EXCTRLDUR                       0x1012
  84#define HDMI_FC_EXCTRLSPAC                      0x1013
  85#define HDMI_FC_CH0PREAM                        0x1014
  86#define HDMI_FC_CH1PREAM                        0x1015
  87#define HDMI_FC_CH2PREAM                        0x1016
  88#define HDMI_FC_AVICONF3                        0x1017
  89#define HDMI_FC_GCP                             0x1018
  90#define HDMI_FC_AVICONF0                        0x1019
  91#define HDMI_FC_AVICONF1                        0x101A
  92#define HDMI_FC_AVICONF2                        0x101B
  93#define HDMI_FC_AVIVID                          0x101C
  94#define HDMI_FC_AVIETB0                         0x101D
  95#define HDMI_FC_AVIETB1                         0x101E
  96#define HDMI_FC_AVISBB0                         0x101F
  97#define HDMI_FC_AVISBB1                         0x1020
  98#define HDMI_FC_AVIELB0                         0x1021
  99#define HDMI_FC_AVIELB1                         0x1022
 100#define HDMI_FC_AVISRB0                         0x1023
 101#define HDMI_FC_AVISRB1                         0x1024
 102#define HDMI_FC_AUDICONF0                       0x1025
 103#define HDMI_FC_AUDICONF1                       0x1026
 104#define HDMI_FC_AUDICONF2                       0x1027
 105#define HDMI_FC_AUDICONF3                       0x1028
 106#define HDMI_FC_VSDIEEEID0                      0x1029
 107#define HDMI_FC_VSDSIZE                         0x102A
 108#define HDMI_FC_VSDIEEEID1                      0x1030
 109#define HDMI_FC_VSDIEEEID2                      0x1031
 110#define HDMI_FC_VSDPAYLOAD0                     0x1032
 111#define HDMI_FC_VSDPAYLOAD1                     0x1033
 112#define HDMI_FC_VSDPAYLOAD2                     0x1034
 113#define HDMI_FC_VSDPAYLOAD3                     0x1035
 114#define HDMI_FC_VSDPAYLOAD4                     0x1036
 115#define HDMI_FC_VSDPAYLOAD5                     0x1037
 116#define HDMI_FC_VSDPAYLOAD6                     0x1038
 117#define HDMI_FC_VSDPAYLOAD7                     0x1039
 118#define HDMI_FC_VSDPAYLOAD8                     0x103A
 119#define HDMI_FC_VSDPAYLOAD9                     0x103B
 120#define HDMI_FC_VSDPAYLOAD10                    0x103C
 121#define HDMI_FC_VSDPAYLOAD11                    0x103D
 122#define HDMI_FC_VSDPAYLOAD12                    0x103E
 123#define HDMI_FC_VSDPAYLOAD13                    0x103F
 124#define HDMI_FC_VSDPAYLOAD14                    0x1040
 125#define HDMI_FC_VSDPAYLOAD15                    0x1041
 126#define HDMI_FC_VSDPAYLOAD16                    0x1042
 127#define HDMI_FC_VSDPAYLOAD17                    0x1043
 128#define HDMI_FC_VSDPAYLOAD18                    0x1044
 129#define HDMI_FC_VSDPAYLOAD19                    0x1045
 130#define HDMI_FC_VSDPAYLOAD20                    0x1046
 131#define HDMI_FC_VSDPAYLOAD21                    0x1047
 132#define HDMI_FC_VSDPAYLOAD22                    0x1048
 133#define HDMI_FC_VSDPAYLOAD23                    0x1049
 134#define HDMI_FC_SPDVENDORNAME0                  0x104A
 135#define HDMI_FC_SPDVENDORNAME1                  0x104B
 136#define HDMI_FC_SPDVENDORNAME2                  0x104C
 137#define HDMI_FC_SPDVENDORNAME3                  0x104D
 138#define HDMI_FC_SPDVENDORNAME4                  0x104E
 139#define HDMI_FC_SPDVENDORNAME5                  0x104F
 140#define HDMI_FC_SPDVENDORNAME6                  0x1050
 141#define HDMI_FC_SPDVENDORNAME7                  0x1051
 142#define HDMI_FC_SDPPRODUCTNAME0                 0x1052
 143#define HDMI_FC_SDPPRODUCTNAME1                 0x1053
 144#define HDMI_FC_SDPPRODUCTNAME2                 0x1054
 145#define HDMI_FC_SDPPRODUCTNAME3                 0x1055
 146#define HDMI_FC_SDPPRODUCTNAME4                 0x1056
 147#define HDMI_FC_SDPPRODUCTNAME5                 0x1057
 148#define HDMI_FC_SDPPRODUCTNAME6                 0x1058
 149#define HDMI_FC_SDPPRODUCTNAME7                 0x1059
 150#define HDMI_FC_SDPPRODUCTNAME8                 0x105A
 151#define HDMI_FC_SDPPRODUCTNAME9                 0x105B
 152#define HDMI_FC_SDPPRODUCTNAME10                0x105C
 153#define HDMI_FC_SDPPRODUCTNAME11                0x105D
 154#define HDMI_FC_SDPPRODUCTNAME12                0x105E
 155#define HDMI_FC_SDPPRODUCTNAME13                0x105F
 156#define HDMI_FC_SDPPRODUCTNAME14                0x1060
 157#define HDMI_FC_SPDPRODUCTNAME15                0x1061
 158#define HDMI_FC_SPDDEVICEINF                    0x1062
 159#define HDMI_FC_AUDSCONF                        0x1063
 160#define HDMI_FC_AUDSSTAT                        0x1064
 161#define HDMI_FC_DATACH0FILL                     0x1070
 162#define HDMI_FC_DATACH1FILL                     0x1071
 163#define HDMI_FC_DATACH2FILL                     0x1072
 164#define HDMI_FC_CTRLQHIGH                       0x1073
 165#define HDMI_FC_CTRLQLOW                        0x1074
 166#define HDMI_FC_ACP0                            0x1075
 167#define HDMI_FC_ACP28                           0x1076
 168#define HDMI_FC_ACP27                           0x1077
 169#define HDMI_FC_ACP26                           0x1078
 170#define HDMI_FC_ACP25                           0x1079
 171#define HDMI_FC_ACP24                           0x107A
 172#define HDMI_FC_ACP23                           0x107B
 173#define HDMI_FC_ACP22                           0x107C
 174#define HDMI_FC_ACP21                           0x107D
 175#define HDMI_FC_ACP20                           0x107E
 176#define HDMI_FC_ACP19                           0x107F
 177#define HDMI_FC_ACP18                           0x1080
 178#define HDMI_FC_ACP17                           0x1081
 179#define HDMI_FC_ACP16                           0x1082
 180#define HDMI_FC_ACP15                           0x1083
 181#define HDMI_FC_ACP14                           0x1084
 182#define HDMI_FC_ACP13                           0x1085
 183#define HDMI_FC_ACP12                           0x1086
 184#define HDMI_FC_ACP11                           0x1087
 185#define HDMI_FC_ACP10                           0x1088
 186#define HDMI_FC_ACP9                            0x1089
 187#define HDMI_FC_ACP8                            0x108A
 188#define HDMI_FC_ACP7                            0x108B
 189#define HDMI_FC_ACP6                            0x108C
 190#define HDMI_FC_ACP5                            0x108D
 191#define HDMI_FC_ACP4                            0x108E
 192#define HDMI_FC_ACP3                            0x108F
 193#define HDMI_FC_ACP2                            0x1090
 194#define HDMI_FC_ACP1                            0x1091
 195#define HDMI_FC_ISCR1_0                         0x1092
 196#define HDMI_FC_ISCR1_16                        0x1093
 197#define HDMI_FC_ISCR1_15                        0x1094
 198#define HDMI_FC_ISCR1_14                        0x1095
 199#define HDMI_FC_ISCR1_13                        0x1096
 200#define HDMI_FC_ISCR1_12                        0x1097
 201#define HDMI_FC_ISCR1_11                        0x1098
 202#define HDMI_FC_ISCR1_10                        0x1099
 203#define HDMI_FC_ISCR1_9                         0x109A
 204#define HDMI_FC_ISCR1_8                         0x109B
 205#define HDMI_FC_ISCR1_7                         0x109C
 206#define HDMI_FC_ISCR1_6                         0x109D
 207#define HDMI_FC_ISCR1_5                         0x109E
 208#define HDMI_FC_ISCR1_4                         0x109F
 209#define HDMI_FC_ISCR1_3                         0x10A0
 210#define HDMI_FC_ISCR1_2                         0x10A1
 211#define HDMI_FC_ISCR1_1                         0x10A2
 212#define HDMI_FC_ISCR2_15                        0x10A3
 213#define HDMI_FC_ISCR2_14                        0x10A4
 214#define HDMI_FC_ISCR2_13                        0x10A5
 215#define HDMI_FC_ISCR2_12                        0x10A6
 216#define HDMI_FC_ISCR2_11                        0x10A7
 217#define HDMI_FC_ISCR2_10                        0x10A8
 218#define HDMI_FC_ISCR2_9                         0x10A9
 219#define HDMI_FC_ISCR2_8                         0x10AA
 220#define HDMI_FC_ISCR2_7                         0x10AB
 221#define HDMI_FC_ISCR2_6                         0x10AC
 222#define HDMI_FC_ISCR2_5                         0x10AD
 223#define HDMI_FC_ISCR2_4                         0x10AE
 224#define HDMI_FC_ISCR2_3                         0x10AF
 225#define HDMI_FC_ISCR2_2                         0x10B0
 226#define HDMI_FC_ISCR2_1                         0x10B1
 227#define HDMI_FC_ISCR2_0                         0x10B2
 228#define HDMI_FC_DATAUTO0                        0x10B3
 229#define HDMI_FC_DATAUTO1                        0x10B4
 230#define HDMI_FC_DATAUTO2                        0x10B5
 231#define HDMI_FC_DATMAN                          0x10B6
 232#define HDMI_FC_DATAUTO3                        0x10B7
 233#define HDMI_FC_RDRB0                           0x10B8
 234#define HDMI_FC_RDRB1                           0x10B9
 235#define HDMI_FC_RDRB2                           0x10BA
 236#define HDMI_FC_RDRB3                           0x10BB
 237#define HDMI_FC_RDRB4                           0x10BC
 238#define HDMI_FC_RDRB5                           0x10BD
 239#define HDMI_FC_RDRB6                           0x10BE
 240#define HDMI_FC_RDRB7                           0x10BF
 241#define HDMI_FC_STAT0                           0x10D0
 242#define HDMI_FC_INT0                            0x10D1
 243#define HDMI_FC_MASK0                           0x10D2
 244#define HDMI_FC_POL0                            0x10D3
 245#define HDMI_FC_STAT1                           0x10D4
 246#define HDMI_FC_INT1                            0x10D5
 247#define HDMI_FC_MASK1                           0x10D6
 248#define HDMI_FC_POL1                            0x10D7
 249#define HDMI_FC_STAT2                           0x10D8
 250#define HDMI_FC_INT2                            0x10D9
 251#define HDMI_FC_MASK2                           0x10DA
 252#define HDMI_FC_POL2                            0x10DB
 253#define HDMI_FC_PRCONF                          0x10E0
 254#define HDMI_FC_SCRAMBLER_CTRL                  0x10E1
 255
 256#define HDMI_FC_GMD_STAT                        0x1100
 257#define HDMI_FC_GMD_EN                          0x1101
 258#define HDMI_FC_GMD_UP                          0x1102
 259#define HDMI_FC_GMD_CONF                        0x1103
 260#define HDMI_FC_GMD_HB                          0x1104
 261#define HDMI_FC_GMD_PB0                         0x1105
 262#define HDMI_FC_GMD_PB1                         0x1106
 263#define HDMI_FC_GMD_PB2                         0x1107
 264#define HDMI_FC_GMD_PB3                         0x1108
 265#define HDMI_FC_GMD_PB4                         0x1109
 266#define HDMI_FC_GMD_PB5                         0x110A
 267#define HDMI_FC_GMD_PB6                         0x110B
 268#define HDMI_FC_GMD_PB7                         0x110C
 269#define HDMI_FC_GMD_PB8                         0x110D
 270#define HDMI_FC_GMD_PB9                         0x110E
 271#define HDMI_FC_GMD_PB10                        0x110F
 272#define HDMI_FC_GMD_PB11                        0x1110
 273#define HDMI_FC_GMD_PB12                        0x1111
 274#define HDMI_FC_GMD_PB13                        0x1112
 275#define HDMI_FC_GMD_PB14                        0x1113
 276#define HDMI_FC_GMD_PB15                        0x1114
 277#define HDMI_FC_GMD_PB16                        0x1115
 278#define HDMI_FC_GMD_PB17                        0x1116
 279#define HDMI_FC_GMD_PB18                        0x1117
 280#define HDMI_FC_GMD_PB19                        0x1118
 281#define HDMI_FC_GMD_PB20                        0x1119
 282#define HDMI_FC_GMD_PB21                        0x111A
 283#define HDMI_FC_GMD_PB22                        0x111B
 284#define HDMI_FC_GMD_PB23                        0x111C
 285#define HDMI_FC_GMD_PB24                        0x111D
 286#define HDMI_FC_GMD_PB25                        0x111E
 287#define HDMI_FC_GMD_PB26                        0x111F
 288#define HDMI_FC_GMD_PB27                        0x1120
 289
 290#define HDMI_FC_DBGFORCE                        0x1200
 291#define HDMI_FC_DBGAUD0CH0                      0x1201
 292#define HDMI_FC_DBGAUD1CH0                      0x1202
 293#define HDMI_FC_DBGAUD2CH0                      0x1203
 294#define HDMI_FC_DBGAUD0CH1                      0x1204
 295#define HDMI_FC_DBGAUD1CH1                      0x1205
 296#define HDMI_FC_DBGAUD2CH1                      0x1206
 297#define HDMI_FC_DBGAUD0CH2                      0x1207
 298#define HDMI_FC_DBGAUD1CH2                      0x1208
 299#define HDMI_FC_DBGAUD2CH2                      0x1209
 300#define HDMI_FC_DBGAUD0CH3                      0x120A
 301#define HDMI_FC_DBGAUD1CH3                      0x120B
 302#define HDMI_FC_DBGAUD2CH3                      0x120C
 303#define HDMI_FC_DBGAUD0CH4                      0x120D
 304#define HDMI_FC_DBGAUD1CH4                      0x120E
 305#define HDMI_FC_DBGAUD2CH4                      0x120F
 306#define HDMI_FC_DBGAUD0CH5                      0x1210
 307#define HDMI_FC_DBGAUD1CH5                      0x1211
 308#define HDMI_FC_DBGAUD2CH5                      0x1212
 309#define HDMI_FC_DBGAUD0CH6                      0x1213
 310#define HDMI_FC_DBGAUD1CH6                      0x1214
 311#define HDMI_FC_DBGAUD2CH6                      0x1215
 312#define HDMI_FC_DBGAUD0CH7                      0x1216
 313#define HDMI_FC_DBGAUD1CH7                      0x1217
 314#define HDMI_FC_DBGAUD2CH7                      0x1218
 315#define HDMI_FC_DBGTMDS0                        0x1219
 316#define HDMI_FC_DBGTMDS1                        0x121A
 317#define HDMI_FC_DBGTMDS2                        0x121B
 318
 319/* HDMI Source PHY Registers */
 320#define HDMI_PHY_CONF0                          0x3000
 321#define HDMI_PHY_TST0                           0x3001
 322#define HDMI_PHY_TST1                           0x3002
 323#define HDMI_PHY_TST2                           0x3003
 324#define HDMI_PHY_STAT0                          0x3004
 325#define HDMI_PHY_INT0                           0x3005
 326#define HDMI_PHY_MASK0                          0x3006
 327#define HDMI_PHY_POL0                           0x3007
 328
 329/* HDMI Master PHY Registers */
 330#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
 331#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
 332#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
 333#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
 334#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
 335#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
 336#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
 337#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
 338#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
 339#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
 340#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
 341#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
 342#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
 343#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
 344#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
 345#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
 346#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
 347#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
 348#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
 349
 350/* Audio Sampler Registers */
 351#define HDMI_AUD_CONF0                          0x3100
 352#define HDMI_AUD_CONF1                          0x3101
 353#define HDMI_AUD_INT                            0x3102
 354#define HDMI_AUD_CONF2                          0x3103
 355#define HDMI_AUD_N1                             0x3200
 356#define HDMI_AUD_N2                             0x3201
 357#define HDMI_AUD_N3                             0x3202
 358#define HDMI_AUD_CTS1                           0x3203
 359#define HDMI_AUD_CTS2                           0x3204
 360#define HDMI_AUD_CTS3                           0x3205
 361#define HDMI_AUD_INPUTCLKFS                     0x3206
 362#define HDMI_AUD_SPDIFINT                       0x3302
 363#define HDMI_AUD_CONF0_HBR                      0x3400
 364#define HDMI_AUD_HBR_STATUS                     0x3401
 365#define HDMI_AUD_HBR_INT                        0x3402
 366#define HDMI_AUD_HBR_POL                        0x3403
 367#define HDMI_AUD_HBR_MASK                       0x3404
 368
 369/*
 370 * Generic Parallel Audio Interface Registers
 371 * Not used as GPAUD interface is not enabled in hw
 372 */
 373#define HDMI_GP_CONF0                           0x3500
 374#define HDMI_GP_CONF1                           0x3501
 375#define HDMI_GP_CONF2                           0x3502
 376#define HDMI_GP_STAT                            0x3503
 377#define HDMI_GP_INT                             0x3504
 378#define HDMI_GP_MASK                            0x3505
 379#define HDMI_GP_POL                             0x3506
 380
 381/* Audio DMA Registers */
 382#define HDMI_AHB_DMA_CONF0                      0x3600
 383#define HDMI_AHB_DMA_START                      0x3601
 384#define HDMI_AHB_DMA_STOP                       0x3602
 385#define HDMI_AHB_DMA_THRSLD                     0x3603
 386#define HDMI_AHB_DMA_STRADDR0                   0x3604
 387#define HDMI_AHB_DMA_STRADDR1                   0x3605
 388#define HDMI_AHB_DMA_STRADDR2                   0x3606
 389#define HDMI_AHB_DMA_STRADDR3                   0x3607
 390#define HDMI_AHB_DMA_STPADDR0                   0x3608
 391#define HDMI_AHB_DMA_STPADDR1                   0x3609
 392#define HDMI_AHB_DMA_STPADDR2                   0x360a
 393#define HDMI_AHB_DMA_STPADDR3                   0x360b
 394#define HDMI_AHB_DMA_BSTADDR0                   0x360c
 395#define HDMI_AHB_DMA_BSTADDR1                   0x360d
 396#define HDMI_AHB_DMA_BSTADDR2                   0x360e
 397#define HDMI_AHB_DMA_BSTADDR3                   0x360f
 398#define HDMI_AHB_DMA_MBLENGTH0                  0x3610
 399#define HDMI_AHB_DMA_MBLENGTH1                  0x3611
 400#define HDMI_AHB_DMA_STAT                       0x3612
 401#define HDMI_AHB_DMA_INT                        0x3613
 402#define HDMI_AHB_DMA_MASK                       0x3614
 403#define HDMI_AHB_DMA_POL                        0x3615
 404#define HDMI_AHB_DMA_CONF1                      0x3616
 405#define HDMI_AHB_DMA_BUFFSTAT                   0x3617
 406#define HDMI_AHB_DMA_BUFFINT                    0x3618
 407#define HDMI_AHB_DMA_BUFFMASK                   0x3619
 408#define HDMI_AHB_DMA_BUFFPOL                    0x361a
 409
 410/* Main Controller Registers */
 411#define HDMI_MC_SFRDIV                          0x4000
 412#define HDMI_MC_CLKDIS                          0x4001
 413#define HDMI_MC_SWRSTZ                          0x4002
 414#define HDMI_MC_OPCTRL                          0x4003
 415#define HDMI_MC_FLOWCTRL                        0x4004
 416#define HDMI_MC_PHYRSTZ                         0x4005
 417#define HDMI_MC_LOCKONCLOCK                     0x4006
 418#define HDMI_MC_HEACPHY_RST                     0x4007
 419
 420/* Color Space  Converter Registers */
 421#define HDMI_CSC_CFG                            0x4100
 422#define HDMI_CSC_SCALE                          0x4101
 423#define HDMI_CSC_COEF_A1_MSB                    0x4102
 424#define HDMI_CSC_COEF_A1_LSB                    0x4103
 425#define HDMI_CSC_COEF_A2_MSB                    0x4104
 426#define HDMI_CSC_COEF_A2_LSB                    0x4105
 427#define HDMI_CSC_COEF_A3_MSB                    0x4106
 428#define HDMI_CSC_COEF_A3_LSB                    0x4107
 429#define HDMI_CSC_COEF_A4_MSB                    0x4108
 430#define HDMI_CSC_COEF_A4_LSB                    0x4109
 431#define HDMI_CSC_COEF_B1_MSB                    0x410A
 432#define HDMI_CSC_COEF_B1_LSB                    0x410B
 433#define HDMI_CSC_COEF_B2_MSB                    0x410C
 434#define HDMI_CSC_COEF_B2_LSB                    0x410D
 435#define HDMI_CSC_COEF_B3_MSB                    0x410E
 436#define HDMI_CSC_COEF_B3_LSB                    0x410F
 437#define HDMI_CSC_COEF_B4_MSB                    0x4110
 438#define HDMI_CSC_COEF_B4_LSB                    0x4111
 439#define HDMI_CSC_COEF_C1_MSB                    0x4112
 440#define HDMI_CSC_COEF_C1_LSB                    0x4113
 441#define HDMI_CSC_COEF_C2_MSB                    0x4114
 442#define HDMI_CSC_COEF_C2_LSB                    0x4115
 443#define HDMI_CSC_COEF_C3_MSB                    0x4116
 444#define HDMI_CSC_COEF_C3_LSB                    0x4117
 445#define HDMI_CSC_COEF_C4_MSB                    0x4118
 446#define HDMI_CSC_COEF_C4_LSB                    0x4119
 447
 448/* HDCP Encryption Engine Registers */
 449#define HDMI_A_HDCPCFG0                         0x5000
 450#define HDMI_A_HDCPCFG1                         0x5001
 451#define HDMI_A_HDCPOBS0                         0x5002
 452#define HDMI_A_HDCPOBS1                         0x5003
 453#define HDMI_A_HDCPOBS2                         0x5004
 454#define HDMI_A_HDCPOBS3                         0x5005
 455#define HDMI_A_APIINTCLR                        0x5006
 456#define HDMI_A_APIINTSTAT                       0x5007
 457#define HDMI_A_APIINTMSK                        0x5008
 458#define HDMI_A_VIDPOLCFG                        0x5009
 459#define HDMI_A_OESSWCFG                         0x500A
 460#define HDMI_A_TIMER1SETUP0                     0x500B
 461#define HDMI_A_TIMER1SETUP1                     0x500C
 462#define HDMI_A_TIMER2SETUP0                     0x500D
 463#define HDMI_A_TIMER2SETUP1                     0x500E
 464#define HDMI_A_100MSCFG                         0x500F
 465#define HDMI_A_2SCFG0                           0x5010
 466#define HDMI_A_2SCFG1                           0x5011
 467#define HDMI_A_5SCFG0                           0x5012
 468#define HDMI_A_5SCFG1                           0x5013
 469#define HDMI_A_SRMVERLSB                        0x5014
 470#define HDMI_A_SRMVERMSB                        0x5015
 471#define HDMI_A_SRMCTRL                          0x5016
 472#define HDMI_A_SFRSETUP                         0x5017
 473#define HDMI_A_I2CHSETUP                        0x5018
 474#define HDMI_A_INTSETUP                         0x5019
 475#define HDMI_A_PRESETUP                         0x501A
 476#define HDMI_A_SRM_BASE                         0x5020
 477
 478/* I2C Master Registers (E-DDC) */
 479#define HDMI_I2CM_SLAVE                         0x7E00
 480#define HDMI_I2CM_ADDRESS                       0x7E01
 481#define HDMI_I2CM_DATAO                         0x7E02
 482#define HDMI_I2CM_DATAI                         0x7E03
 483#define HDMI_I2CM_OPERATION                     0x7E04
 484#define HDMI_I2CM_INT                           0x7E05
 485#define HDMI_I2CM_CTLINT                        0x7E06
 486#define HDMI_I2CM_DIV                           0x7E07
 487#define HDMI_I2CM_SEGADDR                       0x7E08
 488#define HDMI_I2CM_SOFTRSTZ                      0x7E09
 489#define HDMI_I2CM_SEGPTR                        0x7E0A
 490#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
 491#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
 492#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
 493#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
 494#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
 495#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
 496#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
 497#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
 498
 499enum {
 500/* PRODUCT_ID0 field values */
 501        HDMI_PRODUCT_ID0_HDMI_TX = 0xa0,
 502
 503/* PRODUCT_ID1 field values */
 504        HDMI_PRODUCT_ID1_HDCP = 0xc0,
 505        HDMI_PRODUCT_ID1_HDMI_RX = 0x02,
 506        HDMI_PRODUCT_ID1_HDMI_TX = 0x01,
 507
 508/* CONFIG0_ID field values */
 509        HDMI_CONFIG0_I2S = 0x10,
 510        HDMI_CONFIG0_CEC = 0x02,
 511
 512/* CONFIG1_ID field values */
 513        HDMI_CONFIG1_AHB = 0x01,
 514
 515/* CONFIG3_ID field values */
 516        HDMI_CONFIG3_AHBAUDDMA = 0x02,
 517        HDMI_CONFIG3_GPAUD = 0x01,
 518
 519/* IH_FC_INT2 field values */
 520        HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
 521        HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
 522        HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 523
 524/* IH_FC_STAT2 field values */
 525        HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
 526        HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 527        HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 528
 529/* IH_PHY_STAT0 field values */
 530        HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
 531        HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
 532        HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
 533        HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
 534        HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
 535        HDMI_IH_PHY_STAT0_HPD = 0x1,
 536
 537/* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */
 538        HDMI_IH_I2CM_STAT0_DONE = 0x2,
 539        HDMI_IH_I2CM_STAT0_ERROR = 0x1,
 540
 541/* IH_MUTE_I2CMPHY_STAT0 field values */
 542        HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
 543        HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
 544
 545/* IH_AHBDMAAUD_STAT0 field values */
 546        HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
 547        HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
 548        HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
 549        HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
 550        HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
 551        HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
 552
 553/* IH_MUTE_FC_STAT2 field values */
 554        HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
 555        HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 556        HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 557
 558/* IH_MUTE_AHBDMAAUD_STAT0 field values */
 559        HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
 560        HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
 561        HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
 562        HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
 563        HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
 564        HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
 565
 566/* IH_MUTE field values */
 567        HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
 568        HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
 569
 570/* TX_INVID0 field values */
 571        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
 572        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
 573        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
 574        HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
 575        HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
 576
 577/* TX_INSTUFFING field values */
 578        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
 579        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
 580        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
 581        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
 582        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
 583        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
 584        HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
 585        HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
 586        HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
 587
 588/* VP_PR_CD field values */
 589        HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
 590        HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
 591        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
 592        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
 593
 594/* VP_STUFF field values */
 595        HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
 596        HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
 597        HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
 598        HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
 599        HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
 600        HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
 601        HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
 602        HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
 603        HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
 604        HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
 605        HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
 606        HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
 607        HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
 608        HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
 609        HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
 610
 611/* VP_CONF field values */
 612        HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
 613        HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
 614        HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
 615        HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
 616        HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
 617        HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
 618        HDMI_VP_CONF_PR_EN_MASK = 0x10,
 619        HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
 620        HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
 621        HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
 622        HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
 623        HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
 624        HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
 625        HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
 626        HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
 627        HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
 628        HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
 629        HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
 630        HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
 631
 632/* VP_REMAP field values */
 633        HDMI_VP_REMAP_MASK = 0x3,
 634        HDMI_VP_REMAP_YCC422_24bit = 0x2,
 635        HDMI_VP_REMAP_YCC422_20bit = 0x1,
 636        HDMI_VP_REMAP_YCC422_16bit = 0x0,
 637
 638/* FC_INVIDCONF field values */
 639        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
 640        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
 641        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
 642        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
 643        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
 644        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 645        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
 646        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
 647        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 648        HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
 649        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
 650        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
 651        HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
 652        HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
 653        HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
 654        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
 655        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
 656        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
 657        HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
 658        HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
 659        HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
 660
 661/* FC_AUDICONF0 field values */
 662        HDMI_FC_AUDICONF0_CC_OFFSET = 4,
 663        HDMI_FC_AUDICONF0_CC_MASK = 0x70,
 664        HDMI_FC_AUDICONF0_CT_OFFSET = 0,
 665        HDMI_FC_AUDICONF0_CT_MASK = 0xF,
 666
 667/* FC_AUDICONF1 field values */
 668        HDMI_FC_AUDICONF1_SS_OFFSET = 3,
 669        HDMI_FC_AUDICONF1_SS_MASK = 0x18,
 670        HDMI_FC_AUDICONF1_SF_OFFSET = 0,
 671        HDMI_FC_AUDICONF1_SF_MASK = 0x7,
 672
 673/* FC_AUDICONF3 field values */
 674        HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
 675        HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
 676        HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
 677        HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
 678        HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
 679        HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
 680
 681/* FC_AUDSCHNLS0 field values */
 682        HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
 683        HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
 684        HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
 685        HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
 686
 687/* FC_AUDSCHNLS3-6 field values */
 688        HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
 689        HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
 690        HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
 691        HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
 692        HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
 693        HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
 694        HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
 695        HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
 696
 697        HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
 698        HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
 699        HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
 700        HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
 701        HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
 702        HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
 703        HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
 704        HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
 705
 706/* HDMI_FC_AUDSCHNLS7 field values */
 707        HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
 708        HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
 709
 710/* HDMI_FC_AUDSCHNLS8 field values */
 711        HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
 712        HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
 713        HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
 714        HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
 715
 716/* FC_AUDSCONF field values */
 717        HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
 718        HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
 719        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
 720        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
 721        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
 722        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
 723
 724/* FC_STAT2 field values */
 725        HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
 726        HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 727        HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 728
 729/* FC_INT2 field values */
 730        HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
 731        HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
 732        HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 733
 734/* FC_MASK2 field values */
 735        HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
 736        HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
 737        HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
 738
 739/* FC_PRCONF field values */
 740        HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
 741        HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
 742        HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
 743        HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
 744
 745/* FC_AVICONF0-FC_AVICONF3 field values */
 746        HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
 747        HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
 748        HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
 749        HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
 750        HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
 751        HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
 752        HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
 753        HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
 754        HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
 755        HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
 756        HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
 757        HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
 758        HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
 759        HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
 760        HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
 761        HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
 762
 763        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
 764        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
 765        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
 766        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
 767        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
 768        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
 769        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
 770        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
 771        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
 772        HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
 773        HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
 774        HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
 775        HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
 776        HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
 777
 778        HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
 779        HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
 780        HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
 781        HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
 782        HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
 783        HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
 784        HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
 785        HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
 786        HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
 787        HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
 788        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
 789        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
 790        HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
 791        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
 792        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
 793        HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
 794        HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
 795        HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
 796
 797        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
 798        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
 799        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
 800        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
 801        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
 802        HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
 803        HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
 804        HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
 805
 806/* FC_DBGFORCE field values */
 807        HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
 808        HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
 809
 810/* FC_DATAUTO0 field values */
 811        HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
 812        HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
 813
 814/* PHY_CONF0 field values */
 815        HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 816        HDMI_PHY_CONF0_PDZ_OFFSET = 7,
 817        HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
 818        HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
 819        HDMI_PHY_CONF0_SVSRET_MASK = 0x20,
 820        HDMI_PHY_CONF0_SVSRET_OFFSET = 5,
 821        HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
 822        HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
 823        HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
 824        HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
 825        HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
 826        HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
 827        HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
 828        HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
 829        HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
 830        HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
 831
 832/* PHY_TST0 field values */
 833        HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
 834        HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
 835        HDMI_PHY_TST0_TSTEN_MASK = 0x10,
 836        HDMI_PHY_TST0_TSTEN_OFFSET = 4,
 837        HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
 838        HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
 839
 840/* PHY_STAT0 field values */
 841        HDMI_PHY_RX_SENSE3 = 0x80,
 842        HDMI_PHY_RX_SENSE2 = 0x40,
 843        HDMI_PHY_RX_SENSE1 = 0x20,
 844        HDMI_PHY_RX_SENSE0 = 0x10,
 845        HDMI_PHY_HPD = 0x02,
 846        HDMI_PHY_TX_PHY_LOCK = 0x01,
 847
 848/* PHY_I2CM_SLAVE_ADDR field values */
 849        HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
 850        HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
 851
 852/* PHY_I2CM_OPERATION_ADDR field values */
 853        HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
 854        HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
 855
 856/* HDMI_PHY_I2CM_INT_ADDR */
 857        HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
 858        HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
 859
 860/* HDMI_PHY_I2CM_CTLINT_ADDR */
 861        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
 862        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
 863        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
 864        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
 865
 866/* AUD_CONF0 field values */
 867        HDMI_AUD_CONF0_SW_RESET = 0x80,
 868        HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F,
 869
 870/* AUD_CONF1 field values */
 871        HDMI_AUD_CONF1_MODE_I2S = 0x00,
 872        HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02,
 873        HDMI_AUD_CONF1_MODE_LEFT_J = 0x04,
 874        HDMI_AUD_CONF1_WIDTH_16 = 0x10,
 875        HDMI_AUD_CONF1_WIDTH_24 = 0x18,
 876
 877/* AUD_CTS3 field values */
 878        HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
 879        HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
 880        HDMI_AUD_CTS3_N_SHIFT_1 = 0,
 881        HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
 882        HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
 883        HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
 884        HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
 885        HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
 886        /* note that the CTS3 MANUAL bit has been removed
 887           from our part. Can't set it, will read as 0. */
 888        HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
 889        HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
 890
 891/* HDMI_AUD_INPUTCLKFS field values */
 892        HDMI_AUD_INPUTCLKFS_128FS = 0,
 893        HDMI_AUD_INPUTCLKFS_256FS = 1,
 894        HDMI_AUD_INPUTCLKFS_512FS = 2,
 895        HDMI_AUD_INPUTCLKFS_64FS = 4,
 896
 897/* AHB_DMA_CONF0 field values */
 898        HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
 899        HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
 900        HDMI_AHB_DMA_CONF0_HBR = 0x10,
 901        HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
 902        HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
 903        HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
 904        HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
 905        HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
 906        HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
 907        HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
 908        HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
 909
 910/* HDMI_AHB_DMA_START field values */
 911        HDMI_AHB_DMA_START_START_OFFSET = 0,
 912        HDMI_AHB_DMA_START_START_MASK = 0x01,
 913
 914/* HDMI_AHB_DMA_STOP field values */
 915        HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
 916        HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
 917
 918/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
 919        HDMI_AHB_DMA_DONE = 0x80,
 920        HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
 921        HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
 922        HDMI_AHB_DMA_ERROR = 0x10,
 923        HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
 924        HDMI_AHB_DMA_FIFO_FULL = 0x02,
 925        HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
 926
 927/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
 928        HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
 929        HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
 930
 931/* MC_CLKDIS field values */
 932        HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
 933        HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
 934        HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
 935        HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
 936        HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
 937        HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
 938        HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
 939
 940/* MC_SWRSTZ field values */
 941        HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
 942
 943/* MC_FLOWCTRL field values */
 944        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
 945        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
 946        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
 947
 948/* MC_PHYRSTZ field values */
 949        HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01,
 950
 951/* MC_HEACPHY_RST field values */
 952        HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
 953        HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
 954
 955/* CSC_CFG field values */
 956        HDMI_CSC_CFG_INTMODE_MASK = 0x30,
 957        HDMI_CSC_CFG_INTMODE_OFFSET = 4,
 958        HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
 959        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
 960        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
 961        HDMI_CSC_CFG_DECMODE_MASK = 0x3,
 962        HDMI_CSC_CFG_DECMODE_OFFSET = 0,
 963        HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
 964        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
 965        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
 966        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
 967
 968/* CSC_SCALE field values */
 969        HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
 970        HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
 971        HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
 972        HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
 973        HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
 974        HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
 975
 976/* A_HDCPCFG0 field values */
 977        HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
 978        HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
 979        HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
 980        HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
 981        HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
 982        HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
 983        HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
 984        HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
 985        HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
 986        HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
 987        HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
 988        HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
 989        HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
 990        HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
 991        HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
 992        HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
 993        HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
 994        HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
 995        HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
 996        HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
 997        HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
 998        HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
 999        HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1000        HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1001
1002/* A_HDCPCFG1 field values */
1003        HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1004        HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1005        HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1006        HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1007        HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1008        HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1009        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1010        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1011        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1012        HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1013        HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1014
1015/* A_VIDPOLCFG field values */
1016        HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1017        HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1018        HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1019        HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1020        HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1021        HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1022        HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1023        HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1024        HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1025        HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1026        HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1027
1028/* I2CM_OPERATION field values */
1029        HDMI_I2CM_OPERATION_WRITE = 0x10,
1030        HDMI_I2CM_OPERATION_READ_EXT = 0x2,
1031        HDMI_I2CM_OPERATION_READ = 0x1,
1032
1033/* I2CM_INT field values */
1034        HDMI_I2CM_INT_DONE_POL = 0x8,
1035        HDMI_I2CM_INT_DONE_MASK = 0x4,
1036
1037/* I2CM_CTLINT field values */
1038        HDMI_I2CM_CTLINT_NAC_POL = 0x80,
1039        HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
1040        HDMI_I2CM_CTLINT_ARB_POL = 0x8,
1041        HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
1042};
1043
1044/*
1045 * HDMI 3D TX PHY registers
1046 */
1047#define HDMI_3D_TX_PHY_PWRCTRL                  0x00
1048#define HDMI_3D_TX_PHY_SERDIVCTRL               0x01
1049#define HDMI_3D_TX_PHY_SERCKCTRL                0x02
1050#define HDMI_3D_TX_PHY_SERCKKILLCTRL            0x03
1051#define HDMI_3D_TX_PHY_TXRESCTRL                0x04
1052#define HDMI_3D_TX_PHY_CKCALCTRL                0x05
1053#define HDMI_3D_TX_PHY_CPCE_CTRL                0x06
1054#define HDMI_3D_TX_PHY_TXCLKMEASCTRL            0x07
1055#define HDMI_3D_TX_PHY_TXMEASCTRL               0x08
1056#define HDMI_3D_TX_PHY_CKSYMTXCTRL              0x09
1057#define HDMI_3D_TX_PHY_CMPSEQCTRL               0x0a
1058#define HDMI_3D_TX_PHY_CMPPWRCTRL               0x0b
1059#define HDMI_3D_TX_PHY_CMPMODECTRL              0x0c
1060#define HDMI_3D_TX_PHY_MEASCTRL                 0x0d
1061#define HDMI_3D_TX_PHY_VLEVCTRL                 0x0e
1062#define HDMI_3D_TX_PHY_D2ACTRL                  0x0f
1063#define HDMI_3D_TX_PHY_CURRCTRL                 0x10
1064#define HDMI_3D_TX_PHY_DRVANACTRL               0x11
1065#define HDMI_3D_TX_PHY_PLLMEASCTRL              0x12
1066#define HDMI_3D_TX_PHY_PLLPHBYCTRL              0x13
1067#define HDMI_3D_TX_PHY_GRP_CTRL                 0x14
1068#define HDMI_3D_TX_PHY_GMPCTRL                  0x15
1069#define HDMI_3D_TX_PHY_MPLLMEASCTRL             0x16
1070#define HDMI_3D_TX_PHY_MSM_CTRL                 0x17
1071#define HDMI_3D_TX_PHY_SCRPB_STATUS             0x18
1072#define HDMI_3D_TX_PHY_TXTERM                   0x19
1073#define HDMI_3D_TX_PHY_PTRPT_ENBL               0x1a
1074#define HDMI_3D_TX_PHY_PATTERNGEN               0x1b
1075#define HDMI_3D_TX_PHY_SDCAP_MODE               0x1c
1076#define HDMI_3D_TX_PHY_SCOPEMODE                0x1d
1077#define HDMI_3D_TX_PHY_DIGTXMODE                0x1e
1078#define HDMI_3D_TX_PHY_STR_STATUS               0x1f
1079#define HDMI_3D_TX_PHY_SCOPECNT0                0x20
1080#define HDMI_3D_TX_PHY_SCOPECNT1                0x21
1081#define HDMI_3D_TX_PHY_SCOPECNT2                0x22
1082#define HDMI_3D_TX_PHY_SCOPECNTCLK              0x23
1083#define HDMI_3D_TX_PHY_SCOPESAMPLE              0x24
1084#define HDMI_3D_TX_PHY_SCOPECNTMSB01            0x25
1085#define HDMI_3D_TX_PHY_SCOPECNTMSB2CK           0x26
1086
1087/* HDMI_3D_TX_PHY_CKCALCTRL values */
1088#define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE               BIT(15)
1089
1090/* HDMI_3D_TX_PHY_MSM_CTRL values */
1091#define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK          BIT(13)
1092#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL    (0 << 1)
1093#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF             (1 << 1)
1094#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK            (2 << 1)
1095#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK          (3 << 1)
1096#define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL            BIT(0)
1097
1098/* HDMI_3D_TX_PHY_PTRPT_ENBL values */
1099#define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE              BIT(15)
1100#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2          BIT(8)
1101#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1          BIT(7)
1102#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0          BIT(6)
1103#define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB            BIT(5)
1104#define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB              BIT(4)
1105#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB      BIT(3)
1106#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY              BIT(2)
1107#define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB          BIT(1)
1108#define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB            BIT(0)
1109
1110#endif /* __DW_HDMI_H__ */
1111