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23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/i2c.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/sched.h>
30#include <linux/seq_file.h>
31
32#include <drm/drm_dp_helper.h>
33#include <drm/drm_print.h>
34#include <drm/drm_vblank.h>
35
36#include "drm_crtc_helper_internal.h"
37
38
39
40
41
42
43
44
45
46
47
48static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
49{
50 return link_status[r - DP_LANE0_1_STATUS];
51}
52
53static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
54 int lane)
55{
56 int i = DP_LANE0_1_STATUS + (lane >> 1);
57 int s = (lane & 1) * 4;
58 u8 l = dp_link_status(link_status, i);
59 return (l >> s) & 0xf;
60}
61
62bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
63 int lane_count)
64{
65 u8 lane_align;
66 u8 lane_status;
67 int lane;
68
69 lane_align = dp_link_status(link_status,
70 DP_LANE_ALIGN_STATUS_UPDATED);
71 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
72 return false;
73 for (lane = 0; lane < lane_count; lane++) {
74 lane_status = dp_get_lane_status(link_status, lane);
75 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
76 return false;
77 }
78 return true;
79}
80EXPORT_SYMBOL(drm_dp_channel_eq_ok);
81
82bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
83 int lane_count)
84{
85 int lane;
86 u8 lane_status;
87
88 for (lane = 0; lane < lane_count; lane++) {
89 lane_status = dp_get_lane_status(link_status, lane);
90 if ((lane_status & DP_LANE_CR_DONE) == 0)
91 return false;
92 }
93 return true;
94}
95EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
96
97u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
98 int lane)
99{
100 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
101 int s = ((lane & 1) ?
102 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
103 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
104 u8 l = dp_link_status(link_status, i);
105
106 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
107}
108EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
109
110u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
111 int lane)
112{
113 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
114 int s = ((lane & 1) ?
115 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
116 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
117 u8 l = dp_link_status(link_status, i);
118
119 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
120}
121EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
122
123void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
124 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
125 DP_TRAINING_AUX_RD_MASK;
126
127 if (rd_interval > 4)
128 DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
129 rd_interval);
130
131 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
132 udelay(100);
133 else
134 mdelay(rd_interval * 4);
135}
136EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
137
138void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
139 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
140 DP_TRAINING_AUX_RD_MASK;
141
142 if (rd_interval > 4)
143 DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
144 rd_interval);
145
146 if (rd_interval == 0)
147 udelay(400);
148 else
149 mdelay(rd_interval * 4);
150}
151EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
152
153u8 drm_dp_link_rate_to_bw_code(int link_rate)
154{
155 switch (link_rate) {
156 default:
157 WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
158 DP_LINK_BW_1_62);
159
160 case 162000:
161 return DP_LINK_BW_1_62;
162 case 270000:
163 return DP_LINK_BW_2_7;
164 case 540000:
165 return DP_LINK_BW_5_4;
166 case 810000:
167 return DP_LINK_BW_8_1;
168 }
169}
170EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
171
172int drm_dp_bw_code_to_link_rate(u8 link_bw)
173{
174 switch (link_bw) {
175 default:
176 WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
177
178 case DP_LINK_BW_1_62:
179 return 162000;
180 case DP_LINK_BW_2_7:
181 return 270000;
182 case DP_LINK_BW_5_4:
183 return 540000;
184 case DP_LINK_BW_8_1:
185 return 810000;
186 }
187}
188EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
189
190#define AUX_RETRY_INTERVAL 500
191
192static inline void
193drm_dp_dump_access(const struct drm_dp_aux *aux,
194 u8 request, uint offset, void *buffer, int ret)
195{
196 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
197
198 if (ret > 0)
199 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
200 aux->name, offset, arrow, ret, min(ret, 20), buffer);
201 else
202 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
203 aux->name, offset, arrow, ret);
204}
205
206
207
208
209
210
211
212
213
214
215
216
217
218static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
219 unsigned int offset, void *buffer, size_t size)
220{
221 struct drm_dp_aux_msg msg;
222 unsigned int retry, native_reply;
223 int err = 0, ret = 0;
224
225 memset(&msg, 0, sizeof(msg));
226 msg.address = offset;
227 msg.request = request;
228 msg.buffer = buffer;
229 msg.size = size;
230
231 mutex_lock(&aux->hw_mutex);
232
233
234
235
236
237
238
239 for (retry = 0; retry < 32; retry++) {
240 if (ret != 0 && ret != -ETIMEDOUT) {
241 usleep_range(AUX_RETRY_INTERVAL,
242 AUX_RETRY_INTERVAL + 100);
243 }
244
245 ret = aux->transfer(aux, &msg);
246
247 if (ret >= 0) {
248 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
249 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
250 if (ret == size)
251 goto unlock;
252
253 ret = -EPROTO;
254 } else
255 ret = -EIO;
256 }
257
258
259
260
261
262
263 if (!err)
264 err = ret;
265 }
266
267 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
268 ret = err;
269
270unlock:
271 mutex_unlock(&aux->hw_mutex);
272 return ret;
273}
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
290 void *buffer, size_t size)
291{
292 int ret;
293
294
295
296
297
298
299
300
301
302
303
304
305
306 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
307 1);
308 if (ret != 1)
309 goto out;
310
311 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
312 size);
313
314out:
315 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
316 return ret;
317}
318EXPORT_SYMBOL(drm_dp_dpcd_read);
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
335 void *buffer, size_t size)
336{
337 int ret;
338
339 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
340 size);
341 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
342 return ret;
343}
344EXPORT_SYMBOL(drm_dp_dpcd_write);
345
346
347
348
349
350
351
352
353
354int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
355 u8 status[DP_LINK_STATUS_SIZE])
356{
357 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
358 DP_LINK_STATUS_SIZE);
359}
360EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
361
362
363
364
365
366
367
368
369
370
371
372
373int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
374{
375 u8 values[3];
376 int err;
377
378 memset(link, 0, sizeof(*link));
379
380 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
381 if (err < 0)
382 return err;
383
384 link->revision = values[0];
385 link->rate = drm_dp_bw_code_to_link_rate(values[1]);
386 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
387
388 if (values[2] & DP_ENHANCED_FRAME_CAP)
389 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
390
391 return 0;
392}
393EXPORT_SYMBOL(drm_dp_link_probe);
394
395
396
397
398
399
400
401
402int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
403{
404 u8 value;
405 int err;
406
407
408 if (link->revision < 0x11)
409 return 0;
410
411 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
412 if (err < 0)
413 return err;
414
415 value &= ~DP_SET_POWER_MASK;
416 value |= DP_SET_POWER_D0;
417
418 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
419 if (err < 0)
420 return err;
421
422
423
424
425
426
427 usleep_range(1000, 2000);
428
429 return 0;
430}
431EXPORT_SYMBOL(drm_dp_link_power_up);
432
433
434
435
436
437
438
439
440int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
441{
442 u8 value;
443 int err;
444
445
446 if (link->revision < 0x11)
447 return 0;
448
449 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
450 if (err < 0)
451 return err;
452
453 value &= ~DP_SET_POWER_MASK;
454 value |= DP_SET_POWER_D3;
455
456 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
457 if (err < 0)
458 return err;
459
460 return 0;
461}
462EXPORT_SYMBOL(drm_dp_link_power_down);
463
464
465
466
467
468
469
470
471int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
472{
473 u8 values[2];
474 int err;
475
476 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
477 values[1] = link->num_lanes;
478
479 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
480 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
481
482 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
483 if (err < 0)
484 return err;
485
486 return 0;
487}
488EXPORT_SYMBOL(drm_dp_link_configure);
489
490
491
492
493
494
495
496
497
498
499
500int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
501 const u8 port_cap[4])
502{
503 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
504 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
505 DP_DETAILED_CAP_INFO_AVAILABLE;
506
507 if (!detailed_cap_info)
508 return 0;
509
510 switch (type) {
511 case DP_DS_PORT_TYPE_VGA:
512 return port_cap[1] * 8 * 1000;
513 case DP_DS_PORT_TYPE_DVI:
514 case DP_DS_PORT_TYPE_HDMI:
515 case DP_DS_PORT_TYPE_DP_DUALMODE:
516 return port_cap[1] * 2500;
517 default:
518 return 0;
519 }
520}
521EXPORT_SYMBOL(drm_dp_downstream_max_clock);
522
523
524
525
526
527
528
529
530
531int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
532 const u8 port_cap[4])
533{
534 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
535 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
536 DP_DETAILED_CAP_INFO_AVAILABLE;
537 int bpc;
538
539 if (!detailed_cap_info)
540 return 0;
541
542 switch (type) {
543 case DP_DS_PORT_TYPE_VGA:
544 case DP_DS_PORT_TYPE_DVI:
545 case DP_DS_PORT_TYPE_HDMI:
546 case DP_DS_PORT_TYPE_DP_DUALMODE:
547 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
548
549 switch (bpc) {
550 case DP_DS_8BPC:
551 return 8;
552 case DP_DS_10BPC:
553 return 10;
554 case DP_DS_12BPC:
555 return 12;
556 case DP_DS_16BPC:
557 return 16;
558 }
559
560 default:
561 return 0;
562 }
563}
564EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
565
566
567
568
569
570
571
572
573int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
574{
575 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
576}
577EXPORT_SYMBOL(drm_dp_downstream_id);
578
579
580
581
582
583
584
585
586
587void drm_dp_downstream_debug(struct seq_file *m,
588 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
589 const u8 port_cap[4], struct drm_dp_aux *aux)
590{
591 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
592 DP_DETAILED_CAP_INFO_AVAILABLE;
593 int clk;
594 int bpc;
595 char id[7];
596 int len;
597 uint8_t rev[2];
598 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
599 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
600 DP_DWN_STRM_PORT_PRESENT;
601
602 seq_printf(m, "\tDP branch device present: %s\n",
603 branch_device ? "yes" : "no");
604
605 if (!branch_device)
606 return;
607
608 switch (type) {
609 case DP_DS_PORT_TYPE_DP:
610 seq_puts(m, "\t\tType: DisplayPort\n");
611 break;
612 case DP_DS_PORT_TYPE_VGA:
613 seq_puts(m, "\t\tType: VGA\n");
614 break;
615 case DP_DS_PORT_TYPE_DVI:
616 seq_puts(m, "\t\tType: DVI\n");
617 break;
618 case DP_DS_PORT_TYPE_HDMI:
619 seq_puts(m, "\t\tType: HDMI\n");
620 break;
621 case DP_DS_PORT_TYPE_NON_EDID:
622 seq_puts(m, "\t\tType: others without EDID support\n");
623 break;
624 case DP_DS_PORT_TYPE_DP_DUALMODE:
625 seq_puts(m, "\t\tType: DP++\n");
626 break;
627 case DP_DS_PORT_TYPE_WIRELESS:
628 seq_puts(m, "\t\tType: Wireless\n");
629 break;
630 default:
631 seq_puts(m, "\t\tType: N/A\n");
632 }
633
634 memset(id, 0, sizeof(id));
635 drm_dp_downstream_id(aux, id);
636 seq_printf(m, "\t\tID: %s\n", id);
637
638 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
639 if (len > 0)
640 seq_printf(m, "\t\tHW: %d.%d\n",
641 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
642
643 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
644 if (len > 0)
645 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
646
647 if (detailed_cap_info) {
648 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
649
650 if (clk > 0) {
651 if (type == DP_DS_PORT_TYPE_VGA)
652 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
653 else
654 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
655 }
656
657 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
658
659 if (bpc > 0)
660 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
661 }
662}
663EXPORT_SYMBOL(drm_dp_downstream_debug);
664
665
666
667
668
669static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
670{
671 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
672 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
673 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
674 I2C_FUNC_10BIT_ADDR;
675}
676
677static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
678{
679
680
681
682
683
684 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
685 msg->request &= DP_AUX_I2C_MOT;
686 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
687 }
688}
689
690#define AUX_PRECHARGE_LEN 10
691#define AUX_SYNC_LEN (16 + 4)
692#define AUX_STOP_LEN 4
693#define AUX_CMD_LEN 4
694#define AUX_ADDRESS_LEN 20
695#define AUX_REPLY_PAD_LEN 4
696#define AUX_LENGTH_LEN 8
697
698
699
700
701
702static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
703{
704 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
705 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
706
707 if ((msg->request & DP_AUX_I2C_READ) == 0)
708 len += msg->size * 8;
709
710 return len;
711}
712
713static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
714{
715 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
716 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
717
718
719
720
721
722 if (msg->request & DP_AUX_I2C_READ)
723 len += msg->size * 8;
724
725 return len;
726}
727
728#define I2C_START_LEN 1
729#define I2C_STOP_LEN 1
730#define I2C_ADDR_LEN 9
731#define I2C_DATA_LEN 9
732
733
734
735
736
737
738
739
740
741static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
742 int i2c_speed_khz)
743{
744
745 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
746 msg->size * I2C_DATA_LEN +
747 I2C_STOP_LEN) * 1000, i2c_speed_khz);
748}
749
750
751
752
753
754
755static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
756 int i2c_speed_khz)
757{
758 int aux_time_us = drm_dp_aux_req_duration(msg) +
759 drm_dp_aux_reply_duration(msg);
760 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
761
762 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
763}
764
765
766
767
768
769static int dp_aux_i2c_speed_khz __read_mostly = 10;
770module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
771MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
772 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
773
774
775
776
777
778
779
780
781
782static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
783{
784 unsigned int retry, defer_i2c;
785 int ret;
786
787
788
789
790
791
792
793 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
794
795 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
796 ret = aux->transfer(aux, msg);
797 if (ret < 0) {
798 if (ret == -EBUSY)
799 continue;
800
801
802
803
804
805
806
807 if (ret == -ETIMEDOUT)
808 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
809 else
810 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
811
812 return ret;
813 }
814
815
816 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
817 case DP_AUX_NATIVE_REPLY_ACK:
818
819
820
821
822 break;
823
824 case DP_AUX_NATIVE_REPLY_NACK:
825 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
826 return -EREMOTEIO;
827
828 case DP_AUX_NATIVE_REPLY_DEFER:
829 DRM_DEBUG_KMS("native defer\n");
830
831
832
833
834
835
836
837
838
839 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
840 continue;
841
842 default:
843 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
844 return -EREMOTEIO;
845 }
846
847 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
848 case DP_AUX_I2C_REPLY_ACK:
849
850
851
852
853 if (ret != msg->size)
854 drm_dp_i2c_msg_write_status_update(msg);
855 return ret;
856
857 case DP_AUX_I2C_REPLY_NACK:
858 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
859 ret, msg->size);
860 aux->i2c_nack_count++;
861 return -EREMOTEIO;
862
863 case DP_AUX_I2C_REPLY_DEFER:
864 DRM_DEBUG_KMS("I2C defer\n");
865
866
867
868
869 aux->i2c_defer_count++;
870 if (defer_i2c < 7)
871 defer_i2c++;
872 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
873 drm_dp_i2c_msg_write_status_update(msg);
874
875 continue;
876
877 default:
878 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
879 return -EREMOTEIO;
880 }
881 }
882
883 DRM_DEBUG_KMS("too many retries, giving up\n");
884 return -EREMOTEIO;
885}
886
887static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
888 const struct i2c_msg *i2c_msg)
889{
890 msg->request = (i2c_msg->flags & I2C_M_RD) ?
891 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
892 if (!(i2c_msg->flags & I2C_M_STOP))
893 msg->request |= DP_AUX_I2C_MOT;
894}
895
896
897
898
899
900
901static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
902{
903 int err, ret = orig_msg->size;
904 struct drm_dp_aux_msg msg = *orig_msg;
905
906 while (msg.size > 0) {
907 err = drm_dp_i2c_do_msg(aux, &msg);
908 if (err <= 0)
909 return err == 0 ? -EPROTO : err;
910
911 if (err < msg.size && err < ret) {
912 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
913 msg.size, err);
914 ret = err;
915 }
916
917 msg.size -= err;
918 msg.buffer += err;
919 }
920
921 return ret;
922}
923
924
925
926
927
928
929static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
930module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
931MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
932 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
933
934static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
935 int num)
936{
937 struct drm_dp_aux *aux = adapter->algo_data;
938 unsigned int i, j;
939 unsigned transfer_size;
940 struct drm_dp_aux_msg msg;
941 int err = 0;
942
943 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
944
945 memset(&msg, 0, sizeof(msg));
946
947 for (i = 0; i < num; i++) {
948 msg.address = msgs[i].addr;
949 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
950
951
952
953
954 msg.buffer = NULL;
955 msg.size = 0;
956 err = drm_dp_i2c_do_msg(aux, &msg);
957
958
959
960
961
962 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
963
964 if (err < 0)
965 break;
966
967
968
969
970 transfer_size = dp_aux_i2c_transfer_size;
971 for (j = 0; j < msgs[i].len; j += msg.size) {
972 msg.buffer = msgs[i].buf + j;
973 msg.size = min(transfer_size, msgs[i].len - j);
974
975 err = drm_dp_i2c_drain_msg(aux, &msg);
976
977
978
979
980
981 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
982
983 if (err < 0)
984 break;
985 transfer_size = err;
986 }
987 if (err < 0)
988 break;
989 }
990 if (err >= 0)
991 err = num;
992
993
994
995
996 msg.request &= ~DP_AUX_I2C_MOT;
997 msg.buffer = NULL;
998 msg.size = 0;
999 (void)drm_dp_i2c_do_msg(aux, &msg);
1000
1001 return err;
1002}
1003
1004static const struct i2c_algorithm drm_dp_i2c_algo = {
1005 .functionality = drm_dp_i2c_functionality,
1006 .master_xfer = drm_dp_i2c_xfer,
1007};
1008
1009static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1010{
1011 return container_of(i2c, struct drm_dp_aux, ddc);
1012}
1013
1014static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1015{
1016 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1017}
1018
1019static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1020{
1021 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1022}
1023
1024static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1025{
1026 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1027}
1028
1029static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1030 .lock_bus = lock_bus,
1031 .trylock_bus = trylock_bus,
1032 .unlock_bus = unlock_bus,
1033};
1034
1035static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1036{
1037 u8 buf, count;
1038 int ret;
1039
1040 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1041 if (ret < 0)
1042 return ret;
1043
1044 WARN_ON(!(buf & DP_TEST_SINK_START));
1045
1046 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1047 if (ret < 0)
1048 return ret;
1049
1050 count = buf & DP_TEST_COUNT_MASK;
1051 if (count == aux->crc_count)
1052 return -EAGAIN;
1053
1054 aux->crc_count = count;
1055
1056
1057
1058
1059
1060 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1061 if (ret < 0)
1062 return ret;
1063
1064 return 0;
1065}
1066
1067static void drm_dp_aux_crc_work(struct work_struct *work)
1068{
1069 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1070 crc_work);
1071 struct drm_crtc *crtc;
1072 u8 crc_bytes[6];
1073 uint32_t crcs[3];
1074 int ret;
1075
1076 if (WARN_ON(!aux->crtc))
1077 return;
1078
1079 crtc = aux->crtc;
1080 while (crtc->crc.opened) {
1081 drm_crtc_wait_one_vblank(crtc);
1082 if (!crtc->crc.opened)
1083 break;
1084
1085 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1086 if (ret == -EAGAIN) {
1087 usleep_range(1000, 2000);
1088 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1089 }
1090
1091 if (ret == -EAGAIN) {
1092 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1093 ret);
1094 continue;
1095 } else if (ret) {
1096 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1097 continue;
1098 }
1099
1100 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1101 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1102 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1103 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1104 }
1105}
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116void drm_dp_aux_init(struct drm_dp_aux *aux)
1117{
1118 mutex_init(&aux->hw_mutex);
1119 mutex_init(&aux->cec.lock);
1120 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1121
1122 aux->ddc.algo = &drm_dp_i2c_algo;
1123 aux->ddc.algo_data = aux;
1124 aux->ddc.retries = 3;
1125
1126 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1127}
1128EXPORT_SYMBOL(drm_dp_aux_init);
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138int drm_dp_aux_register(struct drm_dp_aux *aux)
1139{
1140 int ret;
1141
1142 if (!aux->ddc.algo)
1143 drm_dp_aux_init(aux);
1144
1145 aux->ddc.class = I2C_CLASS_DDC;
1146 aux->ddc.owner = THIS_MODULE;
1147 aux->ddc.dev.parent = aux->dev;
1148
1149 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1150 sizeof(aux->ddc.name));
1151
1152 ret = drm_dp_aux_register_devnode(aux);
1153 if (ret)
1154 return ret;
1155
1156 ret = i2c_add_adapter(&aux->ddc);
1157 if (ret) {
1158 drm_dp_aux_unregister_devnode(aux);
1159 return ret;
1160 }
1161
1162 return 0;
1163}
1164EXPORT_SYMBOL(drm_dp_aux_register);
1165
1166
1167
1168
1169
1170void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1171{
1172 drm_dp_aux_unregister_devnode(aux);
1173 i2c_del_adapter(&aux->ddc);
1174}
1175EXPORT_SYMBOL(drm_dp_aux_unregister);
1176
1177#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1188{
1189 static const u16 psr_setup_time_us[] = {
1190 PSR_SETUP_TIME(330),
1191 PSR_SETUP_TIME(275),
1192 PSR_SETUP_TIME(220),
1193 PSR_SETUP_TIME(165),
1194 PSR_SETUP_TIME(110),
1195 PSR_SETUP_TIME(55),
1196 PSR_SETUP_TIME(0),
1197 };
1198 int i;
1199
1200 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1201 if (i >= ARRAY_SIZE(psr_setup_time_us))
1202 return -EINVAL;
1203
1204 return psr_setup_time_us[i];
1205}
1206EXPORT_SYMBOL(drm_dp_psr_setup_time);
1207
1208#undef PSR_SETUP_TIME
1209
1210
1211
1212
1213
1214
1215
1216
1217int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1218{
1219 u8 buf;
1220 int ret;
1221
1222 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1223 if (ret < 0)
1224 return ret;
1225
1226 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1227 if (ret < 0)
1228 return ret;
1229
1230 aux->crc_count = 0;
1231 aux->crtc = crtc;
1232 schedule_work(&aux->crc_work);
1233
1234 return 0;
1235}
1236EXPORT_SYMBOL(drm_dp_start_crc);
1237
1238
1239
1240
1241
1242
1243
1244int drm_dp_stop_crc(struct drm_dp_aux *aux)
1245{
1246 u8 buf;
1247 int ret;
1248
1249 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1250 if (ret < 0)
1251 return ret;
1252
1253 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1254 if (ret < 0)
1255 return ret;
1256
1257 flush_work(&aux->crc_work);
1258 aux->crtc = NULL;
1259
1260 return 0;
1261}
1262EXPORT_SYMBOL(drm_dp_stop_crc);
1263
1264struct dpcd_quirk {
1265 u8 oui[3];
1266 u8 device_id[6];
1267 bool is_branch;
1268 u32 quirks;
1269};
1270
1271#define OUI(first, second, third) { (first), (second), (third) }
1272#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1273 { (first), (second), (third), (fourth), (fifth), (sixth) }
1274
1275#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1276
1277static const struct dpcd_quirk dpcd_quirk_list[] = {
1278
1279 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1280
1281 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1282
1283 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1284
1285 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1286};
1287
1288#undef OUI
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298static u32
1299drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1300{
1301 const struct dpcd_quirk *quirk;
1302 u32 quirks = 0;
1303 int i;
1304 u8 any_device[] = DEVICE_ID_ANY;
1305
1306 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1307 quirk = &dpcd_quirk_list[i];
1308
1309 if (quirk->is_branch != is_branch)
1310 continue;
1311
1312 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1313 continue;
1314
1315 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1316 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1317 continue;
1318
1319 quirks |= quirk->quirks;
1320 }
1321
1322 return quirks;
1323}
1324
1325#undef DEVICE_ID_ANY
1326#undef DEVICE_ID
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1340 bool is_branch)
1341{
1342 struct drm_dp_dpcd_ident *ident = &desc->ident;
1343 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1344 int ret, dev_id_len;
1345
1346 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1347 if (ret < 0)
1348 return ret;
1349
1350 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1351
1352 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1353
1354 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1355 is_branch ? "branch" : "sink",
1356 (int)sizeof(ident->oui), ident->oui,
1357 dev_id_len, ident->device_id,
1358 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1359 ident->sw_major_rev, ident->sw_minor_rev,
1360 desc->quirks);
1361
1362 return 0;
1363}
1364EXPORT_SYMBOL(drm_dp_read_desc);
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1383 bool is_edp)
1384{
1385 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
1386
1387 if (is_edp) {
1388
1389 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1390 return 4;
1391 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1392 return 2;
1393 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1394 return 1;
1395 } else {
1396
1397 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
1398
1399 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
1400 return 24;
1401 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
1402 return 20;
1403 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
1404 return 16;
1405 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
1406 return 12;
1407 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
1408 return 10;
1409 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
1410 return 8;
1411 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
1412 return 6;
1413 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1414 return 4;
1415 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1416 return 2;
1417 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1418 return 1;
1419 }
1420
1421 return 0;
1422}
1423EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1441{
1442 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
1443
1444 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
1445 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
1446 return 9;
1447 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
1448 return 10;
1449 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
1450 return 11;
1451 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
1452 return 12;
1453 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
1454 return 13;
1455 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
1456 return 14;
1457 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
1458 return 15;
1459 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
1460 return 16;
1461 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
1462 return 8;
1463 }
1464
1465 return 0;
1466}
1467EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1487 u8 dsc_bpc[3])
1488{
1489 int num_bpc = 0;
1490 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
1491
1492 if (color_depth & DP_DSC_12_BPC)
1493 dsc_bpc[num_bpc++] = 12;
1494 if (color_depth & DP_DSC_10_BPC)
1495 dsc_bpc[num_bpc++] = 10;
1496 if (color_depth & DP_DSC_8_BPC)
1497 dsc_bpc[num_bpc++] = 8;
1498
1499 return num_bpc;
1500}
1501EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
1502