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31#include <linux/hdmi.h>
32#include <linux/i2c.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/vga_switcheroo.h>
37
38#include <drm/drm_displayid.h>
39#include <drm/drm_drv.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_encoder.h>
42#include <drm/drm_print.h>
43#include <drm/drm_scdc_helper.h>
44
45#include "drm_crtc_internal.h"
46
47#define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
50
51#define EDID_EST_TIMINGS 16
52#define EDID_STD_TIMINGS 8
53#define EDID_DETAILED_TIMINGS 4
54
55
56
57
58
59
60
61
62
63#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64
65#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66
67#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68
69#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70
71
72
73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74
75#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76
77#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78
79#define EDID_QUIRK_FORCE_8BPC (1 << 8)
80
81#define EDID_QUIRK_FORCE_12BPC (1 << 9)
82
83#define EDID_QUIRK_FORCE_6BPC (1 << 10)
84
85#define EDID_QUIRK_FORCE_10BPC (1 << 11)
86
87#define EDID_QUIRK_NON_DESKTOP (1 << 12)
88
89struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95};
96
97#define LEVEL_DMT 0
98#define LEVEL_GTF 1
99#define LEVEL_GTF2 2
100#define LEVEL_CVT 3
101
102static const struct edid_quirk {
103 char vendor[4];
104 int product_id;
105 u32 quirks;
106} edid_quirk_list[] = {
107
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111
112
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
115
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
118
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
121
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
124
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
127
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135
136
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
140
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
143
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
147
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
152
153
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
156
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
158
159
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
161
162
163 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
164
165
166 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
167
168
169 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
170 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
171 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
172 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
186
187
188 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
189 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
190
191
192 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
193 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
194 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
195
196
197 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
198 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
199 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
200 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
201 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
202 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
203 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
204 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
205
206
207 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
208
209
210 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
211
212
213 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
214};
215
216
217
218
219
220static const struct drm_display_mode drm_dmt_modes[] = {
221
222 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
223 736, 832, 0, 350, 382, 385, 445, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
225
226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 400, 401, 404, 445, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
229
230 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
231 828, 936, 0, 400, 401, 404, 446, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233
234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
235 752, 800, 0, 480, 490, 492, 525, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
237
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
239 704, 832, 0, 480, 489, 492, 520, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
243 720, 840, 0, 480, 481, 484, 500, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
247 752, 832, 0, 480, 481, 484, 509, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249
250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
251 896, 1024, 0, 600, 601, 603, 625, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
255 968, 1056, 0, 600, 601, 605, 628, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
259 976, 1040, 0, 600, 637, 643, 666, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
263 896, 1056, 0, 600, 601, 604, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
267 896, 1048, 0, 600, 601, 604, 631, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
271 880, 960, 0, 600, 603, 607, 636, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
273
274 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
275 976, 1088, 0, 480, 486, 494, 517, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277
278 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
279 1208, 1264, 0, 768, 768, 776, 817, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
281 DRM_MODE_FLAG_INTERLACE) },
282
283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
284 1184, 1344, 0, 768, 771, 777, 806, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
286
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
288 1184, 1328, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
292 1136, 1312, 0, 768, 769, 772, 800, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
296 1168, 1376, 0, 768, 769, 772, 808, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
300 1104, 1184, 0, 768, 771, 775, 813, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302
303 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
304 1344, 1600, 0, 864, 865, 868, 900, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306
307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
308 1430, 1650, 0, 720, 725, 730, 750, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310
311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
312 1360, 1440, 0, 768, 771, 778, 790, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
316 1472, 1664, 0, 768, 771, 778, 798, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
320 1488, 1696, 0, 768, 771, 778, 805, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
324 1496, 1712, 0, 768, 771, 778, 809, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
328 1360, 1440, 0, 768, 771, 778, 813, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330
331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
332 1360, 1440, 0, 800, 803, 809, 823, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
336 1480, 1680, 0, 800, 803, 809, 831, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
340 1488, 1696, 0, 800, 803, 809, 838, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
344 1496, 1712, 0, 800, 803, 809, 843, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
348 1360, 1440, 0, 800, 803, 809, 847, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350
351 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
352 1488, 1800, 0, 960, 961, 964, 1000, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
356 1504, 1728, 0, 960, 961, 964, 1011, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
360 1360, 1440, 0, 960, 963, 967, 1017, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362
363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
364 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
372 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
376 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378
379 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
380 1536, 1792, 0, 768, 771, 777, 795, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
384 1440, 1520, 0, 768, 771, 776, 813, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386
387 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
388 1579, 1792, 0, 768, 771, 774, 798, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
392 1436, 1500, 0, 768, 769, 772, 800, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394
395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
396 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
400 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
404 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
408 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
412 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
414
415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
416 1520, 1600, 0, 900, 903, 909, 926, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
420 1672, 1904, 0, 900, 903, 909, 934, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
424 1688, 1936, 0, 900, 903, 909, 942, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
428 1696, 1952, 0, 900, 903, 909, 948, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
432 1520, 1600, 0, 900, 903, 909, 953, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434
435 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
436 1704, 1800, 0, 900, 901, 904, 1000, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
438
439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
460 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
462
463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
464 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
468 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
472 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
476 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
480 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482
483 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
484 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
488 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
492 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494
495 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
496 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
500 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
504 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506
507 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
508 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
510
511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
512 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
516 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
520 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
524 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
528 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530
531 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
532 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
536 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
540 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542
543 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
544 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
546
547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
548 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
550
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
552 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
556 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
564 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566
567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
568 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574};
575
576
577
578
579
580
581
582
583
584
585static const struct drm_display_mode edid_est_modes[] = {
586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
587 968, 1056, 0, 600, 601, 605, 628, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
590 896, 1024, 0, 600, 601, 603, 625, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
593 720, 840, 0, 480, 481, 484, 500, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
596 704, 832, 0, 480, 489, 492, 520, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
599 768, 864, 0, 480, 483, 486, 525, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
602 752, 800, 0, 480, 490, 492, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
605 846, 900, 0, 400, 421, 423, 449, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
608 846, 900, 0, 400, 412, 414, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
610 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
611 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
614 1136, 1312, 0, 768, 769, 772, 800, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
617 1184, 1328, 0, 768, 771, 777, 806, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
620 1184, 1344, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
622 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
623 1208, 1264, 0, 768, 768, 776, 817, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) },
625 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
626 928, 1152, 0, 624, 625, 628, 667, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
629 896, 1056, 0, 600, 601, 604, 625, 0,
630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
632 976, 1040, 0, 600, 637, 643, 666, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
634 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
635 1344, 1600, 0, 864, 865, 868, 900, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
637};
638
639struct minimode {
640 short w;
641 short h;
642 short r;
643 short rb;
644};
645
646static const struct minimode est3_modes[] = {
647
648 { 640, 350, 85, 0 },
649 { 640, 400, 85, 0 },
650 { 720, 400, 85, 0 },
651 { 640, 480, 85, 0 },
652 { 848, 480, 60, 0 },
653 { 800, 600, 85, 0 },
654 { 1024, 768, 85, 0 },
655 { 1152, 864, 75, 0 },
656
657 { 1280, 768, 60, 1 },
658 { 1280, 768, 60, 0 },
659 { 1280, 768, 75, 0 },
660 { 1280, 768, 85, 0 },
661 { 1280, 960, 60, 0 },
662 { 1280, 960, 85, 0 },
663 { 1280, 1024, 60, 0 },
664 { 1280, 1024, 85, 0 },
665
666 { 1360, 768, 60, 0 },
667 { 1440, 900, 60, 1 },
668 { 1440, 900, 60, 0 },
669 { 1440, 900, 75, 0 },
670 { 1440, 900, 85, 0 },
671 { 1400, 1050, 60, 1 },
672 { 1400, 1050, 60, 0 },
673 { 1400, 1050, 75, 0 },
674
675 { 1400, 1050, 85, 0 },
676 { 1680, 1050, 60, 1 },
677 { 1680, 1050, 60, 0 },
678 { 1680, 1050, 75, 0 },
679 { 1680, 1050, 85, 0 },
680 { 1600, 1200, 60, 0 },
681 { 1600, 1200, 65, 0 },
682 { 1600, 1200, 70, 0 },
683
684 { 1600, 1200, 75, 0 },
685 { 1600, 1200, 85, 0 },
686 { 1792, 1344, 60, 0 },
687 { 1792, 1344, 75, 0 },
688 { 1856, 1392, 60, 0 },
689 { 1856, 1392, 75, 0 },
690 { 1920, 1200, 60, 1 },
691 { 1920, 1200, 60, 0 },
692
693 { 1920, 1200, 75, 0 },
694 { 1920, 1200, 85, 0 },
695 { 1920, 1440, 60, 0 },
696 { 1920, 1440, 75, 0 },
697};
698
699static const struct minimode extra_modes[] = {
700 { 1024, 576, 60, 0 },
701 { 1366, 768, 60, 0 },
702 { 1600, 900, 60, 0 },
703 { 1680, 945, 60, 0 },
704 { 1920, 1080, 60, 0 },
705 { 2048, 1152, 60, 0 },
706 { 2048, 1536, 60, 0 },
707};
708
709
710
711
712
713
714
715static const struct drm_display_mode edid_cea_modes[] = {
716
717 { },
718
719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723
724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728
729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
733
734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738
739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
742 DRM_MODE_FLAG_INTERLACE),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744
745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750
751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756
757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_DBLCLK),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
762
763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_DBLCLK),
767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768
769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE),
773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774
775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE),
779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780
781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785
786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790
791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795
796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800
801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805
806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810
811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
815
816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
824 DRM_MODE_FLAG_INTERLACE),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826
827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832
833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838
839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_DBLCLK),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844
845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_DBLCLK),
849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850
851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE),
855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
856
857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_INTERLACE),
861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862
863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867
868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
872
873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877
878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882
883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887
888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892
893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897
898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902
903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
907
908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912
913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917
918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928
929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
932 DRM_MODE_FLAG_INTERLACE),
933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
944
945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949
950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
955
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961
962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
965 DRM_MODE_FLAG_INTERLACE),
966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967
968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
977
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982
983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
988
989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994
995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
999
1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004
1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1010
1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1016
1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1021
1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026
1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1032
1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1038
1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043
1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048
1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1053
1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058
1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1068
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1073
1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1078
1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1083
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098
1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103
1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108
1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113
1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133
1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138
1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143
1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148
1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168
1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173
1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178
1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183
1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203
1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1208
1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1213
1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1218
1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1223
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228
1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1233
1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1238
1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1243
1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1248
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1258
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1263
1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1268
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1273
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1278};
1279
1280
1281
1282
1283static const struct drm_display_mode edid_4k_modes[] = {
1284
1285 { },
1286
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1288 3840, 4016, 4104, 4400, 0,
1289 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .vrefresh = 30, },
1292
1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1294 3840, 4896, 4984, 5280, 0,
1295 2160, 2168, 2178, 2250, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .vrefresh = 25, },
1298
1299 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1300 3840, 5116, 5204, 5500, 0,
1301 2160, 2168, 2178, 2250, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .vrefresh = 24, },
1304
1305 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1306 4096, 5116, 5204, 5500, 0,
1307 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .vrefresh = 24, },
1310};
1311
1312
1313
1314static const u8 edid_header[] = {
1315 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1316};
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326int drm_edid_header_is_valid(const u8 *raw_edid)
1327{
1328 int i, score = 0;
1329
1330 for (i = 0; i < sizeof(edid_header); i++)
1331 if (raw_edid[i] == edid_header[i])
1332 score++;
1333
1334 return score;
1335}
1336EXPORT_SYMBOL(drm_edid_header_is_valid);
1337
1338static int edid_fixup __read_mostly = 6;
1339module_param_named(edid_fixup, edid_fixup, int, 0400);
1340MODULE_PARM_DESC(edid_fixup,
1341 "Minimum number of valid EDID header bytes (0-8, default 6)");
1342
1343static void drm_get_displayid(struct drm_connector *connector,
1344 struct edid *edid);
1345static int validate_displayid(u8 *displayid, int length, int idx);
1346
1347static int drm_edid_block_checksum(const u8 *raw_edid)
1348{
1349 int i;
1350 u8 csum = 0;
1351 for (i = 0; i < EDID_LENGTH; i++)
1352 csum += raw_edid[i];
1353
1354 return csum;
1355}
1356
1357static bool drm_edid_is_zero(const u8 *in_edid, int length)
1358{
1359 if (memchr_inv(in_edid, 0, length))
1360 return false;
1361
1362 return true;
1363}
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1378 bool *edid_corrupt)
1379{
1380 u8 csum;
1381 struct edid *edid = (struct edid *)raw_edid;
1382
1383 if (WARN_ON(!raw_edid))
1384 return false;
1385
1386 if (edid_fixup > 8 || edid_fixup < 0)
1387 edid_fixup = 6;
1388
1389 if (block == 0) {
1390 int score = drm_edid_header_is_valid(raw_edid);
1391 if (score == 8) {
1392 if (edid_corrupt)
1393 *edid_corrupt = false;
1394 } else if (score >= edid_fixup) {
1395
1396
1397
1398
1399
1400 if (edid_corrupt)
1401 *edid_corrupt = true;
1402 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1403 memcpy(raw_edid, edid_header, sizeof(edid_header));
1404 } else {
1405 if (edid_corrupt)
1406 *edid_corrupt = true;
1407 goto bad;
1408 }
1409 }
1410
1411 csum = drm_edid_block_checksum(raw_edid);
1412 if (csum) {
1413 if (edid_corrupt)
1414 *edid_corrupt = true;
1415
1416
1417 if (raw_edid[0] == CEA_EXT) {
1418 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1419 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1420 } else {
1421 if (print_bad_edid)
1422 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1423
1424 goto bad;
1425 }
1426 }
1427
1428
1429 switch (raw_edid[0]) {
1430 case 0:
1431 if (edid->version != 1) {
1432 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1433 goto bad;
1434 }
1435
1436 if (edid->revision > 4)
1437 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1438 break;
1439
1440 default:
1441 break;
1442 }
1443
1444 return true;
1445
1446bad:
1447 if (print_bad_edid) {
1448 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1449 pr_notice("EDID block is all zeroes\n");
1450 } else {
1451 pr_notice("Raw EDID:\n");
1452 print_hex_dump(KERN_NOTICE,
1453 " \t", DUMP_PREFIX_NONE, 16, 1,
1454 raw_edid, EDID_LENGTH, false);
1455 }
1456 }
1457 return false;
1458}
1459EXPORT_SYMBOL(drm_edid_block_valid);
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469bool drm_edid_is_valid(struct edid *edid)
1470{
1471 int i;
1472 u8 *raw = (u8 *)edid;
1473
1474 if (!edid)
1475 return false;
1476
1477 for (i = 0; i <= edid->extensions; i++)
1478 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1479 return false;
1480
1481 return true;
1482}
1483EXPORT_SYMBOL(drm_edid_is_valid);
1484
1485#define DDC_SEGMENT_ADDR 0x30
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497static int
1498drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1499{
1500 struct i2c_adapter *adapter = data;
1501 unsigned char start = block * EDID_LENGTH;
1502 unsigned char segment = block >> 1;
1503 unsigned char xfers = segment ? 3 : 2;
1504 int ret, retries = 5;
1505
1506
1507
1508
1509
1510
1511
1512
1513 do {
1514 struct i2c_msg msgs[] = {
1515 {
1516 .addr = DDC_SEGMENT_ADDR,
1517 .flags = 0,
1518 .len = 1,
1519 .buf = &segment,
1520 }, {
1521 .addr = DDC_ADDR,
1522 .flags = 0,
1523 .len = 1,
1524 .buf = &start,
1525 }, {
1526 .addr = DDC_ADDR,
1527 .flags = I2C_M_RD,
1528 .len = len,
1529 .buf = buf,
1530 }
1531 };
1532
1533
1534
1535
1536
1537 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1538
1539 if (ret == -ENXIO) {
1540 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1541 adapter->name);
1542 break;
1543 }
1544 } while (ret != xfers && --retries);
1545
1546 return ret == xfers ? 0 : -1;
1547}
1548
1549static void connector_bad_edid(struct drm_connector *connector,
1550 u8 *edid, int num_blocks)
1551{
1552 int i;
1553
1554 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1555 return;
1556
1557 dev_warn(connector->dev->dev,
1558 "%s: EDID is invalid:\n",
1559 connector->name);
1560 for (i = 0; i < num_blocks; i++) {
1561 u8 *block = edid + i * EDID_LENGTH;
1562 char prefix[20];
1563
1564 if (drm_edid_is_zero(block, EDID_LENGTH))
1565 sprintf(prefix, "\t[%02x] ZERO ", i);
1566 else if (!drm_edid_block_valid(block, i, false, NULL))
1567 sprintf(prefix, "\t[%02x] BAD ", i);
1568 else
1569 sprintf(prefix, "\t[%02x] GOOD ", i);
1570
1571 print_hex_dump(KERN_WARNING,
1572 prefix, DUMP_PREFIX_NONE, 16, 1,
1573 block, EDID_LENGTH, false);
1574 }
1575}
1576
1577
1578static struct edid *drm_get_override_edid(struct drm_connector *connector)
1579{
1580 struct edid *override = NULL;
1581
1582 if (connector->override_edid)
1583 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1584
1585 if (!override)
1586 override = drm_load_edid_firmware(connector);
1587
1588 return IS_ERR(override) ? NULL : override;
1589}
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602int drm_add_override_edid_modes(struct drm_connector *connector)
1603{
1604 struct edid *override;
1605 int num_modes = 0;
1606
1607 override = drm_get_override_edid(connector);
1608 if (override) {
1609 drm_connector_update_edid_property(connector, override);
1610 num_modes = drm_add_edid_modes(connector, override);
1611 kfree(override);
1612
1613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1614 connector->base.id, connector->name, num_modes);
1615 }
1616
1617 return num_modes;
1618}
1619EXPORT_SYMBOL(drm_add_override_edid_modes);
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641struct edid *drm_do_get_edid(struct drm_connector *connector,
1642 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1643 size_t len),
1644 void *data)
1645{
1646 int i, j = 0, valid_extensions = 0;
1647 u8 *edid, *new;
1648 struct edid *override;
1649
1650 override = drm_get_override_edid(connector);
1651 if (override)
1652 return override;
1653
1654 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1655 return NULL;
1656
1657
1658 for (i = 0; i < 4; i++) {
1659 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1660 goto out;
1661 if (drm_edid_block_valid(edid, 0, false,
1662 &connector->edid_corrupt))
1663 break;
1664 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1665 connector->null_edid_counter++;
1666 goto carp;
1667 }
1668 }
1669 if (i == 4)
1670 goto carp;
1671
1672
1673 valid_extensions = edid[0x7e];
1674 if (valid_extensions == 0)
1675 return (struct edid *)edid;
1676
1677 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1678 if (!new)
1679 goto out;
1680 edid = new;
1681
1682 for (j = 1; j <= edid[0x7e]; j++) {
1683 u8 *block = edid + j * EDID_LENGTH;
1684
1685 for (i = 0; i < 4; i++) {
1686 if (get_edid_block(data, block, j, EDID_LENGTH))
1687 goto out;
1688 if (drm_edid_block_valid(block, j, false, NULL))
1689 break;
1690 }
1691
1692 if (i == 4)
1693 valid_extensions--;
1694 }
1695
1696 if (valid_extensions != edid[0x7e]) {
1697 u8 *base;
1698
1699 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1700
1701 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1702 edid[0x7e] = valid_extensions;
1703
1704 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1705 GFP_KERNEL);
1706 if (!new)
1707 goto out;
1708
1709 base = new;
1710 for (i = 0; i <= edid[0x7e]; i++) {
1711 u8 *block = edid + i * EDID_LENGTH;
1712
1713 if (!drm_edid_block_valid(block, i, false, NULL))
1714 continue;
1715
1716 memcpy(base, block, EDID_LENGTH);
1717 base += EDID_LENGTH;
1718 }
1719
1720 kfree(edid);
1721 edid = new;
1722 }
1723
1724 return (struct edid *)edid;
1725
1726carp:
1727 connector_bad_edid(connector, edid, 1);
1728out:
1729 kfree(edid);
1730 return NULL;
1731}
1732EXPORT_SYMBOL_GPL(drm_do_get_edid);
1733
1734
1735
1736
1737
1738
1739
1740bool
1741drm_probe_ddc(struct i2c_adapter *adapter)
1742{
1743 unsigned char out;
1744
1745 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1746}
1747EXPORT_SYMBOL(drm_probe_ddc);
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759struct edid *drm_get_edid(struct drm_connector *connector,
1760 struct i2c_adapter *adapter)
1761{
1762 struct edid *edid;
1763
1764 if (connector->force == DRM_FORCE_OFF)
1765 return NULL;
1766
1767 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1768 return NULL;
1769
1770 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1771 if (edid)
1772 drm_get_displayid(connector, edid);
1773 return edid;
1774}
1775EXPORT_SYMBOL(drm_get_edid);
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1789 struct i2c_adapter *adapter)
1790{
1791 struct pci_dev *pdev = connector->dev->pdev;
1792 struct edid *edid;
1793
1794 vga_switcheroo_lock_ddc(pdev);
1795 edid = drm_get_edid(connector, adapter);
1796 vga_switcheroo_unlock_ddc(pdev);
1797
1798 return edid;
1799}
1800EXPORT_SYMBOL(drm_get_edid_switcheroo);
1801
1802
1803
1804
1805
1806
1807
1808struct edid *drm_edid_duplicate(const struct edid *edid)
1809{
1810 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1811}
1812EXPORT_SYMBOL(drm_edid_duplicate);
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823static bool edid_vendor(const struct edid *edid, const char *vendor)
1824{
1825 char edid_vendor[3];
1826
1827 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1828 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1829 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1830 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1831
1832 return !strncmp(edid_vendor, vendor, 3);
1833}
1834
1835
1836
1837
1838
1839
1840
1841static u32 edid_get_quirks(const struct edid *edid)
1842{
1843 const struct edid_quirk *quirk;
1844 int i;
1845
1846 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1847 quirk = &edid_quirk_list[i];
1848
1849 if (edid_vendor(edid, quirk->vendor) &&
1850 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1851 return quirk->quirks;
1852 }
1853
1854 return 0;
1855}
1856
1857#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1858#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868static void edid_fixup_preferred(struct drm_connector *connector,
1869 u32 quirks)
1870{
1871 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1872 int target_refresh = 0;
1873 int cur_vrefresh, preferred_vrefresh;
1874
1875 if (list_empty(&connector->probed_modes))
1876 return;
1877
1878 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1879 target_refresh = 60;
1880 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1881 target_refresh = 75;
1882
1883 preferred_mode = list_first_entry(&connector->probed_modes,
1884 struct drm_display_mode, head);
1885
1886 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1887 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1888
1889 if (cur_mode == preferred_mode)
1890 continue;
1891
1892
1893 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1894 preferred_mode = cur_mode;
1895
1896 cur_vrefresh = cur_mode->vrefresh ?
1897 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1898 preferred_vrefresh = preferred_mode->vrefresh ?
1899 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1900
1901 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1902 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1903 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1904 preferred_mode = cur_mode;
1905 }
1906 }
1907
1908 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1909}
1910
1911static bool
1912mode_is_rb(const struct drm_display_mode *mode)
1913{
1914 return (mode->htotal - mode->hdisplay == 160) &&
1915 (mode->hsync_end - mode->hdisplay == 80) &&
1916 (mode->hsync_end - mode->hsync_start == 32) &&
1917 (mode->vsync_start - mode->vdisplay == 3);
1918}
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1933 int hsize, int vsize, int fresh,
1934 bool rb)
1935{
1936 int i;
1937
1938 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1939 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1940 if (hsize != ptr->hdisplay)
1941 continue;
1942 if (vsize != ptr->vdisplay)
1943 continue;
1944 if (fresh != drm_mode_vrefresh(ptr))
1945 continue;
1946 if (rb != mode_is_rb(ptr))
1947 continue;
1948
1949 return drm_mode_duplicate(dev, ptr);
1950 }
1951
1952 return NULL;
1953}
1954EXPORT_SYMBOL(drm_mode_find_dmt);
1955
1956typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1957
1958static void
1959cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1960{
1961 int i, n = 0;
1962 u8 d = ext[0x02];
1963 u8 *det_base = ext + d;
1964
1965 n = (127 - d) / 18;
1966 for (i = 0; i < n; i++)
1967 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1968}
1969
1970static void
1971vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1972{
1973 unsigned int i, n = min((int)ext[0x02], 6);
1974 u8 *det_base = ext + 5;
1975
1976 if (ext[0x01] != 1)
1977 return;
1978
1979 for (i = 0; i < n; i++)
1980 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1981}
1982
1983static void
1984drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1985{
1986 int i;
1987 struct edid *edid = (struct edid *)raw_edid;
1988
1989 if (edid == NULL)
1990 return;
1991
1992 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1993 cb(&(edid->detailed_timings[i]), closure);
1994
1995 for (i = 1; i <= raw_edid[0x7e]; i++) {
1996 u8 *ext = raw_edid + (i * EDID_LENGTH);
1997 switch (*ext) {
1998 case CEA_EXT:
1999 cea_for_each_detailed_block(ext, cb, closure);
2000 break;
2001 case VTB_EXT:
2002 vtb_for_each_detailed_block(ext, cb, closure);
2003 break;
2004 default:
2005 break;
2006 }
2007 }
2008}
2009
2010static void
2011is_rb(struct detailed_timing *t, void *data)
2012{
2013 u8 *r = (u8 *)t;
2014 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2015 if (r[15] & 0x10)
2016 *(bool *)data = true;
2017}
2018
2019
2020static bool
2021drm_monitor_supports_rb(struct edid *edid)
2022{
2023 if (edid->revision >= 4) {
2024 bool ret = false;
2025 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2026 return ret;
2027 }
2028
2029 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2030}
2031
2032static void
2033find_gtf2(struct detailed_timing *t, void *data)
2034{
2035 u8 *r = (u8 *)t;
2036 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2037 *(u8 **)data = r;
2038}
2039
2040
2041static int
2042drm_gtf2_hbreak(struct edid *edid)
2043{
2044 u8 *r = NULL;
2045 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2046 return r ? (r[12] * 2) : 0;
2047}
2048
2049static int
2050drm_gtf2_2c(struct edid *edid)
2051{
2052 u8 *r = NULL;
2053 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2054 return r ? r[13] : 0;
2055}
2056
2057static int
2058drm_gtf2_m(struct edid *edid)
2059{
2060 u8 *r = NULL;
2061 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2062 return r ? (r[15] << 8) + r[14] : 0;
2063}
2064
2065static int
2066drm_gtf2_k(struct edid *edid)
2067{
2068 u8 *r = NULL;
2069 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2070 return r ? r[16] : 0;
2071}
2072
2073static int
2074drm_gtf2_2j(struct edid *edid)
2075{
2076 u8 *r = NULL;
2077 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2078 return r ? r[17] : 0;
2079}
2080
2081
2082
2083
2084
2085static int standard_timing_level(struct edid *edid)
2086{
2087 if (edid->revision >= 2) {
2088 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2089 return LEVEL_CVT;
2090 if (drm_gtf2_hbreak(edid))
2091 return LEVEL_GTF2;
2092 return LEVEL_GTF;
2093 }
2094 return LEVEL_DMT;
2095}
2096
2097
2098
2099
2100
2101static int
2102bad_std_timing(u8 a, u8 b)
2103{
2104 return (a == 0x00 && b == 0x00) ||
2105 (a == 0x01 && b == 0x01) ||
2106 (a == 0x20 && b == 0x20);
2107}
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118static struct drm_display_mode *
2119drm_mode_std(struct drm_connector *connector, struct edid *edid,
2120 struct std_timing *t)
2121{
2122 struct drm_device *dev = connector->dev;
2123 struct drm_display_mode *m, *mode = NULL;
2124 int hsize, vsize;
2125 int vrefresh_rate;
2126 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2127 >> EDID_TIMING_ASPECT_SHIFT;
2128 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2129 >> EDID_TIMING_VFREQ_SHIFT;
2130 int timing_level = standard_timing_level(edid);
2131
2132 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2133 return NULL;
2134
2135
2136 hsize = t->hsize * 8 + 248;
2137
2138 vrefresh_rate = vfreq + 60;
2139
2140 if (aspect_ratio == 0) {
2141 if (edid->revision < 3)
2142 vsize = hsize;
2143 else
2144 vsize = (hsize * 10) / 16;
2145 } else if (aspect_ratio == 1)
2146 vsize = (hsize * 3) / 4;
2147 else if (aspect_ratio == 2)
2148 vsize = (hsize * 4) / 5;
2149 else
2150 vsize = (hsize * 9) / 16;
2151
2152
2153 if (vrefresh_rate == 60 &&
2154 ((hsize == 1360 && vsize == 765) ||
2155 (hsize == 1368 && vsize == 769))) {
2156 hsize = 1366;
2157 vsize = 768;
2158 }
2159
2160
2161
2162
2163
2164
2165
2166 list_for_each_entry(m, &connector->probed_modes, head)
2167 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2168 drm_mode_vrefresh(m) == vrefresh_rate)
2169 return NULL;
2170
2171
2172 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2173 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2174 false);
2175 if (!mode)
2176 return NULL;
2177 mode->hdisplay = 1366;
2178 mode->hsync_start = mode->hsync_start - 1;
2179 mode->hsync_end = mode->hsync_end - 1;
2180 return mode;
2181 }
2182
2183
2184 if (drm_monitor_supports_rb(edid)) {
2185 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2186 true);
2187 if (mode)
2188 return mode;
2189 }
2190 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2191 if (mode)
2192 return mode;
2193
2194
2195 switch (timing_level) {
2196 case LEVEL_DMT:
2197 break;
2198 case LEVEL_GTF:
2199 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2200 break;
2201 case LEVEL_GTF2:
2202
2203
2204
2205
2206
2207 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2208 if (!mode)
2209 return NULL;
2210 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2211 drm_mode_destroy(dev, mode);
2212 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2213 vrefresh_rate, 0, 0,
2214 drm_gtf2_m(edid),
2215 drm_gtf2_2c(edid),
2216 drm_gtf2_k(edid),
2217 drm_gtf2_2j(edid));
2218 }
2219 break;
2220 case LEVEL_CVT:
2221 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2222 false);
2223 break;
2224 }
2225 return mode;
2226}
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236static void
2237drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2238 struct detailed_pixel_timing *pt)
2239{
2240 int i;
2241 static const struct {
2242 int w, h;
2243 } cea_interlaced[] = {
2244 { 1920, 1080 },
2245 { 720, 480 },
2246 { 1440, 480 },
2247 { 2880, 480 },
2248 { 720, 576 },
2249 { 1440, 576 },
2250 { 2880, 576 },
2251 };
2252
2253 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2254 return;
2255
2256 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2257 if ((mode->hdisplay == cea_interlaced[i].w) &&
2258 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2259 mode->vdisplay *= 2;
2260 mode->vsync_start *= 2;
2261 mode->vsync_end *= 2;
2262 mode->vtotal *= 2;
2263 mode->vtotal |= 1;
2264 }
2265 }
2266
2267 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2268}
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2281 struct edid *edid,
2282 struct detailed_timing *timing,
2283 u32 quirks)
2284{
2285 struct drm_display_mode *mode;
2286 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2287 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2288 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2289 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2290 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2291 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2292 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2293 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2294 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2295
2296
2297 if (hactive < 64 || vactive < 64)
2298 return NULL;
2299
2300 if (pt->misc & DRM_EDID_PT_STEREO) {
2301 DRM_DEBUG_KMS("stereo mode not supported\n");
2302 return NULL;
2303 }
2304 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2305 DRM_DEBUG_KMS("composite sync not supported\n");
2306 }
2307
2308
2309 if (!hsync_pulse_width || !vsync_pulse_width) {
2310 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2311 "Wrong Hsync/Vsync pulse width\n");
2312 return NULL;
2313 }
2314
2315 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2316 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2317 if (!mode)
2318 return NULL;
2319
2320 goto set_size;
2321 }
2322
2323 mode = drm_mode_create(dev);
2324 if (!mode)
2325 return NULL;
2326
2327 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2328 timing->pixel_clock = cpu_to_le16(1088);
2329
2330 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2331
2332 mode->hdisplay = hactive;
2333 mode->hsync_start = mode->hdisplay + hsync_offset;
2334 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2335 mode->htotal = mode->hdisplay + hblank;
2336
2337 mode->vdisplay = vactive;
2338 mode->vsync_start = mode->vdisplay + vsync_offset;
2339 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2340 mode->vtotal = mode->vdisplay + vblank;
2341
2342
2343 if (mode->hsync_end > mode->htotal)
2344 mode->htotal = mode->hsync_end + 1;
2345 if (mode->vsync_end > mode->vtotal)
2346 mode->vtotal = mode->vsync_end + 1;
2347
2348 drm_mode_do_interlace_quirk(mode, pt);
2349
2350 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2351 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2352 }
2353
2354 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2355 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2356 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2357 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2358
2359set_size:
2360 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2361 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2362
2363 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2364 mode->width_mm *= 10;
2365 mode->height_mm *= 10;
2366 }
2367
2368 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2369 mode->width_mm = edid->width_cm * 10;
2370 mode->height_mm = edid->height_cm * 10;
2371 }
2372
2373 mode->type = DRM_MODE_TYPE_DRIVER;
2374 mode->vrefresh = drm_mode_vrefresh(mode);
2375 drm_mode_set_name(mode);
2376
2377 return mode;
2378}
2379
2380static bool
2381mode_in_hsync_range(const struct drm_display_mode *mode,
2382 struct edid *edid, u8 *t)
2383{
2384 int hsync, hmin, hmax;
2385
2386 hmin = t[7];
2387 if (edid->revision >= 4)
2388 hmin += ((t[4] & 0x04) ? 255 : 0);
2389 hmax = t[8];
2390 if (edid->revision >= 4)
2391 hmax += ((t[4] & 0x08) ? 255 : 0);
2392 hsync = drm_mode_hsync(mode);
2393
2394 return (hsync <= hmax && hsync >= hmin);
2395}
2396
2397static bool
2398mode_in_vsync_range(const struct drm_display_mode *mode,
2399 struct edid *edid, u8 *t)
2400{
2401 int vsync, vmin, vmax;
2402
2403 vmin = t[5];
2404 if (edid->revision >= 4)
2405 vmin += ((t[4] & 0x01) ? 255 : 0);
2406 vmax = t[6];
2407 if (edid->revision >= 4)
2408 vmax += ((t[4] & 0x02) ? 255 : 0);
2409 vsync = drm_mode_vrefresh(mode);
2410
2411 return (vsync <= vmax && vsync >= vmin);
2412}
2413
2414static u32
2415range_pixel_clock(struct edid *edid, u8 *t)
2416{
2417
2418 if (t[9] == 0 || t[9] == 255)
2419 return 0;
2420
2421
2422 if (edid->revision >= 4 && t[10] == 0x04)
2423 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2424
2425
2426 return t[9] * 10000 + 5001;
2427}
2428
2429static bool
2430mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2431 struct detailed_timing *timing)
2432{
2433 u32 max_clock;
2434 u8 *t = (u8 *)timing;
2435
2436 if (!mode_in_hsync_range(mode, edid, t))
2437 return false;
2438
2439 if (!mode_in_vsync_range(mode, edid, t))
2440 return false;
2441
2442 if ((max_clock = range_pixel_clock(edid, t)))
2443 if (mode->clock > max_clock)
2444 return false;
2445
2446
2447 if (edid->revision >= 4 && t[10] == 0x04)
2448 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2449 return false;
2450
2451 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2452 return false;
2453
2454 return true;
2455}
2456
2457static bool valid_inferred_mode(const struct drm_connector *connector,
2458 const struct drm_display_mode *mode)
2459{
2460 const struct drm_display_mode *m;
2461 bool ok = false;
2462
2463 list_for_each_entry(m, &connector->probed_modes, head) {
2464 if (mode->hdisplay == m->hdisplay &&
2465 mode->vdisplay == m->vdisplay &&
2466 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2467 return false;
2468 if (mode->hdisplay <= m->hdisplay &&
2469 mode->vdisplay <= m->vdisplay)
2470 ok = true;
2471 }
2472 return ok;
2473}
2474
2475static int
2476drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2477 struct detailed_timing *timing)
2478{
2479 int i, modes = 0;
2480 struct drm_display_mode *newmode;
2481 struct drm_device *dev = connector->dev;
2482
2483 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2484 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2485 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2486 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2487 if (newmode) {
2488 drm_mode_probed_add(connector, newmode);
2489 modes++;
2490 }
2491 }
2492 }
2493
2494 return modes;
2495}
2496
2497
2498
2499
2500void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2501{
2502 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2503 mode->hdisplay = 1366;
2504 mode->hsync_start--;
2505 mode->hsync_end--;
2506 drm_mode_set_name(mode);
2507 }
2508}
2509
2510static int
2511drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2512 struct detailed_timing *timing)
2513{
2514 int i, modes = 0;
2515 struct drm_display_mode *newmode;
2516 struct drm_device *dev = connector->dev;
2517
2518 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2519 const struct minimode *m = &extra_modes[i];
2520 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2521 if (!newmode)
2522 return modes;
2523
2524 drm_mode_fixup_1366x768(newmode);
2525 if (!mode_in_range(newmode, edid, timing) ||
2526 !valid_inferred_mode(connector, newmode)) {
2527 drm_mode_destroy(dev, newmode);
2528 continue;
2529 }
2530
2531 drm_mode_probed_add(connector, newmode);
2532 modes++;
2533 }
2534
2535 return modes;
2536}
2537
2538static int
2539drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2540 struct detailed_timing *timing)
2541{
2542 int i, modes = 0;
2543 struct drm_display_mode *newmode;
2544 struct drm_device *dev = connector->dev;
2545 bool rb = drm_monitor_supports_rb(edid);
2546
2547 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2548 const struct minimode *m = &extra_modes[i];
2549 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2550 if (!newmode)
2551 return modes;
2552
2553 drm_mode_fixup_1366x768(newmode);
2554 if (!mode_in_range(newmode, edid, timing) ||
2555 !valid_inferred_mode(connector, newmode)) {
2556 drm_mode_destroy(dev, newmode);
2557 continue;
2558 }
2559
2560 drm_mode_probed_add(connector, newmode);
2561 modes++;
2562 }
2563
2564 return modes;
2565}
2566
2567static void
2568do_inferred_modes(struct detailed_timing *timing, void *c)
2569{
2570 struct detailed_mode_closure *closure = c;
2571 struct detailed_non_pixel *data = &timing->data.other_data;
2572 struct detailed_data_monitor_range *range = &data->data.range;
2573
2574 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2575 return;
2576
2577 closure->modes += drm_dmt_modes_for_range(closure->connector,
2578 closure->edid,
2579 timing);
2580
2581 if (!version_greater(closure->edid, 1, 1))
2582 return;
2583
2584 switch (range->flags) {
2585 case 0x02:
2586 case 0x00:
2587 closure->modes += drm_gtf_modes_for_range(closure->connector,
2588 closure->edid,
2589 timing);
2590 break;
2591 case 0x04:
2592 if (!version_greater(closure->edid, 1, 3))
2593 break;
2594
2595 closure->modes += drm_cvt_modes_for_range(closure->connector,
2596 closure->edid,
2597 timing);
2598 break;
2599 case 0x01:
2600 default:
2601 break;
2602 }
2603}
2604
2605static int
2606add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2607{
2608 struct detailed_mode_closure closure = {
2609 .connector = connector,
2610 .edid = edid,
2611 };
2612
2613 if (version_greater(edid, 1, 0))
2614 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2615 &closure);
2616
2617 return closure.modes;
2618}
2619
2620static int
2621drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2622{
2623 int i, j, m, modes = 0;
2624 struct drm_display_mode *mode;
2625 u8 *est = ((u8 *)timing) + 6;
2626
2627 for (i = 0; i < 6; i++) {
2628 for (j = 7; j >= 0; j--) {
2629 m = (i * 8) + (7 - j);
2630 if (m >= ARRAY_SIZE(est3_modes))
2631 break;
2632 if (est[i] & (1 << j)) {
2633 mode = drm_mode_find_dmt(connector->dev,
2634 est3_modes[m].w,
2635 est3_modes[m].h,
2636 est3_modes[m].r,
2637 est3_modes[m].rb);
2638 if (mode) {
2639 drm_mode_probed_add(connector, mode);
2640 modes++;
2641 }
2642 }
2643 }
2644 }
2645
2646 return modes;
2647}
2648
2649static void
2650do_established_modes(struct detailed_timing *timing, void *c)
2651{
2652 struct detailed_mode_closure *closure = c;
2653 struct detailed_non_pixel *data = &timing->data.other_data;
2654
2655 if (data->type == EDID_DETAIL_EST_TIMINGS)
2656 closure->modes += drm_est3_modes(closure->connector, timing);
2657}
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667static int
2668add_established_modes(struct drm_connector *connector, struct edid *edid)
2669{
2670 struct drm_device *dev = connector->dev;
2671 unsigned long est_bits = edid->established_timings.t1 |
2672 (edid->established_timings.t2 << 8) |
2673 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2674 int i, modes = 0;
2675 struct detailed_mode_closure closure = {
2676 .connector = connector,
2677 .edid = edid,
2678 };
2679
2680 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2681 if (est_bits & (1<<i)) {
2682 struct drm_display_mode *newmode;
2683 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2684 if (newmode) {
2685 drm_mode_probed_add(connector, newmode);
2686 modes++;
2687 }
2688 }
2689 }
2690
2691 if (version_greater(edid, 1, 0))
2692 drm_for_each_detailed_block((u8 *)edid,
2693 do_established_modes, &closure);
2694
2695 return modes + closure.modes;
2696}
2697
2698static void
2699do_standard_modes(struct detailed_timing *timing, void *c)
2700{
2701 struct detailed_mode_closure *closure = c;
2702 struct detailed_non_pixel *data = &timing->data.other_data;
2703 struct drm_connector *connector = closure->connector;
2704 struct edid *edid = closure->edid;
2705
2706 if (data->type == EDID_DETAIL_STD_MODES) {
2707 int i;
2708 for (i = 0; i < 6; i++) {
2709 struct std_timing *std;
2710 struct drm_display_mode *newmode;
2711
2712 std = &data->data.timings[i];
2713 newmode = drm_mode_std(connector, edid, std);
2714 if (newmode) {
2715 drm_mode_probed_add(connector, newmode);
2716 closure->modes++;
2717 }
2718 }
2719 }
2720}
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730static int
2731add_standard_modes(struct drm_connector *connector, struct edid *edid)
2732{
2733 int i, modes = 0;
2734 struct detailed_mode_closure closure = {
2735 .connector = connector,
2736 .edid = edid,
2737 };
2738
2739 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2740 struct drm_display_mode *newmode;
2741
2742 newmode = drm_mode_std(connector, edid,
2743 &edid->standard_timings[i]);
2744 if (newmode) {
2745 drm_mode_probed_add(connector, newmode);
2746 modes++;
2747 }
2748 }
2749
2750 if (version_greater(edid, 1, 0))
2751 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2752 &closure);
2753
2754
2755
2756 return modes + closure.modes;
2757}
2758
2759static int drm_cvt_modes(struct drm_connector *connector,
2760 struct detailed_timing *timing)
2761{
2762 int i, j, modes = 0;
2763 struct drm_display_mode *newmode;
2764 struct drm_device *dev = connector->dev;
2765 struct cvt_timing *cvt;
2766 const int rates[] = { 60, 85, 75, 60, 50 };
2767 const u8 empty[3] = { 0, 0, 0 };
2768
2769 for (i = 0; i < 4; i++) {
2770 int uninitialized_var(width), height;
2771 cvt = &(timing->data.other_data.data.cvt[i]);
2772
2773 if (!memcmp(cvt->code, empty, 3))
2774 continue;
2775
2776 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2777 switch (cvt->code[1] & 0x0c) {
2778 case 0x00:
2779 width = height * 4 / 3;
2780 break;
2781 case 0x04:
2782 width = height * 16 / 9;
2783 break;
2784 case 0x08:
2785 width = height * 16 / 10;
2786 break;
2787 case 0x0c:
2788 width = height * 15 / 9;
2789 break;
2790 }
2791
2792 for (j = 1; j < 5; j++) {
2793 if (cvt->code[2] & (1 << j)) {
2794 newmode = drm_cvt_mode(dev, width, height,
2795 rates[j], j == 0,
2796 false, false);
2797 if (newmode) {
2798 drm_mode_probed_add(connector, newmode);
2799 modes++;
2800 }
2801 }
2802 }
2803 }
2804
2805 return modes;
2806}
2807
2808static void
2809do_cvt_mode(struct detailed_timing *timing, void *c)
2810{
2811 struct detailed_mode_closure *closure = c;
2812 struct detailed_non_pixel *data = &timing->data.other_data;
2813
2814 if (data->type == EDID_DETAIL_CVT_3BYTE)
2815 closure->modes += drm_cvt_modes(closure->connector, timing);
2816}
2817
2818static int
2819add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2820{
2821 struct detailed_mode_closure closure = {
2822 .connector = connector,
2823 .edid = edid,
2824 };
2825
2826 if (version_greater(edid, 1, 2))
2827 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2828
2829
2830
2831 return closure.modes;
2832}
2833
2834static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2835
2836static void
2837do_detailed_mode(struct detailed_timing *timing, void *c)
2838{
2839 struct detailed_mode_closure *closure = c;
2840 struct drm_display_mode *newmode;
2841
2842 if (timing->pixel_clock) {
2843 newmode = drm_mode_detailed(closure->connector->dev,
2844 closure->edid, timing,
2845 closure->quirks);
2846 if (!newmode)
2847 return;
2848
2849 if (closure->preferred)
2850 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2851
2852
2853
2854
2855
2856
2857 fixup_detailed_cea_mode_clock(newmode);
2858
2859 drm_mode_probed_add(closure->connector, newmode);
2860 closure->modes++;
2861 closure->preferred = false;
2862 }
2863}
2864
2865
2866
2867
2868
2869
2870
2871static int
2872add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2873 u32 quirks)
2874{
2875 struct detailed_mode_closure closure = {
2876 .connector = connector,
2877 .edid = edid,
2878 .preferred = true,
2879 .quirks = quirks,
2880 };
2881
2882 if (closure.preferred && !version_greater(edid, 1, 3))
2883 closure.preferred =
2884 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2885
2886 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2887
2888 return closure.modes;
2889}
2890
2891#define AUDIO_BLOCK 0x01
2892#define VIDEO_BLOCK 0x02
2893#define VENDOR_BLOCK 0x03
2894#define SPEAKER_BLOCK 0x04
2895#define HDR_STATIC_METADATA_BLOCK 0x6
2896#define USE_EXTENDED_TAG 0x07
2897#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2898#define EXT_VIDEO_DATA_BLOCK_420 0x0E
2899#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2900#define EDID_BASIC_AUDIO (1 << 6)
2901#define EDID_CEA_YCRCB444 (1 << 5)
2902#define EDID_CEA_YCRCB422 (1 << 4)
2903#define EDID_CEA_VCDB_QS (1 << 6)
2904
2905
2906
2907
2908static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2909{
2910 u8 *edid_ext = NULL;
2911 int i;
2912
2913
2914 if (edid == NULL || edid->extensions == 0)
2915 return NULL;
2916
2917
2918 for (i = 0; i < edid->extensions; i++) {
2919 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2920 if (edid_ext[0] == ext_id)
2921 break;
2922 }
2923
2924 if (i == edid->extensions)
2925 return NULL;
2926
2927 return edid_ext;
2928}
2929
2930
2931static u8 *drm_find_displayid_extension(const struct edid *edid)
2932{
2933 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2934}
2935
2936static u8 *drm_find_cea_extension(const struct edid *edid)
2937{
2938 int ret;
2939 int idx = 1;
2940 int length = EDID_LENGTH;
2941 struct displayid_block *block;
2942 u8 *cea;
2943 u8 *displayid;
2944
2945
2946 cea = drm_find_edid_extension(edid, CEA_EXT);
2947 if (cea)
2948 return cea;
2949
2950
2951 displayid = drm_find_displayid_extension(edid);
2952 if (!displayid)
2953 return NULL;
2954
2955 ret = validate_displayid(displayid, length, idx);
2956 if (ret)
2957 return NULL;
2958
2959 idx += sizeof(struct displayid_hdr);
2960 for_each_displayid_db(displayid, block, idx, length) {
2961 if (block->tag == DATA_BLOCK_CTA) {
2962 cea = (u8 *)block;
2963 break;
2964 }
2965 }
2966
2967 return cea;
2968}
2969
2970
2971
2972
2973
2974static unsigned int
2975cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2976{
2977 unsigned int clock = cea_mode->clock;
2978
2979 if (cea_mode->vrefresh % 6 != 0)
2980 return clock;
2981
2982
2983
2984
2985
2986
2987 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2988 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2989 else
2990 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2991
2992 return clock;
2993}
2994
2995static bool
2996cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2997{
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
3008 edid_cea_modes[9].vtotal != 262 ||
3009 edid_cea_modes[12].vtotal != 262 ||
3010 edid_cea_modes[13].vtotal != 262 ||
3011 edid_cea_modes[23].vtotal != 312 ||
3012 edid_cea_modes[24].vtotal != 312 ||
3013 edid_cea_modes[27].vtotal != 312 ||
3014 edid_cea_modes[28].vtotal != 312);
3015
3016 if (((vic == 8 || vic == 9 ||
3017 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3018 ((vic == 23 || vic == 24 ||
3019 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3020 mode->vsync_start++;
3021 mode->vsync_end++;
3022 mode->vtotal++;
3023
3024 return true;
3025 }
3026
3027 return false;
3028}
3029
3030static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3031 unsigned int clock_tolerance)
3032{
3033 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3034 u8 vic;
3035
3036 if (!to_match->clock)
3037 return 0;
3038
3039 if (to_match->picture_aspect_ratio)
3040 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3041
3042 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3043 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3044 unsigned int clock1, clock2;
3045
3046
3047 clock1 = cea_mode.clock;
3048 clock2 = cea_mode_alternate_clock(&cea_mode);
3049
3050 if (abs(to_match->clock - clock1) > clock_tolerance &&
3051 abs(to_match->clock - clock2) > clock_tolerance)
3052 continue;
3053
3054 do {
3055 if (drm_mode_match(to_match, &cea_mode, match_flags))
3056 return vic;
3057 } while (cea_mode_alternate_timings(vic, &cea_mode));
3058 }
3059
3060 return 0;
3061}
3062
3063
3064
3065
3066
3067
3068
3069
3070u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3071{
3072 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3073 u8 vic;
3074
3075 if (!to_match->clock)
3076 return 0;
3077
3078 if (to_match->picture_aspect_ratio)
3079 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3080
3081 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3082 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3083 unsigned int clock1, clock2;
3084
3085
3086 clock1 = cea_mode.clock;
3087 clock2 = cea_mode_alternate_clock(&cea_mode);
3088
3089 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3090 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3091 continue;
3092
3093 do {
3094 if (drm_mode_match(to_match, &cea_mode, match_flags))
3095 return vic;
3096 } while (cea_mode_alternate_timings(vic, &cea_mode));
3097 }
3098
3099 return 0;
3100}
3101EXPORT_SYMBOL(drm_match_cea_mode);
3102
3103static bool drm_valid_cea_vic(u8 vic)
3104{
3105 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3106}
3107
3108
3109
3110
3111
3112
3113
3114
3115enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3116{
3117 return edid_cea_modes[video_code].picture_aspect_ratio;
3118}
3119EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129static unsigned int
3130hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3131{
3132 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3133 return hdmi_mode->clock;
3134
3135 return cea_mode_alternate_clock(hdmi_mode);
3136}
3137
3138static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3139 unsigned int clock_tolerance)
3140{
3141 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3142 u8 vic;
3143
3144 if (!to_match->clock)
3145 return 0;
3146
3147 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3148 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3149 unsigned int clock1, clock2;
3150
3151
3152 clock1 = hdmi_mode->clock;
3153 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3154
3155 if (abs(to_match->clock - clock1) > clock_tolerance &&
3156 abs(to_match->clock - clock2) > clock_tolerance)
3157 continue;
3158
3159 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3160 return vic;
3161 }
3162
3163 return 0;
3164}
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3175{
3176 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3177 u8 vic;
3178
3179 if (!to_match->clock)
3180 return 0;
3181
3182 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3183 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3184 unsigned int clock1, clock2;
3185
3186
3187 clock1 = hdmi_mode->clock;
3188 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3189
3190 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3191 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3192 drm_mode_match(to_match, hdmi_mode, match_flags))
3193 return vic;
3194 }
3195 return 0;
3196}
3197
3198static bool drm_valid_hdmi_vic(u8 vic)
3199{
3200 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3201}
3202
3203static int
3204add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3205{
3206 struct drm_device *dev = connector->dev;
3207 struct drm_display_mode *mode, *tmp;
3208 LIST_HEAD(list);
3209 int modes = 0;
3210
3211
3212 if (!drm_find_cea_extension(edid))
3213 return 0;
3214
3215
3216
3217
3218
3219 list_for_each_entry(mode, &connector->probed_modes, head) {
3220 const struct drm_display_mode *cea_mode = NULL;
3221 struct drm_display_mode *newmode;
3222 u8 vic = drm_match_cea_mode(mode);
3223 unsigned int clock1, clock2;
3224
3225 if (drm_valid_cea_vic(vic)) {
3226 cea_mode = &edid_cea_modes[vic];
3227 clock2 = cea_mode_alternate_clock(cea_mode);
3228 } else {
3229 vic = drm_match_hdmi_mode(mode);
3230 if (drm_valid_hdmi_vic(vic)) {
3231 cea_mode = &edid_4k_modes[vic];
3232 clock2 = hdmi_mode_alternate_clock(cea_mode);
3233 }
3234 }
3235
3236 if (!cea_mode)
3237 continue;
3238
3239 clock1 = cea_mode->clock;
3240
3241 if (clock1 == clock2)
3242 continue;
3243
3244 if (mode->clock != clock1 && mode->clock != clock2)
3245 continue;
3246
3247 newmode = drm_mode_duplicate(dev, cea_mode);
3248 if (!newmode)
3249 continue;
3250
3251
3252 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3253
3254
3255
3256
3257
3258 if (mode->clock != clock1)
3259 newmode->clock = clock1;
3260 else
3261 newmode->clock = clock2;
3262
3263 list_add_tail(&newmode->head, &list);
3264 }
3265
3266 list_for_each_entry_safe(mode, tmp, &list, head) {
3267 list_del(&mode->head);
3268 drm_mode_probed_add(connector, mode);
3269 modes++;
3270 }
3271
3272 return modes;
3273}
3274
3275static u8 svd_to_vic(u8 svd)
3276{
3277
3278 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3279 return svd & 127;
3280
3281 return svd;
3282}
3283
3284static struct drm_display_mode *
3285drm_display_mode_from_vic_index(struct drm_connector *connector,
3286 const u8 *video_db, u8 video_len,
3287 u8 video_index)
3288{
3289 struct drm_device *dev = connector->dev;
3290 struct drm_display_mode *newmode;
3291 u8 vic;
3292
3293 if (video_db == NULL || video_index >= video_len)
3294 return NULL;
3295
3296
3297 vic = svd_to_vic(video_db[video_index]);
3298 if (!drm_valid_cea_vic(vic))
3299 return NULL;
3300
3301 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3302 if (!newmode)
3303 return NULL;
3304
3305 newmode->vrefresh = 0;
3306
3307 return newmode;
3308}
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320static int do_y420vdb_modes(struct drm_connector *connector,
3321 const u8 *svds, u8 svds_len)
3322{
3323 int modes = 0, i;
3324 struct drm_device *dev = connector->dev;
3325 struct drm_display_info *info = &connector->display_info;
3326 struct drm_hdmi_info *hdmi = &info->hdmi;
3327
3328 for (i = 0; i < svds_len; i++) {
3329 u8 vic = svd_to_vic(svds[i]);
3330 struct drm_display_mode *newmode;
3331
3332 if (!drm_valid_cea_vic(vic))
3333 continue;
3334
3335 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3336 if (!newmode)
3337 break;
3338 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3339 drm_mode_probed_add(connector, newmode);
3340 modes++;
3341 }
3342
3343 if (modes > 0)
3344 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3345 return modes;
3346}
3347
3348
3349
3350
3351
3352
3353
3354
3355static void
3356drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3357{
3358 u8 vic = svd_to_vic(svd);
3359 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3360
3361 if (!drm_valid_cea_vic(vic))
3362 return;
3363
3364 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3365}
3366
3367static int
3368do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3369{
3370 int i, modes = 0;
3371 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3372
3373 for (i = 0; i < len; i++) {
3374 struct drm_display_mode *mode;
3375 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3376 if (mode) {
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3387 drm_add_cmdb_modes(connector, db[i]);
3388
3389 drm_mode_probed_add(connector, mode);
3390 modes++;
3391 }
3392 }
3393
3394 return modes;
3395}
3396
3397struct stereo_mandatory_mode {
3398 int width, height, vrefresh;
3399 unsigned int flags;
3400};
3401
3402static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3403 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3404 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3405 { 1920, 1080, 50,
3406 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3407 { 1920, 1080, 60,
3408 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3409 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3410 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3411 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3412 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3413};
3414
3415static bool
3416stereo_match_mandatory(const struct drm_display_mode *mode,
3417 const struct stereo_mandatory_mode *stereo_mode)
3418{
3419 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3420
3421 return mode->hdisplay == stereo_mode->width &&
3422 mode->vdisplay == stereo_mode->height &&
3423 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3424 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3425}
3426
3427static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3428{
3429 struct drm_device *dev = connector->dev;
3430 const struct drm_display_mode *mode;
3431 struct list_head stereo_modes;
3432 int modes = 0, i;
3433
3434 INIT_LIST_HEAD(&stereo_modes);
3435
3436 list_for_each_entry(mode, &connector->probed_modes, head) {
3437 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3438 const struct stereo_mandatory_mode *mandatory;
3439 struct drm_display_mode *new_mode;
3440
3441 if (!stereo_match_mandatory(mode,
3442 &stereo_mandatory_modes[i]))
3443 continue;
3444
3445 mandatory = &stereo_mandatory_modes[i];
3446 new_mode = drm_mode_duplicate(dev, mode);
3447 if (!new_mode)
3448 continue;
3449
3450 new_mode->flags |= mandatory->flags;
3451 list_add_tail(&new_mode->head, &stereo_modes);
3452 modes++;
3453 }
3454 }
3455
3456 list_splice_tail(&stereo_modes, &connector->probed_modes);
3457
3458 return modes;
3459}
3460
3461static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3462{
3463 struct drm_device *dev = connector->dev;
3464 struct drm_display_mode *newmode;
3465
3466 if (!drm_valid_hdmi_vic(vic)) {
3467 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3468 return 0;
3469 }
3470
3471 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3472 if (!newmode)
3473 return 0;
3474
3475 drm_mode_probed_add(connector, newmode);
3476
3477 return 1;
3478}
3479
3480static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3481 const u8 *video_db, u8 video_len, u8 video_index)
3482{
3483 struct drm_display_mode *newmode;
3484 int modes = 0;
3485
3486 if (structure & (1 << 0)) {
3487 newmode = drm_display_mode_from_vic_index(connector, video_db,
3488 video_len,
3489 video_index);
3490 if (newmode) {
3491 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3492 drm_mode_probed_add(connector, newmode);
3493 modes++;
3494 }
3495 }
3496 if (structure & (1 << 6)) {
3497 newmode = drm_display_mode_from_vic_index(connector, video_db,
3498 video_len,
3499 video_index);
3500 if (newmode) {
3501 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3502 drm_mode_probed_add(connector, newmode);
3503 modes++;
3504 }
3505 }
3506 if (structure & (1 << 8)) {
3507 newmode = drm_display_mode_from_vic_index(connector, video_db,
3508 video_len,
3509 video_index);
3510 if (newmode) {
3511 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3512 drm_mode_probed_add(connector, newmode);
3513 modes++;
3514 }
3515 }
3516
3517 return modes;
3518}
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529static int
3530do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3531 const u8 *video_db, u8 video_len)
3532{
3533 struct drm_display_info *info = &connector->display_info;
3534 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3535 u8 vic_len, hdmi_3d_len = 0;
3536 u16 mask;
3537 u16 structure_all;
3538
3539 if (len < 8)
3540 goto out;
3541
3542
3543 if (!(db[8] & (1 << 5)))
3544 goto out;
3545
3546
3547 if (db[8] & (1 << 7))
3548 offset += 2;
3549
3550
3551 if (db[8] & (1 << 6))
3552 offset += 2;
3553
3554
3555
3556 if (len < (8 + offset + 2))
3557 goto out;
3558
3559
3560 offset++;
3561 if (db[8 + offset] & (1 << 7)) {
3562 modes += add_hdmi_mandatory_stereo_modes(connector);
3563
3564
3565 multi_present = (db[8 + offset] & 0x60) >> 5;
3566 }
3567
3568 offset++;
3569 vic_len = db[8 + offset] >> 5;
3570 hdmi_3d_len = db[8 + offset] & 0x1f;
3571
3572 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3573 u8 vic;
3574
3575 vic = db[9 + offset + i];
3576 modes += add_hdmi_mode(connector, vic);
3577 }
3578 offset += 1 + vic_len;
3579
3580 if (multi_present == 1)
3581 multi_len = 2;
3582 else if (multi_present == 2)
3583 multi_len = 4;
3584 else
3585 multi_len = 0;
3586
3587 if (len < (8 + offset + hdmi_3d_len - 1))
3588 goto out;
3589
3590 if (hdmi_3d_len < multi_len)
3591 goto out;
3592
3593 if (multi_present == 1 || multi_present == 2) {
3594
3595 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3596
3597
3598 if (multi_present == 2)
3599 mask = (db[10 + offset] << 8) | db[11 + offset];
3600 else
3601 mask = 0xffff;
3602
3603 for (i = 0; i < 16; i++) {
3604 if (mask & (1 << i))
3605 modes += add_3d_struct_modes(connector,
3606 structure_all,
3607 video_db,
3608 video_len, i);
3609 }
3610 }
3611
3612 offset += multi_len;
3613
3614 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3615 int vic_index;
3616 struct drm_display_mode *newmode = NULL;
3617 unsigned int newflag = 0;
3618 bool detail_present;
3619
3620 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3621
3622 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3623 break;
3624
3625
3626 vic_index = db[8 + offset + i] >> 4;
3627
3628
3629 switch (db[8 + offset + i] & 0x0f) {
3630 case 0:
3631 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3632 break;
3633 case 6:
3634 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3635 break;
3636 case 8:
3637
3638 if ((db[9 + offset + i] >> 4) == 1)
3639 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3640 break;
3641 }
3642
3643 if (newflag != 0) {
3644 newmode = drm_display_mode_from_vic_index(connector,
3645 video_db,
3646 video_len,
3647 vic_index);
3648
3649 if (newmode) {
3650 newmode->flags |= newflag;
3651 drm_mode_probed_add(connector, newmode);
3652 modes++;
3653 }
3654 }
3655
3656 if (detail_present)
3657 i++;
3658 }
3659
3660out:
3661 if (modes > 0)
3662 info->has_hdmi_infoframe = true;
3663 return modes;
3664}
3665
3666static int
3667cea_db_payload_len(const u8 *db)
3668{
3669 return db[0] & 0x1f;
3670}
3671
3672static int
3673cea_db_extended_tag(const u8 *db)
3674{
3675 return db[1];
3676}
3677
3678static int
3679cea_db_tag(const u8 *db)
3680{
3681 return db[0] >> 5;
3682}
3683
3684static int
3685cea_revision(const u8 *cea)
3686{
3687 return cea[1];
3688}
3689
3690static int
3691cea_db_offsets(const u8 *cea, int *start, int *end)
3692{
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710 if (cea[0] == DATA_BLOCK_CTA) {
3711 *start = 3;
3712 *end = *start + cea[2];
3713 } else if (cea[0] == CEA_EXT) {
3714
3715 *start = 4;
3716 *end = cea[2];
3717 if (*end == 0)
3718 *end = 127;
3719 if (*end < 4 || *end > 127)
3720 return -ERANGE;
3721 } else {
3722 return -ENOTSUPP;
3723 }
3724
3725 return 0;
3726}
3727
3728static bool cea_db_is_hdmi_vsdb(const u8 *db)
3729{
3730 int hdmi_id;
3731
3732 if (cea_db_tag(db) != VENDOR_BLOCK)
3733 return false;
3734
3735 if (cea_db_payload_len(db) < 5)
3736 return false;
3737
3738 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3739
3740 return hdmi_id == HDMI_IEEE_OUI;
3741}
3742
3743static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3744{
3745 unsigned int oui;
3746
3747 if (cea_db_tag(db) != VENDOR_BLOCK)
3748 return false;
3749
3750 if (cea_db_payload_len(db) < 7)
3751 return false;
3752
3753 oui = db[3] << 16 | db[2] << 8 | db[1];
3754
3755 return oui == HDMI_FORUM_IEEE_OUI;
3756}
3757
3758static bool cea_db_is_vcdb(const u8 *db)
3759{
3760 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3761 return false;
3762
3763 if (cea_db_payload_len(db) != 2)
3764 return false;
3765
3766 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3767 return false;
3768
3769 return true;
3770}
3771
3772static bool cea_db_is_y420cmdb(const u8 *db)
3773{
3774 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3775 return false;
3776
3777 if (!cea_db_payload_len(db))
3778 return false;
3779
3780 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3781 return false;
3782
3783 return true;
3784}
3785
3786static bool cea_db_is_y420vdb(const u8 *db)
3787{
3788 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3789 return false;
3790
3791 if (!cea_db_payload_len(db))
3792 return false;
3793
3794 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3795 return false;
3796
3797 return true;
3798}
3799
3800#define for_each_cea_db(cea, i, start, end) \
3801 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3802
3803static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3804 const u8 *db)
3805{
3806 struct drm_display_info *info = &connector->display_info;
3807 struct drm_hdmi_info *hdmi = &info->hdmi;
3808 u8 map_len = cea_db_payload_len(db) - 1;
3809 u8 count;
3810 u64 map = 0;
3811
3812 if (map_len == 0) {
3813
3814 hdmi->y420_cmdb_map = U64_MAX;
3815 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3816 return;
3817 }
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831 if (WARN_ON_ONCE(map_len > 8))
3832 map_len = 8;
3833
3834 for (count = 0; count < map_len; count++)
3835 map |= (u64)db[2 + count] << (8 * count);
3836
3837 if (map)
3838 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3839
3840 hdmi->y420_cmdb_map = map;
3841}
3842
3843static int
3844add_cea_modes(struct drm_connector *connector, struct edid *edid)
3845{
3846 const u8 *cea = drm_find_cea_extension(edid);
3847 const u8 *db, *hdmi = NULL, *video = NULL;
3848 u8 dbl, hdmi_len, video_len = 0;
3849 int modes = 0;
3850
3851 if (cea && cea_revision(cea) >= 3) {
3852 int i, start, end;
3853
3854 if (cea_db_offsets(cea, &start, &end))
3855 return 0;
3856
3857 for_each_cea_db(cea, i, start, end) {
3858 db = &cea[i];
3859 dbl = cea_db_payload_len(db);
3860
3861 if (cea_db_tag(db) == VIDEO_BLOCK) {
3862 video = db + 1;
3863 video_len = dbl;
3864 modes += do_cea_modes(connector, video, dbl);
3865 } else if (cea_db_is_hdmi_vsdb(db)) {
3866 hdmi = db;
3867 hdmi_len = dbl;
3868 } else if (cea_db_is_y420vdb(db)) {
3869 const u8 *vdb420 = &db[2];
3870
3871
3872 modes += do_y420vdb_modes(connector,
3873 vdb420,
3874 dbl - 1);
3875 }
3876 }
3877 }
3878
3879
3880
3881
3882
3883 if (hdmi)
3884 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3885 video_len);
3886
3887 return modes;
3888}
3889
3890static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3891{
3892 const struct drm_display_mode *cea_mode;
3893 int clock1, clock2, clock;
3894 u8 vic;
3895 const char *type;
3896
3897
3898
3899
3900
3901 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3902 if (drm_valid_cea_vic(vic)) {
3903 type = "CEA";
3904 cea_mode = &edid_cea_modes[vic];
3905 clock1 = cea_mode->clock;
3906 clock2 = cea_mode_alternate_clock(cea_mode);
3907 } else {
3908 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3909 if (drm_valid_hdmi_vic(vic)) {
3910 type = "HDMI";
3911 cea_mode = &edid_4k_modes[vic];
3912 clock1 = cea_mode->clock;
3913 clock2 = hdmi_mode_alternate_clock(cea_mode);
3914 } else {
3915 return;
3916 }
3917 }
3918
3919
3920 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3921 clock = clock1;
3922 else
3923 clock = clock2;
3924
3925 if (mode->clock == clock)
3926 return;
3927
3928 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3929 type, vic, mode->clock, clock);
3930 mode->clock = clock;
3931}
3932
3933static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
3934{
3935 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3936 return false;
3937
3938 if (db[1] != HDR_STATIC_METADATA_BLOCK)
3939 return false;
3940
3941 if (cea_db_payload_len(db) < 3)
3942 return false;
3943
3944 return true;
3945}
3946
3947static uint8_t eotf_supported(const u8 *edid_ext)
3948{
3949 return edid_ext[2] &
3950 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
3951 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
3952 BIT(HDMI_EOTF_SMPTE_ST2084) |
3953 BIT(HDMI_EOTF_BT_2100_HLG));
3954}
3955
3956static uint8_t hdr_metadata_type(const u8 *edid_ext)
3957{
3958 return edid_ext[3] &
3959 BIT(HDMI_STATIC_METADATA_TYPE1);
3960}
3961
3962static void
3963drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
3964{
3965 u16 len;
3966
3967 len = cea_db_payload_len(db);
3968
3969 connector->hdr_sink_metadata.hdmi_type1.eotf =
3970 eotf_supported(db);
3971 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
3972 hdr_metadata_type(db);
3973
3974 if (len >= 4)
3975 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
3976 if (len >= 5)
3977 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
3978 if (len >= 6)
3979 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
3980}
3981
3982static void
3983drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3984{
3985 u8 len = cea_db_payload_len(db);
3986
3987 if (len >= 6 && (db[6] & (1 << 7)))
3988 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3989 if (len >= 8) {
3990 connector->latency_present[0] = db[8] >> 7;
3991 connector->latency_present[1] = (db[8] >> 6) & 1;
3992 }
3993 if (len >= 9)
3994 connector->video_latency[0] = db[9];
3995 if (len >= 10)
3996 connector->audio_latency[0] = db[10];
3997 if (len >= 11)
3998 connector->video_latency[1] = db[11];
3999 if (len >= 12)
4000 connector->audio_latency[1] = db[12];
4001
4002 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4003 "video latency %d %d, "
4004 "audio latency %d %d\n",
4005 connector->latency_present[0],
4006 connector->latency_present[1],
4007 connector->video_latency[0],
4008 connector->video_latency[1],
4009 connector->audio_latency[0],
4010 connector->audio_latency[1]);
4011}
4012
4013static void
4014monitor_name(struct detailed_timing *t, void *data)
4015{
4016 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4017 *(u8 **)data = t->data.other_data.data.str.str;
4018}
4019
4020static int get_monitor_name(struct edid *edid, char name[13])
4021{
4022 char *edid_name = NULL;
4023 int mnl;
4024
4025 if (!edid || !name)
4026 return 0;
4027
4028 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4029 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4030 if (edid_name[mnl] == 0x0a)
4031 break;
4032
4033 name[mnl] = edid_name[mnl];
4034 }
4035
4036 return mnl;
4037}
4038
4039
4040
4041
4042
4043
4044
4045
4046void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4047{
4048 int name_length;
4049 char buf[13];
4050
4051 if (bufsize <= 0)
4052 return;
4053
4054 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4055 memcpy(name, buf, name_length);
4056 name[name_length] = '\0';
4057}
4058EXPORT_SYMBOL(drm_edid_get_monitor_name);
4059
4060static void clear_eld(struct drm_connector *connector)
4061{
4062 memset(connector->eld, 0, sizeof(connector->eld));
4063
4064 connector->latency_present[0] = false;
4065 connector->latency_present[1] = false;
4066 connector->video_latency[0] = 0;
4067 connector->audio_latency[0] = 0;
4068 connector->video_latency[1] = 0;
4069 connector->audio_latency[1] = 0;
4070}
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4081{
4082 uint8_t *eld = connector->eld;
4083 u8 *cea;
4084 u8 *db;
4085 int total_sad_count = 0;
4086 int mnl;
4087 int dbl;
4088
4089 clear_eld(connector);
4090
4091 if (!edid)
4092 return;
4093
4094 cea = drm_find_cea_extension(edid);
4095 if (!cea) {
4096 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4097 return;
4098 }
4099
4100 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4101 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4102
4103 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4104 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4105
4106 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4107
4108 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4109 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4110 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4111 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4112
4113 if (cea_revision(cea) >= 3) {
4114 int i, start, end;
4115
4116 if (cea_db_offsets(cea, &start, &end)) {
4117 start = 0;
4118 end = 0;
4119 }
4120
4121 for_each_cea_db(cea, i, start, end) {
4122 db = &cea[i];
4123 dbl = cea_db_payload_len(db);
4124
4125 switch (cea_db_tag(db)) {
4126 int sad_count;
4127
4128 case AUDIO_BLOCK:
4129
4130 sad_count = min(dbl / 3, 15 - total_sad_count);
4131 if (sad_count >= 1)
4132 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4133 &db[1], sad_count * 3);
4134 total_sad_count += sad_count;
4135 break;
4136 case SPEAKER_BLOCK:
4137
4138 if (dbl >= 1)
4139 eld[DRM_ELD_SPEAKER] = db[1];
4140 break;
4141 case VENDOR_BLOCK:
4142
4143 if (cea_db_is_hdmi_vsdb(db))
4144 drm_parse_hdmi_vsdb_audio(connector, db);
4145 break;
4146 default:
4147 break;
4148 }
4149 }
4150 }
4151 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4152
4153 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4154 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4155 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4156 else
4157 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4158
4159 eld[DRM_ELD_BASELINE_ELD_LEN] =
4160 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4161
4162 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4163 drm_eld_size(eld), total_sad_count);
4164}
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4178{
4179 int count = 0;
4180 int i, start, end, dbl;
4181 u8 *cea;
4182
4183 cea = drm_find_cea_extension(edid);
4184 if (!cea) {
4185 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4186 return -ENOENT;
4187 }
4188
4189 if (cea_revision(cea) < 3) {
4190 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4191 return -ENOTSUPP;
4192 }
4193
4194 if (cea_db_offsets(cea, &start, &end)) {
4195 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4196 return -EPROTO;
4197 }
4198
4199 for_each_cea_db(cea, i, start, end) {
4200 u8 *db = &cea[i];
4201
4202 if (cea_db_tag(db) == AUDIO_BLOCK) {
4203 int j;
4204 dbl = cea_db_payload_len(db);
4205
4206 count = dbl / 3;
4207 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4208 if (!*sads)
4209 return -ENOMEM;
4210 for (j = 0; j < count; j++) {
4211 u8 *sad = &db[1 + j * 3];
4212
4213 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4214 (*sads)[j].channels = sad[0] & 0x7;
4215 (*sads)[j].freq = sad[1] & 0x7F;
4216 (*sads)[j].byte2 = sad[2];
4217 }
4218 break;
4219 }
4220 }
4221
4222 return count;
4223}
4224EXPORT_SYMBOL(drm_edid_to_sad);
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4239{
4240 int count = 0;
4241 int i, start, end, dbl;
4242 const u8 *cea;
4243
4244 cea = drm_find_cea_extension(edid);
4245 if (!cea) {
4246 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4247 return -ENOENT;
4248 }
4249
4250 if (cea_revision(cea) < 3) {
4251 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4252 return -ENOTSUPP;
4253 }
4254
4255 if (cea_db_offsets(cea, &start, &end)) {
4256 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4257 return -EPROTO;
4258 }
4259
4260 for_each_cea_db(cea, i, start, end) {
4261 const u8 *db = &cea[i];
4262
4263 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4264 dbl = cea_db_payload_len(db);
4265
4266
4267 if (dbl == 3) {
4268 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4269 if (!*sadb)
4270 return -ENOMEM;
4271 count = dbl;
4272 break;
4273 }
4274 }
4275 }
4276
4277 return count;
4278}
4279EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289int drm_av_sync_delay(struct drm_connector *connector,
4290 const struct drm_display_mode *mode)
4291{
4292 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4293 int a, v;
4294
4295 if (!connector->latency_present[0])
4296 return 0;
4297 if (!connector->latency_present[1])
4298 i = 0;
4299
4300 a = connector->audio_latency[i];
4301 v = connector->video_latency[i];
4302
4303
4304
4305
4306 if (a == 255 || v == 255)
4307 return 0;
4308
4309
4310
4311
4312
4313 if (a)
4314 a = min(2 * (a - 1), 500);
4315 if (v)
4316 v = min(2 * (v - 1), 500);
4317
4318 return max(v - a, 0);
4319}
4320EXPORT_SYMBOL(drm_av_sync_delay);
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330bool drm_detect_hdmi_monitor(struct edid *edid)
4331{
4332 u8 *edid_ext;
4333 int i;
4334 int start_offset, end_offset;
4335
4336 edid_ext = drm_find_cea_extension(edid);
4337 if (!edid_ext)
4338 return false;
4339
4340 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4341 return false;
4342
4343
4344
4345
4346
4347 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4348 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4349 return true;
4350 }
4351
4352 return false;
4353}
4354EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368bool drm_detect_monitor_audio(struct edid *edid)
4369{
4370 u8 *edid_ext;
4371 int i, j;
4372 bool has_audio = false;
4373 int start_offset, end_offset;
4374
4375 edid_ext = drm_find_cea_extension(edid);
4376 if (!edid_ext)
4377 goto end;
4378
4379 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4380
4381 if (has_audio) {
4382 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4383 goto end;
4384 }
4385
4386 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4387 goto end;
4388
4389 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4390 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4391 has_audio = true;
4392 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4393 DRM_DEBUG_KMS("CEA audio format %d\n",
4394 (edid_ext[i + j] >> 3) & 0xf);
4395 goto end;
4396 }
4397 }
4398end:
4399 return has_audio;
4400}
4401EXPORT_SYMBOL(drm_detect_monitor_audio);
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413enum hdmi_quantization_range
4414drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4415{
4416
4417 return drm_match_cea_mode(mode) > 1 ?
4418 HDMI_QUANTIZATION_RANGE_LIMITED :
4419 HDMI_QUANTIZATION_RANGE_FULL;
4420}
4421EXPORT_SYMBOL(drm_default_rgb_quant_range);
4422
4423static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4424{
4425 struct drm_display_info *info = &connector->display_info;
4426
4427 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4428
4429 if (db[2] & EDID_CEA_VCDB_QS)
4430 info->rgb_quant_range_selectable = true;
4431}
4432
4433static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4434 const u8 *db)
4435{
4436 u8 dc_mask;
4437 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4438
4439 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4440 hdmi->y420_dc_modes = dc_mask;
4441}
4442
4443static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4444 const u8 *hf_vsdb)
4445{
4446 struct drm_display_info *display = &connector->display_info;
4447 struct drm_hdmi_info *hdmi = &display->hdmi;
4448
4449 display->has_hdmi_infoframe = true;
4450
4451 if (hf_vsdb[6] & 0x80) {
4452 hdmi->scdc.supported = true;
4453 if (hf_vsdb[6] & 0x40)
4454 hdmi->scdc.read_request = true;
4455 }
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466 if (hf_vsdb[5]) {
4467
4468 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4469 struct drm_scdc *scdc = &hdmi->scdc;
4470
4471 if (max_tmds_clock > 340000) {
4472 display->max_tmds_clock = max_tmds_clock;
4473 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4474 display->max_tmds_clock);
4475 }
4476
4477 if (scdc->supported) {
4478 scdc->scrambling.supported = true;
4479
4480
4481 if ((hf_vsdb[6] & 0x8))
4482 scdc->scrambling.low_rates = true;
4483 }
4484 }
4485
4486 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4487}
4488
4489static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4490 const u8 *hdmi)
4491{
4492 struct drm_display_info *info = &connector->display_info;
4493 unsigned int dc_bpc = 0;
4494
4495
4496 info->bpc = 8;
4497
4498 if (cea_db_payload_len(hdmi) < 6)
4499 return;
4500
4501 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4502 dc_bpc = 10;
4503 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4504 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4505 connector->name);
4506 }
4507
4508 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4509 dc_bpc = 12;
4510 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4511 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4512 connector->name);
4513 }
4514
4515 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4516 dc_bpc = 16;
4517 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4518 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4519 connector->name);
4520 }
4521
4522 if (dc_bpc == 0) {
4523 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4524 connector->name);
4525 return;
4526 }
4527
4528 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4529 connector->name, dc_bpc);
4530 info->bpc = dc_bpc;
4531
4532
4533
4534
4535
4536
4537 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4538
4539
4540 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4541 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4542 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4543 connector->name);
4544 }
4545
4546
4547
4548
4549
4550 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4551 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4552 connector->name);
4553 }
4554}
4555
4556static void
4557drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4558{
4559 struct drm_display_info *info = &connector->display_info;
4560 u8 len = cea_db_payload_len(db);
4561
4562 if (len >= 6)
4563 info->dvi_dual = db[6] & 1;
4564 if (len >= 7)
4565 info->max_tmds_clock = db[7] * 5000;
4566
4567 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4568 "max TMDS clock %d kHz\n",
4569 info->dvi_dual,
4570 info->max_tmds_clock);
4571
4572 drm_parse_hdmi_deep_color_info(connector, db);
4573}
4574
4575static void drm_parse_cea_ext(struct drm_connector *connector,
4576 const struct edid *edid)
4577{
4578 struct drm_display_info *info = &connector->display_info;
4579 const u8 *edid_ext;
4580 int i, start, end;
4581
4582 edid_ext = drm_find_cea_extension(edid);
4583 if (!edid_ext)
4584 return;
4585
4586 info->cea_rev = edid_ext[1];
4587
4588
4589 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4590 if (edid_ext[3] & EDID_CEA_YCRCB444)
4591 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4592 if (edid_ext[3] & EDID_CEA_YCRCB422)
4593 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4594
4595 if (cea_db_offsets(edid_ext, &start, &end))
4596 return;
4597
4598 for_each_cea_db(edid_ext, i, start, end) {
4599 const u8 *db = &edid_ext[i];
4600
4601 if (cea_db_is_hdmi_vsdb(db))
4602 drm_parse_hdmi_vsdb_video(connector, db);
4603 if (cea_db_is_hdmi_forum_vsdb(db))
4604 drm_parse_hdmi_forum_vsdb(connector, db);
4605 if (cea_db_is_y420cmdb(db))
4606 drm_parse_y420cmdb_bitmap(connector, db);
4607 if (cea_db_is_vcdb(db))
4608 drm_parse_vcdb(connector, db);
4609 if (cea_db_is_hdmi_hdr_metadata_block(db))
4610 drm_parse_hdr_metadata_block(connector, db);
4611 }
4612}
4613
4614
4615
4616
4617void
4618drm_reset_display_info(struct drm_connector *connector)
4619{
4620 struct drm_display_info *info = &connector->display_info;
4621
4622 info->width_mm = 0;
4623 info->height_mm = 0;
4624
4625 info->bpc = 0;
4626 info->color_formats = 0;
4627 info->cea_rev = 0;
4628 info->max_tmds_clock = 0;
4629 info->dvi_dual = false;
4630 info->has_hdmi_infoframe = false;
4631 info->rgb_quant_range_selectable = false;
4632 memset(&info->hdmi, 0, sizeof(info->hdmi));
4633
4634 info->non_desktop = 0;
4635}
4636
4637u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4638{
4639 struct drm_display_info *info = &connector->display_info;
4640
4641 u32 quirks = edid_get_quirks(edid);
4642
4643 drm_reset_display_info(connector);
4644
4645 info->width_mm = edid->width_cm * 10;
4646 info->height_mm = edid->height_cm * 10;
4647
4648 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4649
4650 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4651
4652 if (edid->revision < 3)
4653 return quirks;
4654
4655 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4656 return quirks;
4657
4658 drm_parse_cea_ext(connector, edid);
4659
4660
4661
4662
4663
4664
4665
4666
4667 if (info->bpc == 0 && edid->revision == 3 &&
4668 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4669 info->bpc = 8;
4670 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4671 connector->name, info->bpc);
4672 }
4673
4674
4675 if (edid->revision < 4)
4676 return quirks;
4677
4678 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4679 case DRM_EDID_DIGITAL_DEPTH_6:
4680 info->bpc = 6;
4681 break;
4682 case DRM_EDID_DIGITAL_DEPTH_8:
4683 info->bpc = 8;
4684 break;
4685 case DRM_EDID_DIGITAL_DEPTH_10:
4686 info->bpc = 10;
4687 break;
4688 case DRM_EDID_DIGITAL_DEPTH_12:
4689 info->bpc = 12;
4690 break;
4691 case DRM_EDID_DIGITAL_DEPTH_14:
4692 info->bpc = 14;
4693 break;
4694 case DRM_EDID_DIGITAL_DEPTH_16:
4695 info->bpc = 16;
4696 break;
4697 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4698 default:
4699 info->bpc = 0;
4700 break;
4701 }
4702
4703 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4704 connector->name, info->bpc);
4705
4706 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4707 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4708 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4709 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4710 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4711 return quirks;
4712}
4713
4714static int validate_displayid(u8 *displayid, int length, int idx)
4715{
4716 int i;
4717 u8 csum = 0;
4718 struct displayid_hdr *base;
4719
4720 base = (struct displayid_hdr *)&displayid[idx];
4721
4722 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4723 base->rev, base->bytes, base->prod_id, base->ext_count);
4724
4725 if (base->bytes + 5 > length - idx)
4726 return -EINVAL;
4727 for (i = idx; i <= base->bytes + 5; i++) {
4728 csum += displayid[i];
4729 }
4730 if (csum) {
4731 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4732 return -EINVAL;
4733 }
4734 return 0;
4735}
4736
4737static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4738 struct displayid_detailed_timings_1 *timings)
4739{
4740 struct drm_display_mode *mode;
4741 unsigned pixel_clock = (timings->pixel_clock[0] |
4742 (timings->pixel_clock[1] << 8) |
4743 (timings->pixel_clock[2] << 16));
4744 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4745 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4746 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4747 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4748 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4749 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4750 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4751 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4752 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4753 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4754 mode = drm_mode_create(dev);
4755 if (!mode)
4756 return NULL;
4757
4758 mode->clock = pixel_clock * 10;
4759 mode->hdisplay = hactive;
4760 mode->hsync_start = mode->hdisplay + hsync;
4761 mode->hsync_end = mode->hsync_start + hsync_width;
4762 mode->htotal = mode->hdisplay + hblank;
4763
4764 mode->vdisplay = vactive;
4765 mode->vsync_start = mode->vdisplay + vsync;
4766 mode->vsync_end = mode->vsync_start + vsync_width;
4767 mode->vtotal = mode->vdisplay + vblank;
4768
4769 mode->flags = 0;
4770 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4771 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4772 mode->type = DRM_MODE_TYPE_DRIVER;
4773
4774 if (timings->flags & 0x80)
4775 mode->type |= DRM_MODE_TYPE_PREFERRED;
4776 mode->vrefresh = drm_mode_vrefresh(mode);
4777 drm_mode_set_name(mode);
4778
4779 return mode;
4780}
4781
4782static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4783 struct displayid_block *block)
4784{
4785 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4786 int i;
4787 int num_timings;
4788 struct drm_display_mode *newmode;
4789 int num_modes = 0;
4790
4791 if (block->num_bytes % 20)
4792 return 0;
4793
4794 num_timings = block->num_bytes / 20;
4795 for (i = 0; i < num_timings; i++) {
4796 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4797
4798 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4799 if (!newmode)
4800 continue;
4801
4802 drm_mode_probed_add(connector, newmode);
4803 num_modes++;
4804 }
4805 return num_modes;
4806}
4807
4808static int add_displayid_detailed_modes(struct drm_connector *connector,
4809 struct edid *edid)
4810{
4811 u8 *displayid;
4812 int ret;
4813 int idx = 1;
4814 int length = EDID_LENGTH;
4815 struct displayid_block *block;
4816 int num_modes = 0;
4817
4818 displayid = drm_find_displayid_extension(edid);
4819 if (!displayid)
4820 return 0;
4821
4822 ret = validate_displayid(displayid, length, idx);
4823 if (ret)
4824 return 0;
4825
4826 idx += sizeof(struct displayid_hdr);
4827 for_each_displayid_db(displayid, block, idx, length) {
4828 switch (block->tag) {
4829 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4830 num_modes += add_displayid_detailed_1_modes(connector, block);
4831 break;
4832 }
4833 }
4834 return num_modes;
4835}
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4849{
4850 int num_modes = 0;
4851 u32 quirks;
4852
4853 if (edid == NULL) {
4854 clear_eld(connector);
4855 return 0;
4856 }
4857 if (!drm_edid_is_valid(edid)) {
4858 clear_eld(connector);
4859 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4860 connector->name);
4861 return 0;
4862 }
4863
4864 drm_edid_to_eld(connector, edid);
4865
4866
4867
4868
4869
4870
4871 quirks = drm_add_display_info(connector, edid);
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887 num_modes += add_detailed_modes(connector, edid, quirks);
4888 num_modes += add_cvt_modes(connector, edid);
4889 num_modes += add_standard_modes(connector, edid);
4890 num_modes += add_established_modes(connector, edid);
4891 num_modes += add_cea_modes(connector, edid);
4892 num_modes += add_alternate_cea_modes(connector, edid);
4893 num_modes += add_displayid_detailed_modes(connector, edid);
4894 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4895 num_modes += add_inferred_modes(connector, edid);
4896
4897 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4898 edid_fixup_preferred(connector, quirks);
4899
4900 if (quirks & EDID_QUIRK_FORCE_6BPC)
4901 connector->display_info.bpc = 6;
4902
4903 if (quirks & EDID_QUIRK_FORCE_8BPC)
4904 connector->display_info.bpc = 8;
4905
4906 if (quirks & EDID_QUIRK_FORCE_10BPC)
4907 connector->display_info.bpc = 10;
4908
4909 if (quirks & EDID_QUIRK_FORCE_12BPC)
4910 connector->display_info.bpc = 12;
4911
4912 return num_modes;
4913}
4914EXPORT_SYMBOL(drm_add_edid_modes);
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927int drm_add_modes_noedid(struct drm_connector *connector,
4928 int hdisplay, int vdisplay)
4929{
4930 int i, count, num_modes = 0;
4931 struct drm_display_mode *mode;
4932 struct drm_device *dev = connector->dev;
4933
4934 count = ARRAY_SIZE(drm_dmt_modes);
4935 if (hdisplay < 0)
4936 hdisplay = 0;
4937 if (vdisplay < 0)
4938 vdisplay = 0;
4939
4940 for (i = 0; i < count; i++) {
4941 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4942 if (hdisplay && vdisplay) {
4943
4944
4945
4946
4947
4948 if (ptr->hdisplay > hdisplay ||
4949 ptr->vdisplay > vdisplay)
4950 continue;
4951 }
4952 if (drm_mode_vrefresh(ptr) > 61)
4953 continue;
4954 mode = drm_mode_duplicate(dev, ptr);
4955 if (mode) {
4956 drm_mode_probed_add(connector, mode);
4957 num_modes++;
4958 }
4959 }
4960 return num_modes;
4961}
4962EXPORT_SYMBOL(drm_add_modes_noedid);
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973void drm_set_preferred_mode(struct drm_connector *connector,
4974 int hpref, int vpref)
4975{
4976 struct drm_display_mode *mode;
4977
4978 list_for_each_entry(mode, &connector->probed_modes, head) {
4979 if (mode->hdisplay == hpref &&
4980 mode->vdisplay == vpref)
4981 mode->type |= DRM_MODE_TYPE_PREFERRED;
4982 }
4983}
4984EXPORT_SYMBOL(drm_set_preferred_mode);
4985
4986static bool is_hdmi2_sink(struct drm_connector *connector)
4987{
4988
4989
4990
4991
4992 if (!connector)
4993 return true;
4994
4995 return connector->display_info.hdmi.scdc.supported ||
4996 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
4997}
4998
4999static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5000{
5001 return sink_eotf & BIT(output_eotf);
5002}
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012int
5013drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5014 const struct drm_connector_state *conn_state)
5015{
5016 struct drm_connector *connector;
5017 struct hdr_output_metadata *hdr_metadata;
5018 int err;
5019
5020 if (!frame || !conn_state)
5021 return -EINVAL;
5022
5023 connector = conn_state->connector;
5024
5025 if (!conn_state->hdr_output_metadata)
5026 return -EINVAL;
5027
5028 hdr_metadata = conn_state->hdr_output_metadata->data;
5029
5030 if (!hdr_metadata || !connector)
5031 return -EINVAL;
5032
5033
5034 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5035 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5036 DRM_DEBUG_KMS("EOTF Not Supported\n");
5037 return -EINVAL;
5038 }
5039
5040 err = hdmi_drm_infoframe_init(frame);
5041 if (err < 0)
5042 return err;
5043
5044 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5045 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5046
5047 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5048 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5049 BUILD_BUG_ON(sizeof(frame->white_point) !=
5050 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5051
5052 memcpy(&frame->display_primaries,
5053 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5054 sizeof(frame->display_primaries));
5055
5056 memcpy(&frame->white_point,
5057 &hdr_metadata->hdmi_metadata_type1.white_point,
5058 sizeof(frame->white_point));
5059
5060 frame->max_display_mastering_luminance =
5061 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5062 frame->min_display_mastering_luminance =
5063 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5064 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5065 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5066
5067 return 0;
5068}
5069EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080int
5081drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5082 struct drm_connector *connector,
5083 const struct drm_display_mode *mode)
5084{
5085 enum hdmi_picture_aspect picture_aspect;
5086 int err;
5087
5088 if (!frame || !mode)
5089 return -EINVAL;
5090
5091 err = hdmi_avi_infoframe_init(frame);
5092 if (err < 0)
5093 return err;
5094
5095 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5096 frame->pixel_repeat = 1;
5097
5098 frame->video_code = drm_match_cea_mode(mode);
5099
5100
5101
5102
5103
5104
5105 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
5106 frame->video_code = 0;
5107
5108
5109
5110
5111
5112
5113
5114 if (frame->video_code) {
5115 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
5116 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
5117
5118 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
5119 frame->video_code = 0;
5120 }
5121
5122 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5123
5124
5125
5126
5127
5128
5129 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5130 frame->itc = 0;
5131
5132
5133
5134
5135
5136 picture_aspect = mode->picture_aspect_ratio;
5137 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
5138 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
5139
5140
5141
5142
5143
5144
5145 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5146 if (picture_aspect !=
5147 drm_get_cea_aspect_ratio(frame->video_code))
5148 return -EINVAL;
5149 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5150 }
5151
5152 frame->picture_aspect = picture_aspect;
5153 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5154 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5155
5156 return 0;
5157}
5158EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5159
5160
5161#define FULL_COLORIMETRY_MASK 0x1FF
5162#define NORMAL_COLORIMETRY_MASK 0x3
5163#define EXTENDED_COLORIMETRY_MASK 0x7
5164#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5165
5166#define C(x) ((x) << 0)
5167#define EC(x) ((x) << 2)
5168#define ACE(x) ((x) << 5)
5169
5170#define HDMI_COLORIMETRY_NO_DATA 0x0
5171#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5172#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5173#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5174#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5175#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5176#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5177#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5178#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5179#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5180#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5181#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5182#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5183
5184static const u32 hdmi_colorimetry_val[] = {
5185 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5186 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5187 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5188 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5189 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5190 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5191 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5192 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5193 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5194 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5195 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5196};
5197
5198#undef C
5199#undef EC
5200#undef ACE
5201
5202
5203
5204
5205
5206
5207
5208void
5209drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5210 const struct drm_connector_state *conn_state)
5211{
5212 u32 colorimetry_val;
5213 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5214
5215 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5216 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5217 else
5218 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5219
5220 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5221
5222
5223
5224
5225 frame->extended_colorimetry = (colorimetry_val >> 2) &
5226 EXTENDED_COLORIMETRY_MASK;
5227}
5228EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238void
5239drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5240 struct drm_connector *connector,
5241 const struct drm_display_mode *mode,
5242 enum hdmi_quantization_range rgb_quant_range)
5243{
5244 const struct drm_display_info *info = &connector->display_info;
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256 if (info->rgb_quant_range_selectable ||
5257 rgb_quant_range == drm_default_rgb_quant_range(mode))
5258 frame->quantization_range = rgb_quant_range;
5259 else
5260 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275 if (!is_hdmi2_sink(connector) ||
5276 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5277 frame->ycc_quantization_range =
5278 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5279 else
5280 frame->ycc_quantization_range =
5281 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5282}
5283EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5284
5285static enum hdmi_3d_structure
5286s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5287{
5288 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5289
5290 switch (layout) {
5291 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5292 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5293 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5294 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5295 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5296 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5297 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5298 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5299 case DRM_MODE_FLAG_3D_L_DEPTH:
5300 return HDMI_3D_STRUCTURE_L_DEPTH;
5301 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5302 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5303 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5304 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5305 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5306 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5307 default:
5308 return HDMI_3D_STRUCTURE_INVALID;
5309 }
5310}
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325int
5326drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5327 struct drm_connector *connector,
5328 const struct drm_display_mode *mode)
5329{
5330
5331
5332
5333
5334 bool has_hdmi_infoframe = connector ?
5335 connector->display_info.has_hdmi_infoframe : false;
5336 int err;
5337 u32 s3d_flags;
5338 u8 vic;
5339
5340 if (!frame || !mode)
5341 return -EINVAL;
5342
5343 if (!has_hdmi_infoframe)
5344 return -EINVAL;
5345
5346 vic = drm_match_hdmi_mode(mode);
5347 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359 if (vic && s3d_flags)
5360 return -EINVAL;
5361
5362 err = hdmi_vendor_infoframe_init(frame);
5363 if (err < 0)
5364 return err;
5365
5366 frame->vic = vic;
5367 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5368
5369 return 0;
5370}
5371EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5372
5373static int drm_parse_tiled_block(struct drm_connector *connector,
5374 struct displayid_block *block)
5375{
5376 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5377 u16 w, h;
5378 u8 tile_v_loc, tile_h_loc;
5379 u8 num_v_tile, num_h_tile;
5380 struct drm_tile_group *tg;
5381
5382 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5383 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5384
5385 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5386 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5387 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5388 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5389
5390 connector->has_tile = true;
5391 if (tile->tile_cap & 0x80)
5392 connector->tile_is_single_monitor = true;
5393
5394 connector->num_h_tile = num_h_tile + 1;
5395 connector->num_v_tile = num_v_tile + 1;
5396 connector->tile_h_loc = tile_h_loc;
5397 connector->tile_v_loc = tile_v_loc;
5398 connector->tile_h_size = w + 1;
5399 connector->tile_v_size = h + 1;
5400
5401 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5402 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5403 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5404 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5405 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5406
5407 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5408 if (!tg) {
5409 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5410 }
5411 if (!tg)
5412 return -ENOMEM;
5413
5414 if (connector->tile_group != tg) {
5415
5416
5417 if (connector->tile_group) {
5418 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5419 }
5420 connector->tile_group = tg;
5421 } else
5422
5423 drm_mode_put_tile_group(connector->dev, tg);
5424 return 0;
5425}
5426
5427static int drm_parse_display_id(struct drm_connector *connector,
5428 u8 *displayid, int length,
5429 bool is_edid_extension)
5430{
5431
5432 int idx = 0;
5433 struct displayid_block *block;
5434 int ret;
5435
5436 if (is_edid_extension)
5437 idx = 1;
5438
5439 ret = validate_displayid(displayid, length, idx);
5440 if (ret)
5441 return ret;
5442
5443 idx += sizeof(struct displayid_hdr);
5444 for_each_displayid_db(displayid, block, idx, length) {
5445 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5446 block->tag, block->rev, block->num_bytes);
5447
5448 switch (block->tag) {
5449 case DATA_BLOCK_TILED_DISPLAY:
5450 ret = drm_parse_tiled_block(connector, block);
5451 if (ret)
5452 return ret;
5453 break;
5454 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5455
5456 break;
5457 case DATA_BLOCK_CTA:
5458
5459 break;
5460 default:
5461 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5462 break;
5463 }
5464 }
5465 return 0;
5466}
5467
5468static void drm_get_displayid(struct drm_connector *connector,
5469 struct edid *edid)
5470{
5471 void *displayid = NULL;
5472 int ret;
5473 connector->has_tile = false;
5474 displayid = drm_find_displayid_extension(edid);
5475 if (!displayid) {
5476
5477 goto out_drop_ref;
5478 }
5479
5480 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5481 if (ret < 0)
5482 goto out_drop_ref;
5483 if (!connector->has_tile)
5484 goto out_drop_ref;
5485 return;
5486out_drop_ref:
5487 if (connector->tile_group) {
5488 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5489 connector->tile_group = NULL;
5490 }
5491 return;
5492}
5493