1
2
3
4
5
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/dma-fence.h>
9#include <linux/moduleparam.h>
10#include <linux/of_device.h>
11#include <linux/regulator/consumer.h>
12#include <linux/thermal.h>
13
14#include "etnaviv_cmdbuf.h"
15#include "etnaviv_dump.h"
16#include "etnaviv_gpu.h"
17#include "etnaviv_gem.h"
18#include "etnaviv_mmu.h"
19#include "etnaviv_perfmon.h"
20#include "etnaviv_sched.h"
21#include "common.xml.h"
22#include "state.xml.h"
23#include "state_hi.xml.h"
24#include "cmdstream.xml.h"
25
26#ifndef PHYS_OFFSET
27#define PHYS_OFFSET 0
28#endif
29
30static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33};
34
35
36
37
38
39int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40{
41 switch (param) {
42 case ETNAVIV_PARAM_GPU_MODEL:
43 *value = gpu->identity.model;
44 break;
45
46 case ETNAVIV_PARAM_GPU_REVISION:
47 *value = gpu->identity.revision;
48 break;
49
50 case ETNAVIV_PARAM_GPU_FEATURES_0:
51 *value = gpu->identity.features;
52 break;
53
54 case ETNAVIV_PARAM_GPU_FEATURES_1:
55 *value = gpu->identity.minor_features0;
56 break;
57
58 case ETNAVIV_PARAM_GPU_FEATURES_2:
59 *value = gpu->identity.minor_features1;
60 break;
61
62 case ETNAVIV_PARAM_GPU_FEATURES_3:
63 *value = gpu->identity.minor_features2;
64 break;
65
66 case ETNAVIV_PARAM_GPU_FEATURES_4:
67 *value = gpu->identity.minor_features3;
68 break;
69
70 case ETNAVIV_PARAM_GPU_FEATURES_5:
71 *value = gpu->identity.minor_features4;
72 break;
73
74 case ETNAVIV_PARAM_GPU_FEATURES_6:
75 *value = gpu->identity.minor_features5;
76 break;
77
78 case ETNAVIV_PARAM_GPU_FEATURES_7:
79 *value = gpu->identity.minor_features6;
80 break;
81
82 case ETNAVIV_PARAM_GPU_FEATURES_8:
83 *value = gpu->identity.minor_features7;
84 break;
85
86 case ETNAVIV_PARAM_GPU_FEATURES_9:
87 *value = gpu->identity.minor_features8;
88 break;
89
90 case ETNAVIV_PARAM_GPU_FEATURES_10:
91 *value = gpu->identity.minor_features9;
92 break;
93
94 case ETNAVIV_PARAM_GPU_FEATURES_11:
95 *value = gpu->identity.minor_features10;
96 break;
97
98 case ETNAVIV_PARAM_GPU_FEATURES_12:
99 *value = gpu->identity.minor_features11;
100 break;
101
102 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
103 *value = gpu->identity.stream_count;
104 break;
105
106 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
107 *value = gpu->identity.register_max;
108 break;
109
110 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
111 *value = gpu->identity.thread_count;
112 break;
113
114 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
115 *value = gpu->identity.vertex_cache_size;
116 break;
117
118 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
119 *value = gpu->identity.shader_core_count;
120 break;
121
122 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
123 *value = gpu->identity.pixel_pipes;
124 break;
125
126 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
127 *value = gpu->identity.vertex_output_buffer_size;
128 break;
129
130 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
131 *value = gpu->identity.buffer_size;
132 break;
133
134 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
135 *value = gpu->identity.instruction_count;
136 break;
137
138 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
139 *value = gpu->identity.num_constants;
140 break;
141
142 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
143 *value = gpu->identity.varyings_count;
144 break;
145
146 default:
147 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
148 return -EINVAL;
149 }
150
151 return 0;
152}
153
154
155#define etnaviv_is_model_rev(gpu, mod, rev) \
156 ((gpu)->identity.model == chipModel_##mod && \
157 (gpu)->identity.revision == rev)
158#define etnaviv_field(val, field) \
159 (((val) & field##__MASK) >> field##__SHIFT)
160
161static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
162{
163 if (gpu->identity.minor_features0 &
164 chipMinorFeatures0_MORE_MINOR_FEATURES) {
165 u32 specs[4];
166 unsigned int streams;
167
168 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
169 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
170 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
171 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
172
173 gpu->identity.stream_count = etnaviv_field(specs[0],
174 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
175 gpu->identity.register_max = etnaviv_field(specs[0],
176 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
177 gpu->identity.thread_count = etnaviv_field(specs[0],
178 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
179 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
180 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
181 gpu->identity.shader_core_count = etnaviv_field(specs[0],
182 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
183 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
184 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
185 gpu->identity.vertex_output_buffer_size =
186 etnaviv_field(specs[0],
187 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
188
189 gpu->identity.buffer_size = etnaviv_field(specs[1],
190 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
191 gpu->identity.instruction_count = etnaviv_field(specs[1],
192 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
193 gpu->identity.num_constants = etnaviv_field(specs[1],
194 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
195
196 gpu->identity.varyings_count = etnaviv_field(specs[2],
197 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
198
199
200 streams = etnaviv_field(specs[3],
201 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
202 if (streams)
203 gpu->identity.stream_count = streams;
204 }
205
206
207 if (gpu->identity.stream_count == 0) {
208 if (gpu->identity.model >= 0x1000)
209 gpu->identity.stream_count = 4;
210 else
211 gpu->identity.stream_count = 1;
212 }
213
214
215 if (gpu->identity.register_max)
216 gpu->identity.register_max = 1 << gpu->identity.register_max;
217 else if (gpu->identity.model == chipModel_GC400)
218 gpu->identity.register_max = 32;
219 else
220 gpu->identity.register_max = 64;
221
222
223 if (gpu->identity.thread_count)
224 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
225 else if (gpu->identity.model == chipModel_GC400)
226 gpu->identity.thread_count = 64;
227 else if (gpu->identity.model == chipModel_GC500 ||
228 gpu->identity.model == chipModel_GC530)
229 gpu->identity.thread_count = 128;
230 else
231 gpu->identity.thread_count = 256;
232
233 if (gpu->identity.vertex_cache_size == 0)
234 gpu->identity.vertex_cache_size = 8;
235
236 if (gpu->identity.shader_core_count == 0) {
237 if (gpu->identity.model >= 0x1000)
238 gpu->identity.shader_core_count = 2;
239 else
240 gpu->identity.shader_core_count = 1;
241 }
242
243 if (gpu->identity.pixel_pipes == 0)
244 gpu->identity.pixel_pipes = 1;
245
246
247 if (gpu->identity.vertex_output_buffer_size) {
248 gpu->identity.vertex_output_buffer_size =
249 1 << gpu->identity.vertex_output_buffer_size;
250 } else if (gpu->identity.model == chipModel_GC400) {
251 if (gpu->identity.revision < 0x4000)
252 gpu->identity.vertex_output_buffer_size = 512;
253 else if (gpu->identity.revision < 0x4200)
254 gpu->identity.vertex_output_buffer_size = 256;
255 else
256 gpu->identity.vertex_output_buffer_size = 128;
257 } else {
258 gpu->identity.vertex_output_buffer_size = 512;
259 }
260
261 switch (gpu->identity.instruction_count) {
262 case 0:
263 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
264 gpu->identity.model == chipModel_GC880)
265 gpu->identity.instruction_count = 512;
266 else
267 gpu->identity.instruction_count = 256;
268 break;
269
270 case 1:
271 gpu->identity.instruction_count = 1024;
272 break;
273
274 case 2:
275 gpu->identity.instruction_count = 2048;
276 break;
277
278 default:
279 gpu->identity.instruction_count = 256;
280 break;
281 }
282
283 if (gpu->identity.num_constants == 0)
284 gpu->identity.num_constants = 168;
285
286 if (gpu->identity.varyings_count == 0) {
287 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
288 gpu->identity.varyings_count = 12;
289 else
290 gpu->identity.varyings_count = 8;
291 }
292
293
294
295
296
297 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
298 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
299 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
300 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
301 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
302 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
303 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
304 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
305 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
306 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
307 etnaviv_is_model_rev(gpu, GC880, 0x5106))
308 gpu->identity.varyings_count -= 1;
309}
310
311static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
312{
313 u32 chipIdentity;
314
315 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
316
317
318 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
319 gpu->identity.model = chipModel_GC500;
320 gpu->identity.revision = etnaviv_field(chipIdentity,
321 VIVS_HI_CHIP_IDENTITY_REVISION);
322 } else {
323
324 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
325 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
326
327
328
329
330
331
332
333 if ((gpu->identity.model & 0xff00) == 0x0400 &&
334 gpu->identity.model != chipModel_GC420) {
335 gpu->identity.model = gpu->identity.model & 0x0400;
336 }
337
338
339 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
340 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
341 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
342
343 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
344
345
346
347
348 gpu->identity.revision = 0x1051;
349 }
350 }
351
352
353
354
355
356
357
358
359 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
360 gpu->identity.model = chipModel_GC3000;
361 gpu->identity.revision &= 0xffff;
362 }
363 }
364
365 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
366 gpu->identity.model, gpu->identity.revision);
367
368 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
369
370
371
372
373 if (etnaviv_fill_identity_from_hwdb(gpu))
374 return;
375
376 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
377
378
379 if (gpu->identity.model == chipModel_GC700)
380 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
381
382 if ((gpu->identity.model == chipModel_GC500 &&
383 gpu->identity.revision < 2) ||
384 (gpu->identity.model == chipModel_GC300 &&
385 gpu->identity.revision < 0x2000)) {
386
387
388
389
390
391 gpu->identity.minor_features0 = 0;
392 gpu->identity.minor_features1 = 0;
393 gpu->identity.minor_features2 = 0;
394 gpu->identity.minor_features3 = 0;
395 gpu->identity.minor_features4 = 0;
396 gpu->identity.minor_features5 = 0;
397 } else
398 gpu->identity.minor_features0 =
399 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
400
401 if (gpu->identity.minor_features0 &
402 chipMinorFeatures0_MORE_MINOR_FEATURES) {
403 gpu->identity.minor_features1 =
404 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
405 gpu->identity.minor_features2 =
406 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
407 gpu->identity.minor_features3 =
408 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
409 gpu->identity.minor_features4 =
410 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
411 gpu->identity.minor_features5 =
412 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
413 }
414
415
416 if (gpu->identity.model == chipModel_GC600)
417 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
418 VIVS_HI_IDLE_STATE_RA |
419 VIVS_HI_IDLE_STATE_SE |
420 VIVS_HI_IDLE_STATE_PA |
421 VIVS_HI_IDLE_STATE_SH |
422 VIVS_HI_IDLE_STATE_PE |
423 VIVS_HI_IDLE_STATE_DE |
424 VIVS_HI_IDLE_STATE_FE;
425
426 etnaviv_hw_specs(gpu);
427}
428
429static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
430{
431 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
432 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
433 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
434}
435
436static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
437{
438 if (gpu->identity.minor_features2 &
439 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
440 clk_set_rate(gpu->clk_core,
441 gpu->base_rate_core >> gpu->freq_scale);
442 clk_set_rate(gpu->clk_shader,
443 gpu->base_rate_shader >> gpu->freq_scale);
444 } else {
445 unsigned int fscale = 1 << (6 - gpu->freq_scale);
446 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
447
448 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
449 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
450 etnaviv_gpu_load_clock(gpu, clock);
451 }
452}
453
454static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
455{
456 u32 control, idle;
457 unsigned long timeout;
458 bool failed = true;
459
460
461 timeout = jiffies + msecs_to_jiffies(1000);
462
463 while (time_is_after_jiffies(timeout)) {
464
465 unsigned int fscale = 1 << (6 - gpu->freq_scale);
466 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
467 etnaviv_gpu_load_clock(gpu, control);
468
469
470 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
471 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
472
473 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
474 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
475 VIVS_MMUv2_AHB_CONTROL_RESET);
476 } else {
477
478 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
480 }
481
482
483 usleep_range(10, 20);
484
485
486 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
487 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
488
489
490 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
491 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
492
493
494 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
495
496
497 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
498 dev_dbg(gpu->dev, "FE is not idle\n");
499 continue;
500 }
501
502
503 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
504
505
506 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
507 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
508 dev_dbg(gpu->dev, "GPU is not idle\n");
509 continue;
510 }
511
512
513 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
514 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
515
516 failed = false;
517 break;
518 }
519
520 if (failed) {
521 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
522 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
523
524 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
525 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
526 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
527 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
528
529 return -EBUSY;
530 }
531
532
533 etnaviv_gpu_update_clock(gpu);
534
535 return 0;
536}
537
538static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
539{
540 u32 pmc, ppc;
541
542
543 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
544 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
545
546
547 if (gpu->identity.revision == 0x4301 ||
548 gpu->identity.revision == 0x4302)
549 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
550
551 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
552
553 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
554
555
556 if (gpu->identity.model >= chipModel_GC400 &&
557 gpu->identity.model != chipModel_GC420 &&
558 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
559 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
560
561
562
563
564
565 if (gpu->identity.revision < 0x5000 &&
566 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
567 !(gpu->identity.minor_features1 &
568 chipMinorFeatures1_DISABLE_PE_GATING))
569 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
570
571 if (gpu->identity.revision < 0x5422)
572 pmc |= BIT(15);
573
574
575 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
576 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
577 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
578
579 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
580 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
581
582 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
583}
584
585void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
586{
587 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
588 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
589 VIVS_FE_COMMAND_CONTROL_ENABLE |
590 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
591
592 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
593 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
594 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
595 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
596 }
597}
598
599static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
600{
601
602
603
604
605 u32 pulse_eater = 0x01590880;
606
607 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
608 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
609 pulse_eater |= BIT(23);
610
611 }
612
613 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
614 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
615 pulse_eater &= ~BIT(16);
616 pulse_eater |= BIT(17);
617 }
618
619 if ((gpu->identity.revision > 0x5420) &&
620 (gpu->identity.features & chipFeatures_PIPE_3D))
621 {
622
623 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
624 pulse_eater |= BIT(18);
625 }
626
627 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
628}
629
630static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
631{
632 u16 prefetch;
633
634 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
635 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
636 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
637 u32 mc_memory_debug;
638
639 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
640
641 if (gpu->identity.revision == 0x5007)
642 mc_memory_debug |= 0x0c;
643 else
644 mc_memory_debug |= 0x08;
645
646 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
647 }
648
649
650 etnaviv_gpu_enable_mlcg(gpu);
651
652
653
654
655
656 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
657 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
658 VIVS_HI_AXI_CONFIG_ARCACHE(2));
659
660
661 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
662 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
663 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
664 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
665 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
666 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
667 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
668 }
669
670 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
671 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
672 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
673 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
674 }
675
676
677 etnaviv_gpu_setup_pulse_eater(gpu);
678
679
680 etnaviv_iommu_restore(gpu);
681
682
683 prefetch = etnaviv_buffer_init(gpu);
684
685 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
686 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
687 prefetch);
688}
689
690int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
691{
692 int ret, i;
693
694 ret = pm_runtime_get_sync(gpu->dev);
695 if (ret < 0) {
696 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
697 return ret;
698 }
699
700 etnaviv_hw_identify(gpu);
701
702 if (gpu->identity.model == 0) {
703 dev_err(gpu->dev, "Unknown GPU model\n");
704 ret = -ENXIO;
705 goto fail;
706 }
707
708
709 if (gpu->identity.features & chipFeatures_PIPE_VG &&
710 gpu->identity.features & chipFeatures_FE20) {
711 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
712 ret = -ENXIO;
713 goto fail;
714 }
715
716
717
718
719
720
721
722
723
724
725 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
726 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
727 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
728 if (dma_mask < PHYS_OFFSET + SZ_2G)
729 gpu->memory_base = PHYS_OFFSET;
730 else
731 gpu->memory_base = dma_mask - SZ_2G + 1;
732 } else if (PHYS_OFFSET >= SZ_2G) {
733 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
734 gpu->memory_base = PHYS_OFFSET;
735 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
736 }
737
738
739
740
741
742 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
743 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
744 gpu->sec_mode = ETNA_SEC_KERNEL;
745
746 ret = etnaviv_hw_reset(gpu);
747 if (ret) {
748 dev_err(gpu->dev, "GPU reset failed\n");
749 goto fail;
750 }
751
752 gpu->mmu = etnaviv_iommu_new(gpu);
753 if (IS_ERR(gpu->mmu)) {
754 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
755 ret = PTR_ERR(gpu->mmu);
756 goto fail;
757 }
758
759 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
760 if (IS_ERR(gpu->cmdbuf_suballoc)) {
761 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
762 ret = PTR_ERR(gpu->cmdbuf_suballoc);
763 goto destroy_iommu;
764 }
765
766
767 ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
768 PAGE_SIZE);
769 if (ret) {
770 dev_err(gpu->dev, "could not create command buffer\n");
771 goto destroy_suballoc;
772 }
773
774 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
775 etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
776 ret = -EINVAL;
777 dev_err(gpu->dev,
778 "command buffer outside valid memory window\n");
779 goto free_buffer;
780 }
781
782
783 spin_lock_init(&gpu->event_spinlock);
784 init_completion(&gpu->event_free);
785 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
786 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
787 complete(&gpu->event_free);
788
789
790 mutex_lock(&gpu->lock);
791 etnaviv_gpu_hw_init(gpu);
792 gpu->exec_state = -1;
793 mutex_unlock(&gpu->lock);
794
795 pm_runtime_mark_last_busy(gpu->dev);
796 pm_runtime_put_autosuspend(gpu->dev);
797
798 return 0;
799
800free_buffer:
801 etnaviv_cmdbuf_free(&gpu->buffer);
802 gpu->buffer.suballoc = NULL;
803destroy_suballoc:
804 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
805 gpu->cmdbuf_suballoc = NULL;
806destroy_iommu:
807 etnaviv_iommu_destroy(gpu->mmu);
808 gpu->mmu = NULL;
809fail:
810 pm_runtime_mark_last_busy(gpu->dev);
811 pm_runtime_put_autosuspend(gpu->dev);
812
813 return ret;
814}
815
816#ifdef CONFIG_DEBUG_FS
817struct dma_debug {
818 u32 address[2];
819 u32 state[2];
820};
821
822static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
823{
824 u32 i;
825
826 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
827 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
828
829 for (i = 0; i < 500; i++) {
830 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
831 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
832
833 if (debug->address[0] != debug->address[1])
834 break;
835
836 if (debug->state[0] != debug->state[1])
837 break;
838 }
839}
840
841int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
842{
843 struct dma_debug debug;
844 u32 dma_lo, dma_hi, axi, idle;
845 int ret;
846
847 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
848
849 ret = pm_runtime_get_sync(gpu->dev);
850 if (ret < 0)
851 return ret;
852
853 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
854 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
855 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
856 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
857
858 verify_dma(gpu, &debug);
859
860 seq_puts(m, "\tfeatures\n");
861 seq_printf(m, "\t major_features: 0x%08x\n",
862 gpu->identity.features);
863 seq_printf(m, "\t minor_features0: 0x%08x\n",
864 gpu->identity.minor_features0);
865 seq_printf(m, "\t minor_features1: 0x%08x\n",
866 gpu->identity.minor_features1);
867 seq_printf(m, "\t minor_features2: 0x%08x\n",
868 gpu->identity.minor_features2);
869 seq_printf(m, "\t minor_features3: 0x%08x\n",
870 gpu->identity.minor_features3);
871 seq_printf(m, "\t minor_features4: 0x%08x\n",
872 gpu->identity.minor_features4);
873 seq_printf(m, "\t minor_features5: 0x%08x\n",
874 gpu->identity.minor_features5);
875 seq_printf(m, "\t minor_features6: 0x%08x\n",
876 gpu->identity.minor_features6);
877 seq_printf(m, "\t minor_features7: 0x%08x\n",
878 gpu->identity.minor_features7);
879 seq_printf(m, "\t minor_features8: 0x%08x\n",
880 gpu->identity.minor_features8);
881 seq_printf(m, "\t minor_features9: 0x%08x\n",
882 gpu->identity.minor_features9);
883 seq_printf(m, "\t minor_features10: 0x%08x\n",
884 gpu->identity.minor_features10);
885 seq_printf(m, "\t minor_features11: 0x%08x\n",
886 gpu->identity.minor_features11);
887
888 seq_puts(m, "\tspecs\n");
889 seq_printf(m, "\t stream_count: %d\n",
890 gpu->identity.stream_count);
891 seq_printf(m, "\t register_max: %d\n",
892 gpu->identity.register_max);
893 seq_printf(m, "\t thread_count: %d\n",
894 gpu->identity.thread_count);
895 seq_printf(m, "\t vertex_cache_size: %d\n",
896 gpu->identity.vertex_cache_size);
897 seq_printf(m, "\t shader_core_count: %d\n",
898 gpu->identity.shader_core_count);
899 seq_printf(m, "\t pixel_pipes: %d\n",
900 gpu->identity.pixel_pipes);
901 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
902 gpu->identity.vertex_output_buffer_size);
903 seq_printf(m, "\t buffer_size: %d\n",
904 gpu->identity.buffer_size);
905 seq_printf(m, "\t instruction_count: %d\n",
906 gpu->identity.instruction_count);
907 seq_printf(m, "\t num_constants: %d\n",
908 gpu->identity.num_constants);
909 seq_printf(m, "\t varyings_count: %d\n",
910 gpu->identity.varyings_count);
911
912 seq_printf(m, "\taxi: 0x%08x\n", axi);
913 seq_printf(m, "\tidle: 0x%08x\n", idle);
914 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
915 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
916 seq_puts(m, "\t FE is not idle\n");
917 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
918 seq_puts(m, "\t DE is not idle\n");
919 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
920 seq_puts(m, "\t PE is not idle\n");
921 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
922 seq_puts(m, "\t SH is not idle\n");
923 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
924 seq_puts(m, "\t PA is not idle\n");
925 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
926 seq_puts(m, "\t SE is not idle\n");
927 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
928 seq_puts(m, "\t RA is not idle\n");
929 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
930 seq_puts(m, "\t TX is not idle\n");
931 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
932 seq_puts(m, "\t VG is not idle\n");
933 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
934 seq_puts(m, "\t IM is not idle\n");
935 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
936 seq_puts(m, "\t FP is not idle\n");
937 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
938 seq_puts(m, "\t TS is not idle\n");
939 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
940 seq_puts(m, "\t AXI low power mode\n");
941
942 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
943 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
944 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
945 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
946
947 seq_puts(m, "\tMC\n");
948 seq_printf(m, "\t read0: 0x%08x\n", read0);
949 seq_printf(m, "\t read1: 0x%08x\n", read1);
950 seq_printf(m, "\t write: 0x%08x\n", write);
951 }
952
953 seq_puts(m, "\tDMA ");
954
955 if (debug.address[0] == debug.address[1] &&
956 debug.state[0] == debug.state[1]) {
957 seq_puts(m, "seems to be stuck\n");
958 } else if (debug.address[0] == debug.address[1]) {
959 seq_puts(m, "address is constant\n");
960 } else {
961 seq_puts(m, "is running\n");
962 }
963
964 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
965 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
966 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
967 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
968 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
969 dma_lo, dma_hi);
970
971 ret = 0;
972
973 pm_runtime_mark_last_busy(gpu->dev);
974 pm_runtime_put_autosuspend(gpu->dev);
975
976 return ret;
977}
978#endif
979
980void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
981{
982 unsigned int i = 0;
983
984 dev_err(gpu->dev, "recover hung GPU!\n");
985
986 if (pm_runtime_get_sync(gpu->dev) < 0)
987 return;
988
989 mutex_lock(&gpu->lock);
990
991 etnaviv_hw_reset(gpu);
992
993
994 spin_lock(&gpu->event_spinlock);
995 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
996 complete(&gpu->event_free);
997 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
998 spin_unlock(&gpu->event_spinlock);
999
1000 etnaviv_gpu_hw_init(gpu);
1001 gpu->exec_state = -1;
1002
1003 mutex_unlock(&gpu->lock);
1004 pm_runtime_mark_last_busy(gpu->dev);
1005 pm_runtime_put_autosuspend(gpu->dev);
1006}
1007
1008
1009struct etnaviv_fence {
1010 struct etnaviv_gpu *gpu;
1011 struct dma_fence base;
1012};
1013
1014static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1015{
1016 return container_of(fence, struct etnaviv_fence, base);
1017}
1018
1019static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1020{
1021 return "etnaviv";
1022}
1023
1024static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1025{
1026 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1027
1028 return dev_name(f->gpu->dev);
1029}
1030
1031static bool etnaviv_fence_signaled(struct dma_fence *fence)
1032{
1033 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1034
1035 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1036}
1037
1038static void etnaviv_fence_release(struct dma_fence *fence)
1039{
1040 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1041
1042 kfree_rcu(f, base.rcu);
1043}
1044
1045static const struct dma_fence_ops etnaviv_fence_ops = {
1046 .get_driver_name = etnaviv_fence_get_driver_name,
1047 .get_timeline_name = etnaviv_fence_get_timeline_name,
1048 .signaled = etnaviv_fence_signaled,
1049 .release = etnaviv_fence_release,
1050};
1051
1052static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1053{
1054 struct etnaviv_fence *f;
1055
1056
1057
1058
1059
1060 lockdep_assert_held(&gpu->lock);
1061
1062 f = kzalloc(sizeof(*f), GFP_KERNEL);
1063 if (!f)
1064 return NULL;
1065
1066 f->gpu = gpu;
1067
1068 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1069 gpu->fence_context, ++gpu->next_fence);
1070
1071 return &f->base;
1072}
1073
1074
1075static inline bool fence_after(u32 a, u32 b)
1076{
1077 return (s32)(a - b) > 0;
1078}
1079
1080
1081
1082
1083
1084static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1085 unsigned int *events)
1086{
1087 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1088 unsigned i, acquired = 0;
1089
1090 for (i = 0; i < nr_events; i++) {
1091 unsigned long ret;
1092
1093 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1094
1095 if (!ret) {
1096 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1097 goto out;
1098 }
1099
1100 acquired++;
1101 timeout = ret;
1102 }
1103
1104 spin_lock(&gpu->event_spinlock);
1105
1106 for (i = 0; i < nr_events; i++) {
1107 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1108
1109 events[i] = event;
1110 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1111 set_bit(event, gpu->event_bitmap);
1112 }
1113
1114 spin_unlock(&gpu->event_spinlock);
1115
1116 return 0;
1117
1118out:
1119 for (i = 0; i < acquired; i++)
1120 complete(&gpu->event_free);
1121
1122 return -EBUSY;
1123}
1124
1125static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1126{
1127 if (!test_bit(event, gpu->event_bitmap)) {
1128 dev_warn(gpu->dev, "event %u is already marked as free",
1129 event);
1130 } else {
1131 clear_bit(event, gpu->event_bitmap);
1132 complete(&gpu->event_free);
1133 }
1134}
1135
1136
1137
1138
1139int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1140 u32 id, struct timespec *timeout)
1141{
1142 struct dma_fence *fence;
1143 int ret;
1144
1145
1146
1147
1148
1149
1150 rcu_read_lock();
1151 fence = idr_find(&gpu->fence_idr, id);
1152 if (fence)
1153 fence = dma_fence_get_rcu(fence);
1154 rcu_read_unlock();
1155
1156 if (!fence)
1157 return 0;
1158
1159 if (!timeout) {
1160
1161 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1162 } else {
1163 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1164
1165 ret = dma_fence_wait_timeout(fence, true, remaining);
1166 if (ret == 0)
1167 ret = -ETIMEDOUT;
1168 else if (ret != -ERESTARTSYS)
1169 ret = 0;
1170
1171 }
1172
1173 dma_fence_put(fence);
1174 return ret;
1175}
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1187 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1188{
1189 unsigned long remaining;
1190 long ret;
1191
1192 if (!timeout)
1193 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1194
1195 remaining = etnaviv_timeout_to_jiffies(timeout);
1196
1197 ret = wait_event_interruptible_timeout(gpu->fence_event,
1198 !is_active(etnaviv_obj),
1199 remaining);
1200 if (ret > 0)
1201 return 0;
1202 else if (ret == -ERESTARTSYS)
1203 return -ERESTARTSYS;
1204 else
1205 return -ETIMEDOUT;
1206}
1207
1208static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1209 struct etnaviv_event *event, unsigned int flags)
1210{
1211 const struct etnaviv_gem_submit *submit = event->submit;
1212 unsigned int i;
1213
1214 for (i = 0; i < submit->nr_pmrs; i++) {
1215 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1216
1217 if (pmr->flags == flags)
1218 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1219 }
1220}
1221
1222static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1223 struct etnaviv_event *event)
1224{
1225 u32 val;
1226
1227
1228 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1229 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1230 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1231
1232
1233 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1234 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1235 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1236
1237 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1238}
1239
1240static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1241 struct etnaviv_event *event)
1242{
1243 const struct etnaviv_gem_submit *submit = event->submit;
1244 unsigned int i;
1245 u32 val;
1246
1247 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1248
1249 for (i = 0; i < submit->nr_pmrs; i++) {
1250 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1251
1252 *pmr->bo_vma = pmr->sequence;
1253 }
1254
1255
1256 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1257 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1258 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1259
1260
1261 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1262 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1263 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1264}
1265
1266
1267
1268struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1269{
1270 struct etnaviv_gpu *gpu = submit->gpu;
1271 struct dma_fence *gpu_fence;
1272 unsigned int i, nr_events = 1, event[3];
1273 int ret;
1274
1275 if (!submit->runtime_resumed) {
1276 ret = pm_runtime_get_sync(gpu->dev);
1277 if (ret < 0)
1278 return NULL;
1279 submit->runtime_resumed = true;
1280 }
1281
1282
1283
1284
1285
1286
1287
1288
1289 if (submit->nr_pmrs)
1290 nr_events = 3;
1291
1292 ret = event_alloc(gpu, nr_events, event);
1293 if (ret) {
1294 DRM_ERROR("no free events\n");
1295 return NULL;
1296 }
1297
1298 mutex_lock(&gpu->lock);
1299
1300 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1301 if (!gpu_fence) {
1302 for (i = 0; i < nr_events; i++)
1303 event_free(gpu, event[i]);
1304
1305 goto out_unlock;
1306 }
1307
1308 if (submit->nr_pmrs) {
1309 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1310 kref_get(&submit->refcount);
1311 gpu->event[event[1]].submit = submit;
1312 etnaviv_sync_point_queue(gpu, event[1]);
1313 }
1314
1315 gpu->event[event[0]].fence = gpu_fence;
1316 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1317 etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1318 &submit->cmdbuf);
1319
1320 if (submit->nr_pmrs) {
1321 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1322 kref_get(&submit->refcount);
1323 gpu->event[event[2]].submit = submit;
1324 etnaviv_sync_point_queue(gpu, event[2]);
1325 }
1326
1327out_unlock:
1328 mutex_unlock(&gpu->lock);
1329
1330 return gpu_fence;
1331}
1332
1333static void sync_point_worker(struct work_struct *work)
1334{
1335 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1336 sync_point_work);
1337 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1338 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1339
1340 event->sync_point(gpu, event);
1341 etnaviv_submit_put(event->submit);
1342 event_free(gpu, gpu->sync_point_event);
1343
1344
1345 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1346}
1347
1348static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1349{
1350 u32 status_reg, status;
1351 int i;
1352
1353 if (gpu->sec_mode == ETNA_SEC_NONE)
1354 status_reg = VIVS_MMUv2_STATUS;
1355 else
1356 status_reg = VIVS_MMUv2_SEC_STATUS;
1357
1358 status = gpu_read(gpu, status_reg);
1359 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1360
1361 for (i = 0; i < 4; i++) {
1362 u32 address_reg;
1363
1364 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1365 continue;
1366
1367 if (gpu->sec_mode == ETNA_SEC_NONE)
1368 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1369 else
1370 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1371
1372 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1373 gpu_read(gpu, address_reg));
1374 }
1375}
1376
1377static irqreturn_t irq_handler(int irq, void *data)
1378{
1379 struct etnaviv_gpu *gpu = data;
1380 irqreturn_t ret = IRQ_NONE;
1381
1382 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1383
1384 if (intr != 0) {
1385 int event;
1386
1387 pm_runtime_mark_last_busy(gpu->dev);
1388
1389 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1390
1391 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1392 dev_err(gpu->dev, "AXI bus error\n");
1393 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1394 }
1395
1396 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1397 dump_mmu_fault(gpu);
1398 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1399 }
1400
1401 while ((event = ffs(intr)) != 0) {
1402 struct dma_fence *fence;
1403
1404 event -= 1;
1405
1406 intr &= ~(1 << event);
1407
1408 dev_dbg(gpu->dev, "event %u\n", event);
1409
1410 if (gpu->event[event].sync_point) {
1411 gpu->sync_point_event = event;
1412 queue_work(gpu->wq, &gpu->sync_point_work);
1413 }
1414
1415 fence = gpu->event[event].fence;
1416 if (!fence)
1417 continue;
1418
1419 gpu->event[event].fence = NULL;
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430 if (fence_after(fence->seqno, gpu->completed_fence))
1431 gpu->completed_fence = fence->seqno;
1432 dma_fence_signal(fence);
1433
1434 event_free(gpu, event);
1435 }
1436
1437 ret = IRQ_HANDLED;
1438 }
1439
1440 return ret;
1441}
1442
1443static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1444{
1445 int ret;
1446
1447 if (gpu->clk_reg) {
1448 ret = clk_prepare_enable(gpu->clk_reg);
1449 if (ret)
1450 return ret;
1451 }
1452
1453 if (gpu->clk_bus) {
1454 ret = clk_prepare_enable(gpu->clk_bus);
1455 if (ret)
1456 return ret;
1457 }
1458
1459 if (gpu->clk_core) {
1460 ret = clk_prepare_enable(gpu->clk_core);
1461 if (ret)
1462 goto disable_clk_bus;
1463 }
1464
1465 if (gpu->clk_shader) {
1466 ret = clk_prepare_enable(gpu->clk_shader);
1467 if (ret)
1468 goto disable_clk_core;
1469 }
1470
1471 return 0;
1472
1473disable_clk_core:
1474 if (gpu->clk_core)
1475 clk_disable_unprepare(gpu->clk_core);
1476disable_clk_bus:
1477 if (gpu->clk_bus)
1478 clk_disable_unprepare(gpu->clk_bus);
1479
1480 return ret;
1481}
1482
1483static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1484{
1485 if (gpu->clk_shader)
1486 clk_disable_unprepare(gpu->clk_shader);
1487 if (gpu->clk_core)
1488 clk_disable_unprepare(gpu->clk_core);
1489 if (gpu->clk_bus)
1490 clk_disable_unprepare(gpu->clk_bus);
1491 if (gpu->clk_reg)
1492 clk_disable_unprepare(gpu->clk_reg);
1493
1494 return 0;
1495}
1496
1497int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1498{
1499 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1500
1501 do {
1502 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1503
1504 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1505 return 0;
1506
1507 if (time_is_before_jiffies(timeout)) {
1508 dev_warn(gpu->dev,
1509 "timed out waiting for idle: idle=0x%x\n",
1510 idle);
1511 return -ETIMEDOUT;
1512 }
1513
1514 udelay(5);
1515 } while (1);
1516}
1517
1518static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1519{
1520 if (gpu->buffer.suballoc) {
1521
1522 mutex_lock(&gpu->lock);
1523 etnaviv_buffer_end(gpu);
1524 mutex_unlock(&gpu->lock);
1525
1526
1527
1528
1529
1530
1531 etnaviv_gpu_wait_idle(gpu, 100);
1532 }
1533
1534 return etnaviv_gpu_clk_disable(gpu);
1535}
1536
1537#ifdef CONFIG_PM
1538static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1539{
1540 int ret;
1541
1542 ret = mutex_lock_killable(&gpu->lock);
1543 if (ret)
1544 return ret;
1545
1546 etnaviv_gpu_update_clock(gpu);
1547 etnaviv_gpu_hw_init(gpu);
1548
1549 gpu->exec_state = -1;
1550
1551 mutex_unlock(&gpu->lock);
1552
1553 return 0;
1554}
1555#endif
1556
1557static int
1558etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1559 unsigned long *state)
1560{
1561 *state = 6;
1562
1563 return 0;
1564}
1565
1566static int
1567etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1568 unsigned long *state)
1569{
1570 struct etnaviv_gpu *gpu = cdev->devdata;
1571
1572 *state = gpu->freq_scale;
1573
1574 return 0;
1575}
1576
1577static int
1578etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1579 unsigned long state)
1580{
1581 struct etnaviv_gpu *gpu = cdev->devdata;
1582
1583 mutex_lock(&gpu->lock);
1584 gpu->freq_scale = state;
1585 if (!pm_runtime_suspended(gpu->dev))
1586 etnaviv_gpu_update_clock(gpu);
1587 mutex_unlock(&gpu->lock);
1588
1589 return 0;
1590}
1591
1592static struct thermal_cooling_device_ops cooling_ops = {
1593 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1594 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1595 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1596};
1597
1598static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1599 void *data)
1600{
1601 struct drm_device *drm = data;
1602 struct etnaviv_drm_private *priv = drm->dev_private;
1603 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1604 int ret;
1605
1606 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1607 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1608 (char *)dev_name(dev), gpu, &cooling_ops);
1609 if (IS_ERR(gpu->cooling))
1610 return PTR_ERR(gpu->cooling);
1611 }
1612
1613 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1614 if (!gpu->wq) {
1615 ret = -ENOMEM;
1616 goto out_thermal;
1617 }
1618
1619 ret = etnaviv_sched_init(gpu);
1620 if (ret)
1621 goto out_workqueue;
1622
1623#ifdef CONFIG_PM
1624 ret = pm_runtime_get_sync(gpu->dev);
1625#else
1626 ret = etnaviv_gpu_clk_enable(gpu);
1627#endif
1628 if (ret < 0)
1629 goto out_sched;
1630
1631
1632 gpu->drm = drm;
1633 gpu->fence_context = dma_fence_context_alloc(1);
1634 idr_init(&gpu->fence_idr);
1635 spin_lock_init(&gpu->fence_spinlock);
1636
1637 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1638 init_waitqueue_head(&gpu->fence_event);
1639
1640 priv->gpu[priv->num_gpus++] = gpu;
1641
1642 pm_runtime_mark_last_busy(gpu->dev);
1643 pm_runtime_put_autosuspend(gpu->dev);
1644
1645 return 0;
1646
1647out_sched:
1648 etnaviv_sched_fini(gpu);
1649
1650out_workqueue:
1651 destroy_workqueue(gpu->wq);
1652
1653out_thermal:
1654 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1655 thermal_cooling_device_unregister(gpu->cooling);
1656
1657 return ret;
1658}
1659
1660static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1661 void *data)
1662{
1663 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1664
1665 DBG("%s", dev_name(gpu->dev));
1666
1667 flush_workqueue(gpu->wq);
1668 destroy_workqueue(gpu->wq);
1669
1670 etnaviv_sched_fini(gpu);
1671
1672#ifdef CONFIG_PM
1673 pm_runtime_get_sync(gpu->dev);
1674 pm_runtime_put_sync_suspend(gpu->dev);
1675#else
1676 etnaviv_gpu_hw_suspend(gpu);
1677#endif
1678
1679 if (gpu->buffer.suballoc)
1680 etnaviv_cmdbuf_free(&gpu->buffer);
1681
1682 if (gpu->cmdbuf_suballoc) {
1683 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1684 gpu->cmdbuf_suballoc = NULL;
1685 }
1686
1687 if (gpu->mmu) {
1688 etnaviv_iommu_destroy(gpu->mmu);
1689 gpu->mmu = NULL;
1690 }
1691
1692 gpu->drm = NULL;
1693 idr_destroy(&gpu->fence_idr);
1694
1695 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1696 thermal_cooling_device_unregister(gpu->cooling);
1697 gpu->cooling = NULL;
1698}
1699
1700static const struct component_ops gpu_ops = {
1701 .bind = etnaviv_gpu_bind,
1702 .unbind = etnaviv_gpu_unbind,
1703};
1704
1705static const struct of_device_id etnaviv_gpu_match[] = {
1706 {
1707 .compatible = "vivante,gc"
1708 },
1709 { }
1710};
1711MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1712
1713static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1714{
1715 struct device *dev = &pdev->dev;
1716 struct etnaviv_gpu *gpu;
1717 struct resource *res;
1718 int err;
1719
1720 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1721 if (!gpu)
1722 return -ENOMEM;
1723
1724 gpu->dev = &pdev->dev;
1725 mutex_init(&gpu->lock);
1726 mutex_init(&gpu->fence_lock);
1727
1728
1729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1730 gpu->mmio = devm_ioremap_resource(&pdev->dev, res);
1731 if (IS_ERR(gpu->mmio))
1732 return PTR_ERR(gpu->mmio);
1733
1734
1735 gpu->irq = platform_get_irq(pdev, 0);
1736 if (gpu->irq < 0) {
1737 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1738 return gpu->irq;
1739 }
1740
1741 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1742 dev_name(gpu->dev), gpu);
1743 if (err) {
1744 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1745 return err;
1746 }
1747
1748
1749 gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1750 DBG("clk_reg: %p", gpu->clk_reg);
1751 if (IS_ERR(gpu->clk_reg))
1752 gpu->clk_reg = NULL;
1753
1754 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1755 DBG("clk_bus: %p", gpu->clk_bus);
1756 if (IS_ERR(gpu->clk_bus))
1757 gpu->clk_bus = NULL;
1758
1759 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1760 DBG("clk_core: %p", gpu->clk_core);
1761 if (IS_ERR(gpu->clk_core))
1762 gpu->clk_core = NULL;
1763 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1764
1765 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1766 DBG("clk_shader: %p", gpu->clk_shader);
1767 if (IS_ERR(gpu->clk_shader))
1768 gpu->clk_shader = NULL;
1769 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1770
1771
1772 dev_set_drvdata(dev, gpu);
1773
1774
1775
1776
1777
1778
1779 pm_runtime_use_autosuspend(gpu->dev);
1780 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1781 pm_runtime_enable(gpu->dev);
1782
1783 err = component_add(&pdev->dev, &gpu_ops);
1784 if (err < 0) {
1785 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1786 return err;
1787 }
1788
1789 return 0;
1790}
1791
1792static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1793{
1794 component_del(&pdev->dev, &gpu_ops);
1795 pm_runtime_disable(&pdev->dev);
1796 return 0;
1797}
1798
1799#ifdef CONFIG_PM
1800static int etnaviv_gpu_rpm_suspend(struct device *dev)
1801{
1802 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1803 u32 idle, mask;
1804
1805
1806 if (atomic_read(&gpu->sched.hw_rq_count))
1807 return -EBUSY;
1808
1809
1810 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1811 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1812 if (idle != mask)
1813 return -EBUSY;
1814
1815 return etnaviv_gpu_hw_suspend(gpu);
1816}
1817
1818static int etnaviv_gpu_rpm_resume(struct device *dev)
1819{
1820 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1821 int ret;
1822
1823 ret = etnaviv_gpu_clk_enable(gpu);
1824 if (ret)
1825 return ret;
1826
1827
1828 if (gpu->drm && gpu->buffer.suballoc) {
1829 ret = etnaviv_gpu_hw_resume(gpu);
1830 if (ret) {
1831 etnaviv_gpu_clk_disable(gpu);
1832 return ret;
1833 }
1834 }
1835
1836 return 0;
1837}
1838#endif
1839
1840static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1841 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1842 NULL)
1843};
1844
1845struct platform_driver etnaviv_gpu_driver = {
1846 .driver = {
1847 .name = "etnaviv-gpu",
1848 .owner = THIS_MODULE,
1849 .pm = &etnaviv_gpu_pm_ops,
1850 .of_match_table = etnaviv_gpu_match,
1851 },
1852 .probe = etnaviv_gpu_platform_probe,
1853 .remove = etnaviv_gpu_platform_remove,
1854 .id_table = gpu_ids,
1855};
1856
