LXR linux/drivers/gpu/drm/i915/display/intel_dpll

   1/*
   2 * Copyright © 2012-2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef _INTEL_DPLL_MGR_H_
  26#define _INTEL_DPLL_MGR_H_
  27
  28#include <linux/types.h>
  29
  30#include "intel_display.h"
  31
  32/*FIXME: Move this to a more appropriate place. */
  33#define abs_diff(a, b) ({                       \
  34        typeof(a) __a = (a);                    \
  35        typeof(b) __b = (b);                    \
  36        (void) (&__a == &__b);                  \
  37        __a > __b ? (__a - __b) : (__b - __a); })
  38
  39struct drm_atomic_state;
  40struct drm_device;
  41struct drm_i915_private;
  42struct intel_crtc;
  43struct intel_crtc_state;
  44struct intel_encoder;
  45struct intel_shared_dpll;
  46
  47/**
  48 * enum intel_dpll_id - possible DPLL ids
  49 *
  50 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
  51 */
  52enum intel_dpll_id {
  53        /**
  54         * @DPLL_ID_PRIVATE: non-shared dpll in use
  55         */
  56        DPLL_ID_PRIVATE = -1,
  57
  58        /**
  59         * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
  60         */
  61        DPLL_ID_PCH_PLL_A = 0,
  62        /**
  63         * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
  64         */
  65        DPLL_ID_PCH_PLL_B = 1,
  66
  67
  68        /**
  69         * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
  70         */
  71        DPLL_ID_WRPLL1 = 0,
  72        /**
  73         * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
  74         */
  75        DPLL_ID_WRPLL2 = 1,
  76        /**
  77         * @DPLL_ID_SPLL: HSW and BDW SPLL
  78         */
  79        DPLL_ID_SPLL = 2,
  80        /**
  81         * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
  82         */
  83        DPLL_ID_LCPLL_810 = 3,
  84        /**
  85         * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
  86         */
  87        DPLL_ID_LCPLL_1350 = 4,
  88        /**
  89         * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
  90         */
  91        DPLL_ID_LCPLL_2700 = 5,
  92
  93
  94        /**
  95         * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
  96         */
  97        DPLL_ID_SKL_DPLL0 = 0,
  98        /**
  99         * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
 100         */
 101        DPLL_ID_SKL_DPLL1 = 1,
 102        /**
 103         * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
 104         */
 105        DPLL_ID_SKL_DPLL2 = 2,
 106        /**
 107         * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
 108         */
 109        DPLL_ID_SKL_DPLL3 = 3,
 110
 111
 112        /**
 113         * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
 114         */
 115        DPLL_ID_ICL_DPLL0 = 0,
 116        /**
 117         * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
 118         */
 119        DPLL_ID_ICL_DPLL1 = 1,
 120        /**
 121         * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
 122         */
 123        DPLL_ID_ICL_TBTPLL = 2,
 124        /**
 125         * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
 126         */
 127        DPLL_ID_ICL_MGPLL1 = 3,
 128        /**
 129         * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
 130         */
 131        DPLL_ID_ICL_MGPLL2 = 4,
 132        /**
 133         * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
 134         */
 135        DPLL_ID_ICL_MGPLL3 = 5,
 136        /**
 137         * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
 138         */
 139        DPLL_ID_ICL_MGPLL4 = 6,
 140};
 141#define I915_NUM_PLLS 7
 142
 143struct intel_dpll_hw_state {
 144        /* i9xx, pch plls */
 145        u32 dpll;
 146        u32 dpll_md;
 147        u32 fp0;
 148        u32 fp1;
 149
 150        /* hsw, bdw */
 151        u32 wrpll;
 152        u32 spll;
 153
 154        /* skl */
 155        /*
 156         * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
 157         * lower part of ctrl1 and they get shifted into position when writing
 158         * the register.  This allows us to easily compare the state to share
 159         * the DPLL.
 160         */
 161        u32 ctrl1;
 162        /* HDMI only, 0 when used for DP */
 163        u32 cfgcr1, cfgcr2;
 164
 165        /* cnl */
 166        u32 cfgcr0;
 167        /* CNL also uses cfgcr1 */
 168
 169        /* bxt */
 170        u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
 171
 172        /*
 173         * ICL uses the following, already defined:
 174         * u32 cfgcr0, cfgcr1;
 175         */
 176        u32 mg_refclkin_ctl;
 177        u32 mg_clktop2_coreclkctl1;
 178        u32 mg_clktop2_hsclkctl;
 179        u32 mg_pll_div0;
 180        u32 mg_pll_div1;
 181        u32 mg_pll_lf;
 182        u32 mg_pll_frac_lock;
 183        u32 mg_pll_ssc;
 184        u32 mg_pll_bias;
 185        u32 mg_pll_tdc_coldst_bias;
 186        u32 mg_pll_bias_mask;
 187        u32 mg_pll_tdc_coldst_bias_mask;
 188};
 189
 190/**
 191 * struct intel_shared_dpll_state - hold the DPLL atomic state
 192 *
 193 * This structure holds an atomic state for the DPLL, that can represent
 194 * either its current state (in struct &intel_shared_dpll) or a desired
 195 * future state which would be applied by an atomic mode set (stored in
 196 * a struct &intel_atomic_state).
 197 *
 198 * See also intel_get_shared_dpll() and intel_release_shared_dpll().
 199 */
 200struct intel_shared_dpll_state {
 201        /**
 202         * @crtc_mask: mask of CRTC using this DPLL, active or not
 203         */
 204        unsigned crtc_mask;
 205
 206        /**
 207         * @hw_state: hardware configuration for the DPLL stored in
 208         * struct &intel_dpll_hw_state.
 209         */
 210        struct intel_dpll_hw_state hw_state;
 211};
 212
 213/**
 214 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
 215 */
 216struct intel_shared_dpll_funcs {
 217        /**
 218         * @prepare:
 219         *
 220         * Optional hook to perform operations prior to enabling the PLL.
 221         * Called from intel_prepare_shared_dpll() function unless the PLL
 222         * is already enabled.
 223         */
 224        void (*prepare)(struct drm_i915_private *dev_priv,
 225                        struct intel_shared_dpll *pll);
 226
 227        /**
 228         * @enable:
 229         *
 230         * Hook for enabling the pll, called from intel_enable_shared_dpll()
 231         * if the pll is not already enabled.
 232         */
 233        void (*enable)(struct drm_i915_private *dev_priv,
 234                       struct intel_shared_dpll *pll);
 235
 236        /**
 237         * @disable:
 238         *
 239         * Hook for disabling the pll, called from intel_disable_shared_dpll()
 240         * only when it is safe to disable the pll, i.e., there are no more
 241         * tracked users for it.
 242         */
 243        void (*disable)(struct drm_i915_private *dev_priv,
 244                        struct intel_shared_dpll *pll);
 245
 246        /**
 247         * @get_hw_state:
 248         *
 249         * Hook for reading the values currently programmed to the DPLL
 250         * registers. This is used for initial hw state readout and state
 251         * verification after a mode set.
 252         */
 253        bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 254                             struct intel_shared_dpll *pll,
 255                             struct intel_dpll_hw_state *hw_state);
 256};
 257
 258/**
 259 * struct dpll_info - display PLL platform specific info
 260 */
 261struct dpll_info {
 262        /**
 263         * @name: DPLL name; used for logging
 264         */
 265        const char *name;
 266
 267        /**
 268         * @funcs: platform specific hooks
 269         */
 270        const struct intel_shared_dpll_funcs *funcs;
 271
 272        /**
 273         * @id: unique indentifier for this DPLL; should match the index in the
 274         * dev_priv->shared_dplls array
 275         */
 276        enum intel_dpll_id id;
 277
 278#define INTEL_DPLL_ALWAYS_ON    (1 << 0)
 279        /**
 280         * @flags:
 281         *
 282         * INTEL_DPLL_ALWAYS_ON
 283         *     Inform the state checker that the DPLL is kept enabled even if
 284         *     not in use by any CRTC.
 285         */
 286        u32 flags;
 287};
 288
 289/**
 290 * struct intel_shared_dpll - display PLL with tracked state and users
 291 */
 292struct intel_shared_dpll {
 293        /**
 294         * @state:
 295         *
 296         * Store the state for the pll, including its hw state
 297         * and CRTCs using it.
 298         */
 299        struct intel_shared_dpll_state state;
 300
 301        /**
 302         * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
 303         */
 304        unsigned active_mask;
 305
 306        /**
 307         * @on: is the PLL actually active? Disabled during modeset
 308         */
 309        bool on;
 310
 311        /**
 312         * @info: platform specific info
 313         */
 314        const struct dpll_info *info;
 315};
 316
 317#define SKL_DPLL0 0
 318#define SKL_DPLL1 1
 319#define SKL_DPLL2 2
 320#define SKL_DPLL3 3
 321
 322/* shared dpll functions */
 323struct intel_shared_dpll *
 324intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
 325                            enum intel_dpll_id id);
 326enum intel_dpll_id
 327intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 328                         struct intel_shared_dpll *pll);
 329void assert_shared_dpll(struct drm_i915_private *dev_priv,
 330                        struct intel_shared_dpll *pll,
 331                        bool state);
 332#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 333#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 334struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc_state *state,
 335                                                struct intel_encoder *encoder);
 336void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
 337                               struct intel_crtc *crtc,
 338                               struct drm_atomic_state *state);
 339void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
 340void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 341void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 342void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
 343void intel_shared_dpll_init(struct drm_device *dev);
 344
 345void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 346                              const struct intel_dpll_hw_state *hw_state);
 347int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
 348enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
 349bool intel_dpll_is_combophy(enum intel_dpll_id id);
 350
 351#endif /* _INTEL_DPLL_MGR_H_ */
 352