LXR linux/drivers/gpu/drm/i915/display/intel_vbt

   1/*
   2 * Copyright © 2006-2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 *
  23 * Authors:
  24 *    Eric Anholt <eric@anholt.net>
  25 *
  26 */
  27
  28/*
  29 * This information is private to VBT parsing in intel_bios.c.
  30 *
  31 * Please do NOT include anywhere else.
  32 */
  33#ifndef _INTEL_BIOS_PRIVATE
  34#error "intel_vbt_defs.h is private to intel_bios.c"
  35#endif
  36
  37#ifndef _INTEL_VBT_DEFS_H_
  38#define _INTEL_VBT_DEFS_H_
  39
  40#include "intel_bios.h"
  41
  42/**
  43 * struct vbt_header - VBT Header structure
  44 * @signature:          VBT signature, always starts with "$VBT"
  45 * @version:            Version of this structure
  46 * @header_size:        Size of this structure
  47 * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  48 * @vbt_checksum:       Checksum
  49 * @reserved0:          Reserved
  50 * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  51 * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  52 */
  53struct vbt_header {
  54        u8 signature[20];
  55        u16 version;
  56        u16 header_size;
  57        u16 vbt_size;
  58        u8 vbt_checksum;
  59        u8 reserved0;
  60        u32 bdb_offset;
  61        u32 aim_offset[4];
  62} __packed;
  63
  64/**
  65 * struct bdb_header - BDB Header structure
  66 * @signature:          BDB signature "BIOS_DATA_BLOCK"
  67 * @version:            Version of the data block definitions
  68 * @header_size:        Size of this structure
  69 * @bdb_size:           Size of BDB (BDB Header and data blocks)
  70 */
  71struct bdb_header {
  72        u8 signature[16];
  73        u16 version;
  74        u16 header_size;
  75        u16 bdb_size;
  76} __packed;
  77
  78/*
  79 * There are several types of BIOS data blocks (BDBs), each block has
  80 * an ID and size in the first 3 bytes (ID in first, size in next 2).
  81 * Known types are listed below.
  82 */
  83enum bdb_block_id {
  84        BDB_GENERAL_FEATURES            = 1,
  85        BDB_GENERAL_DEFINITIONS         = 2,
  86        BDB_OLD_TOGGLE_LIST             = 3,
  87        BDB_MODE_SUPPORT_LIST           = 4,
  88        BDB_GENERIC_MODE_TABLE          = 5,
  89        BDB_EXT_MMIO_REGS               = 6,
  90        BDB_SWF_IO                      = 7,
  91        BDB_SWF_MMIO                    = 8,
  92        BDB_PSR                         = 9,
  93        BDB_MODE_REMOVAL_TABLE          = 10,
  94        BDB_CHILD_DEVICE_TABLE          = 11,
  95        BDB_DRIVER_FEATURES             = 12,
  96        BDB_DRIVER_PERSISTENCE          = 13,
  97        BDB_EXT_TABLE_PTRS              = 14,
  98        BDB_DOT_CLOCK_OVERRIDE          = 15,
  99        BDB_DISPLAY_SELECT              = 16,
 100        BDB_DRIVER_ROTATION             = 18,
 101        BDB_DISPLAY_REMOVE              = 19,
 102        BDB_OEM_CUSTOM                  = 20,
 103        BDB_EFP_LIST                    = 21, /* workarounds for VGA hsync/vsync */
 104        BDB_SDVO_LVDS_OPTIONS           = 22,
 105        BDB_SDVO_PANEL_DTDS             = 23,
 106        BDB_SDVO_LVDS_PNP_IDS           = 24,
 107        BDB_SDVO_LVDS_POWER_SEQ         = 25,
 108        BDB_TV_OPTIONS                  = 26,
 109        BDB_EDP                         = 27,
 110        BDB_LVDS_OPTIONS                = 40,
 111        BDB_LVDS_LFP_DATA_PTRS          = 41,
 112        BDB_LVDS_LFP_DATA               = 42,
 113        BDB_LVDS_BACKLIGHT              = 43,
 114        BDB_LVDS_POWER                  = 44,
 115        BDB_MIPI_CONFIG                 = 52,
 116        BDB_MIPI_SEQUENCE               = 53,
 117        BDB_SKIP                        = 254, /* VBIOS private block, ignore */
 118};
 119
 120/*
 121 * Block 1 - General Bit Definitions
 122 */
 123
 124struct bdb_general_features {
 125        /* bits 1 */
 126        u8 panel_fitting:2;
 127        u8 flexaim:1;
 128        u8 msg_enable:1;
 129        u8 clear_screen:3;
 130        u8 color_flip:1;
 131
 132        /* bits 2 */
 133        u8 download_ext_vbt:1;
 134        u8 enable_ssc:1;
 135        u8 ssc_freq:1;
 136        u8 enable_lfp_on_override:1;
 137        u8 disable_ssc_ddt:1;
 138        u8 underscan_vga_timings:1;
 139        u8 display_clock_mode:1;
 140        u8 vbios_hotplug_support:1;
 141
 142        /* bits 3 */
 143        u8 disable_smooth_vision:1;
 144        u8 single_dvi:1;
 145        u8 rotate_180:1;                                        /* 181 */
 146        u8 fdi_rx_polarity_inverted:1;
 147        u8 vbios_extended_mode:1;                               /* 160 */
 148        u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;                    /* 160 */
 149        u8 panel_best_fit_timing:1;                             /* 160 */
 150        u8 ignore_strap_state:1;                                /* 160 */
 151
 152        /* bits 4 */
 153        u8 legacy_monitor_detect;
 154
 155        /* bits 5 */
 156        u8 int_crt_support:1;
 157        u8 int_tv_support:1;
 158        u8 int_efp_support:1;
 159        u8 dp_ssc_enable:1;     /* PCH attached eDP supports SSC */
 160        u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 161        u8 dp_ssc_dongle_supported:1;
 162        u8 rsvd11:2; /* finish byte */
 163} __packed;
 164
 165/*
 166 * Block 2 - General Bytes Definition
 167 */
 168
 169/* pre-915 */
 170#define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 171#define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 172#define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 173#define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 174
 175/* Pre 915 */
 176#define DEVICE_TYPE_NONE        0x00
 177#define DEVICE_TYPE_CRT         0x01
 178#define DEVICE_TYPE_TV          0x09
 179#define DEVICE_TYPE_EFP         0x12
 180#define DEVICE_TYPE_LFP         0x22
 181/* On 915+ */
 182#define DEVICE_TYPE_CRT_DPMS            0x6001
 183#define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 184#define DEVICE_TYPE_TV_COMPOSITE        0x0209
 185#define DEVICE_TYPE_TV_MACROVISION      0x0289
 186#define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 187#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 188#define DEVICE_TYPE_TV_SCART            0x0209
 189#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 190#define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 191#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 192#define DEVICE_TYPE_EFP_DVI_I           0x6053
 193#define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 194#define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 195#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 196#define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 197#define DEVICE_TYPE_LFP_PANELLINK       0x5012
 198#define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 199#define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 200#define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 201#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 202
 203/* Add the device class for LFP, TV, HDMI */
 204#define DEVICE_TYPE_INT_LFP             0x1022
 205#define DEVICE_TYPE_INT_TV              0x1009
 206#define DEVICE_TYPE_HDMI                0x60D2
 207#define DEVICE_TYPE_DP                  0x68C6
 208#define DEVICE_TYPE_DP_DUAL_MODE        0x60D6
 209#define DEVICE_TYPE_eDP                 0x78C6
 210
 211#define DEVICE_TYPE_CLASS_EXTENSION     (1 << 15)
 212#define DEVICE_TYPE_POWER_MANAGEMENT    (1 << 14)
 213#define DEVICE_TYPE_HOTPLUG_SIGNALING   (1 << 13)
 214#define DEVICE_TYPE_INTERNAL_CONNECTOR  (1 << 12)
 215#define DEVICE_TYPE_NOT_HDMI_OUTPUT     (1 << 11)
 216#define DEVICE_TYPE_MIPI_OUTPUT         (1 << 10)
 217#define DEVICE_TYPE_COMPOSITE_OUTPUT    (1 << 9)
 218#define DEVICE_TYPE_DUAL_CHANNEL        (1 << 8)
 219#define DEVICE_TYPE_HIGH_SPEED_LINK     (1 << 6)
 220#define DEVICE_TYPE_LVDS_SIGNALING      (1 << 5)
 221#define DEVICE_TYPE_TMDS_DVI_SIGNALING  (1 << 4)
 222#define DEVICE_TYPE_VIDEO_SIGNALING     (1 << 3)
 223#define DEVICE_TYPE_DISPLAYPORT_OUTPUT  (1 << 2)
 224#define DEVICE_TYPE_DIGITAL_OUTPUT      (1 << 1)
 225#define DEVICE_TYPE_ANALOG_OUTPUT       (1 << 0)
 226
 227/*
 228 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
 229 * system, the other bits may or may not be set for eDP outputs.
 230 */
 231#define DEVICE_TYPE_eDP_BITS \
 232        (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 233         DEVICE_TYPE_MIPI_OUTPUT |              \
 234         DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 235         DEVICE_TYPE_DUAL_CHANNEL |             \
 236         DEVICE_TYPE_LVDS_SIGNALING |           \
 237         DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 238         DEVICE_TYPE_VIDEO_SIGNALING |          \
 239         DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 240         DEVICE_TYPE_ANALOG_OUTPUT)
 241
 242#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
 243        (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 244         DEVICE_TYPE_MIPI_OUTPUT |              \
 245         DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 246         DEVICE_TYPE_LVDS_SIGNALING |           \
 247         DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 248         DEVICE_TYPE_VIDEO_SIGNALING |          \
 249         DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 250         DEVICE_TYPE_DIGITAL_OUTPUT |           \
 251         DEVICE_TYPE_ANALOG_OUTPUT)
 252
 253#define DEVICE_CFG_NONE         0x00
 254#define DEVICE_CFG_12BIT_DVOB   0x01
 255#define DEVICE_CFG_12BIT_DVOC   0x02
 256#define DEVICE_CFG_24BIT_DVOBC  0x09
 257#define DEVICE_CFG_24BIT_DVOCB  0x0a
 258#define DEVICE_CFG_DUAL_DVOB    0x11
 259#define DEVICE_CFG_DUAL_DVOC    0x12
 260#define DEVICE_CFG_DUAL_DVOBC   0x13
 261#define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 262#define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 263
 264#define DEVICE_WIRE_NONE        0x00
 265#define DEVICE_WIRE_DVOB        0x01
 266#define DEVICE_WIRE_DVOC        0x02
 267#define DEVICE_WIRE_DVOBC       0x03
 268#define DEVICE_WIRE_DVOBB       0x05
 269#define DEVICE_WIRE_DVOCC       0x06
 270#define DEVICE_WIRE_DVOB_MASTER 0x0d
 271#define DEVICE_WIRE_DVOC_MASTER 0x0e
 272
 273/* dvo_port pre BDB 155 */
 274#define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 275#define DEVICE_PORT_DVOB        0x01
 276#define DEVICE_PORT_DVOC        0x02
 277
 278/* dvo_port BDB 155+ */
 279#define DVO_PORT_HDMIA          0
 280#define DVO_PORT_HDMIB          1
 281#define DVO_PORT_HDMIC          2
 282#define DVO_PORT_HDMID          3
 283#define DVO_PORT_LVDS           4
 284#define DVO_PORT_TV             5
 285#define DVO_PORT_CRT            6
 286#define DVO_PORT_DPB            7
 287#define DVO_PORT_DPC            8
 288#define DVO_PORT_DPD            9
 289#define DVO_PORT_DPA            10
 290#define DVO_PORT_DPE            11                              /* 193 */
 291#define DVO_PORT_HDMIE          12                              /* 193 */
 292#define DVO_PORT_DPF            13                              /* N/A */
 293#define DVO_PORT_HDMIF          14                              /* N/A */
 294#define DVO_PORT_MIPIA          21                              /* 171 */
 295#define DVO_PORT_MIPIB          22                              /* 171 */
 296#define DVO_PORT_MIPIC          23                              /* 171 */
 297#define DVO_PORT_MIPID          24                              /* 171 */
 298
 299#define HDMI_MAX_DATA_RATE_PLATFORM     0                       /* 204 */
 300#define HDMI_MAX_DATA_RATE_297          1                       /* 204 */
 301#define HDMI_MAX_DATA_RATE_165          2                       /* 204 */
 302
 303#define LEGACY_CHILD_DEVICE_CONFIG_SIZE         33
 304
 305/* DDC Bus DDI Type 155+ */
 306enum vbt_gmbus_ddi {
 307        DDC_BUS_DDI_B = 0x1,
 308        DDC_BUS_DDI_C,
 309        DDC_BUS_DDI_D,
 310        DDC_BUS_DDI_F,
 311        ICL_DDC_BUS_DDI_A = 0x1,
 312        ICL_DDC_BUS_DDI_B,
 313        ICL_DDC_BUS_PORT_1 = 0x4,
 314        ICL_DDC_BUS_PORT_2,
 315        ICL_DDC_BUS_PORT_3,
 316        ICL_DDC_BUS_PORT_4,
 317        MCC_DDC_BUS_DDI_A = 0x1,
 318        MCC_DDC_BUS_DDI_B,
 319        MCC_DDC_BUS_DDI_C = 0x4,
 320};
 321
 322#define DP_AUX_A 0x40
 323#define DP_AUX_B 0x10
 324#define DP_AUX_C 0x20
 325#define DP_AUX_D 0x30
 326#define DP_AUX_E 0x50
 327#define DP_AUX_F 0x60
 328
 329#define VBT_DP_MAX_LINK_RATE_HBR3       0
 330#define VBT_DP_MAX_LINK_RATE_HBR2       1
 331#define VBT_DP_MAX_LINK_RATE_HBR        2
 332#define VBT_DP_MAX_LINK_RATE_LBR        3
 333
 334/*
 335 * The child device config, aka the display device data structure, provides a
 336 * description of a port and its configuration on the platform.
 337 *
 338 * The child device config size has been increased, and fields have been added
 339 * and their meaning has changed over time. Care must be taken when accessing
 340 * basically any of the fields to ensure the correct interpretation for the BDB
 341 * version in question.
 342 *
 343 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
 344 * space for the full structure below, and initialize the tail not actually
 345 * present in VBT to zeros. Accessing those fields is fine, as long as the
 346 * default zero is taken into account, again according to the BDB version.
 347 *
 348 * BDB versions 155 and below are considered legacy, and version 155 seems to be
 349 * a baseline for some of the VBT documentation. When adding new fields, please
 350 * include the BDB version when the field was added, if it's above that.
 351 */
 352struct child_device_config {
 353        u16 handle;
 354        u16 device_type; /* See DEVICE_TYPE_* above */
 355
 356        union {
 357                u8  device_id[10]; /* ascii string */
 358                struct {
 359                        u8 i2c_speed;
 360                        u8 dp_onboard_redriver;                 /* 158 */
 361                        u8 dp_ondock_redriver;                  /* 158 */
 362                        u8 hdmi_level_shifter_value:5;          /* 169 */
 363                        u8 hdmi_max_data_rate:3;                /* 204 */
 364                        u16 dtd_buf_ptr;                        /* 161 */
 365                        u8 edidless_efp:1;                      /* 161 */
 366                        u8 compression_enable:1;                /* 198 */
 367                        u8 compression_method:1;                /* 198 */
 368                        u8 ganged_edp:1;                        /* 202 */
 369                        u8 reserved0:4;
 370                        u8 compression_structure_index:4;       /* 198 */
 371                        u8 reserved1:4;
 372                        u8 slave_port;                          /* 202 */
 373                        u8 reserved2;
 374                } __packed;
 375        } __packed;
 376
 377        u16 addin_offset;
 378        u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
 379        u8 i2c_pin;
 380        u8 slave_addr;
 381        u8 ddc_pin;
 382        u16 edid_ptr;
 383        u8 dvo_cfg; /* See DEVICE_CFG_* above */
 384
 385        union {
 386                struct {
 387                        u8 dvo2_port;
 388                        u8 i2c2_pin;
 389                        u8 slave2_addr;
 390                        u8 ddc2_pin;
 391                } __packed;
 392                struct {
 393                        u8 efp_routed:1;                        /* 158 */
 394                        u8 lane_reversal:1;                     /* 184 */
 395                        u8 lspcon:1;                            /* 192 */
 396                        u8 iboost:1;                            /* 196 */
 397                        u8 hpd_invert:1;                        /* 196 */
 398                        u8 use_vbt_vswing:1;                    /* 218 */
 399                        u8 flag_reserved:2;
 400                        u8 hdmi_support:1;                      /* 158 */
 401                        u8 dp_support:1;                        /* 158 */
 402                        u8 tmds_support:1;                      /* 158 */
 403                        u8 support_reserved:5;
 404                        u8 aux_channel;
 405                        u8 dongle_detect;
 406                } __packed;
 407        } __packed;
 408
 409        u8 pipe_cap:2;
 410        u8 sdvo_stall:1;                                        /* 158 */
 411        u8 hpd_status:2;
 412        u8 integrated_encoder:1;
 413        u8 capabilities_reserved:2;
 414        u8 dvo_wiring; /* See DEVICE_WIRE_* above */
 415
 416        union {
 417                u8 dvo2_wiring;
 418                u8 mipi_bridge_type;                            /* 171 */
 419        } __packed;
 420
 421        u16 extended_type;
 422        u8 dvo_function;
 423        u8 dp_usb_type_c:1;                                     /* 195 */
 424        u8 tbt:1;                                               /* 209 */
 425        u8 flags2_reserved:2;                                   /* 195 */
 426        u8 dp_port_trace_length:4;                              /* 209 */
 427        u8 dp_gpio_index;                                       /* 195 */
 428        u16 dp_gpio_pin_num;                                    /* 195 */
 429        u8 dp_iboost_level:4;                                   /* 196 */
 430        u8 hdmi_iboost_level:4;                                 /* 196 */
 431        u8 dp_max_link_rate:2;                                  /* 216 CNL+ */
 432        u8 dp_max_link_rate_reserved:6;                         /* 216 */
 433} __packed;
 434
 435struct bdb_general_definitions {
 436        /* DDC GPIO */
 437        u8 crt_ddc_gmbus_pin;
 438
 439        /* DPMS bits */
 440        u8 dpms_acpi:1;
 441        u8 skip_boot_crt_detect:1;
 442        u8 dpms_aim:1;
 443        u8 rsvd1:5; /* finish byte */
 444
 445        /* boot device bits */
 446        u8 boot_display[2];
 447        u8 child_dev_size;
 448
 449        /*
 450         * Device info:
 451         * If TV is present, it'll be at devices[0].
 452         * LVDS will be next, either devices[0] or [1], if present.
 453         * On some platforms the number of device is 6. But could be as few as
 454         * 4 if both TV and LVDS are missing.
 455         * And the device num is related with the size of general definition
 456         * block. It is obtained by using the following formula:
 457         * number = (block_size - sizeof(bdb_general_definitions))/
 458         *           defs->child_dev_size;
 459         */
 460        u8 devices[0];
 461} __packed;
 462
 463/*
 464 * Block 9 - SRD Feature Block
 465 */
 466
 467struct psr_table {
 468        /* Feature bits */
 469        u8 full_link:1;
 470        u8 require_aux_to_wakeup:1;
 471        u8 feature_bits_rsvd:6;
 472
 473        /* Wait times */
 474        u8 idle_frames:4;
 475        u8 lines_to_wait:3;
 476        u8 wait_times_rsvd:1;
 477
 478        /* TP wake up time in multiple of 100 */
 479        u16 tp1_wakeup_time;
 480        u16 tp2_tp3_wakeup_time;
 481} __packed;
 482
 483struct bdb_psr {
 484        struct psr_table psr_table[16];
 485
 486        /* PSR2 TP2/TP3 wakeup time for 16 panels */
 487        u32 psr2_tp2_tp3_wakeup_time;
 488} __packed;
 489
 490/*
 491 * Block 12 - Driver Features Data Block
 492 */
 493
 494#define BDB_DRIVER_FEATURE_NO_LVDS              0
 495#define BDB_DRIVER_FEATURE_INT_LVDS             1
 496#define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 497#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS        3
 498
 499struct bdb_driver_features {
 500        u8 boot_dev_algorithm:1;
 501        u8 block_display_switch:1;
 502        u8 allow_display_switch:1;
 503        u8 hotplug_dvo:1;
 504        u8 dual_view_zoom:1;
 505        u8 int15h_hook:1;
 506        u8 sprite_in_clone:1;
 507        u8 primary_lfp_id:1;
 508
 509        u16 boot_mode_x;
 510        u16 boot_mode_y;
 511        u8 boot_mode_bpp;
 512        u8 boot_mode_refresh;
 513
 514        u16 enable_lfp_primary:1;
 515        u16 selective_mode_pruning:1;
 516        u16 dual_frequency:1;
 517        u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 518        u16 nt_clone_support:1;
 519        u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 520        u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 521        u16 cui_aspect_scaling:1;
 522        u16 preserve_aspect_ratio:1;
 523        u16 sdvo_device_power_down:1;
 524        u16 crt_hotplug:1;
 525        u16 lvds_config:2;
 526        u16 tv_hotplug:1;
 527        u16 hdmi_config:2;
 528
 529        u8 static_display:1;
 530        u8 reserved2:7;
 531        u16 legacy_crt_max_x;
 532        u16 legacy_crt_max_y;
 533        u8 legacy_crt_max_refresh;
 534
 535        u8 hdmi_termination;
 536        u8 custom_vbt_version;
 537        /* Driver features data block */
 538        u16 rmpm_enabled:1;
 539        u16 s2ddt_enabled:1;
 540        u16 dpst_enabled:1;
 541        u16 bltclt_enabled:1;
 542        u16 adb_enabled:1;
 543        u16 drrs_enabled:1;
 544        u16 grs_enabled:1;
 545        u16 gpmt_enabled:1;
 546        u16 tbt_enabled:1;
 547        u16 psr_enabled:1;
 548        u16 ips_enabled:1;
 549        u16 reserved3:4;
 550        u16 pc_feature_valid:1;
 551} __packed;
 552
 553/*
 554 * Block 22 - SDVO LVDS General Options
 555 */
 556
 557struct bdb_sdvo_lvds_options {
 558        u8 panel_backlight;
 559        u8 h40_set_panel_type;
 560        u8 panel_type;
 561        u8 ssc_clk_freq;
 562        u16 als_low_trip;
 563        u16 als_high_trip;
 564        u8 sclalarcoeff_tab_row_num;
 565        u8 sclalarcoeff_tab_row_size;
 566        u8 coefficient[8];
 567        u8 panel_misc_bits_1;
 568        u8 panel_misc_bits_2;
 569        u8 panel_misc_bits_3;
 570        u8 panel_misc_bits_4;
 571} __packed;
 572
 573/*
 574 * Block 23 - SDVO LVDS Panel DTDs
 575 */
 576
 577struct lvds_dvo_timing {
 578        u16 clock;              /**< In 10khz */
 579        u8 hactive_lo;
 580        u8 hblank_lo;
 581        u8 hblank_hi:4;
 582        u8 hactive_hi:4;
 583        u8 vactive_lo;
 584        u8 vblank_lo;
 585        u8 vblank_hi:4;
 586        u8 vactive_hi:4;
 587        u8 hsync_off_lo;
 588        u8 hsync_pulse_width_lo;
 589        u8 vsync_pulse_width_lo:4;
 590        u8 vsync_off_lo:4;
 591        u8 vsync_pulse_width_hi:2;
 592        u8 vsync_off_hi:2;
 593        u8 hsync_pulse_width_hi:2;
 594        u8 hsync_off_hi:2;
 595        u8 himage_lo;
 596        u8 vimage_lo;
 597        u8 vimage_hi:4;
 598        u8 himage_hi:4;
 599        u8 h_border;
 600        u8 v_border;
 601        u8 rsvd1:3;
 602        u8 digital:2;
 603        u8 vsync_positive:1;
 604        u8 hsync_positive:1;
 605        u8 non_interlaced:1;
 606} __packed;
 607
 608struct bdb_sdvo_panel_dtds {
 609        struct lvds_dvo_timing dtds[4];
 610} __packed;
 611
 612/*
 613 * Block 27 - eDP VBT Block
 614 */
 615
 616#define EDP_18BPP       0
 617#define EDP_24BPP       1
 618#define EDP_30BPP       2
 619#define EDP_RATE_1_62   0
 620#define EDP_RATE_2_7    1
 621#define EDP_LANE_1      0
 622#define EDP_LANE_2      1
 623#define EDP_LANE_4      3
 624#define EDP_PREEMPHASIS_NONE    0
 625#define EDP_PREEMPHASIS_3_5dB   1
 626#define EDP_PREEMPHASIS_6dB     2
 627#define EDP_PREEMPHASIS_9_5dB   3
 628#define EDP_VSWING_0_4V         0
 629#define EDP_VSWING_0_6V         1
 630#define EDP_VSWING_0_8V         2
 631#define EDP_VSWING_1_2V         3
 632
 633
 634struct edp_fast_link_params {
 635        u8 rate:4;
 636        u8 lanes:4;
 637        u8 preemphasis:4;
 638        u8 vswing:4;
 639} __packed;
 640
 641struct edp_pwm_delays {
 642        u16 pwm_on_to_backlight_enable;
 643        u16 backlight_disable_to_pwm_off;
 644} __packed;
 645
 646struct edp_full_link_params {
 647        u8 preemphasis:4;
 648        u8 vswing:4;
 649} __packed;
 650
 651struct bdb_edp {
 652        struct edp_power_seq power_seqs[16];
 653        u32 color_depth;
 654        struct edp_fast_link_params fast_link_params[16];
 655        u32 sdrrs_msa_timing_delay;
 656
 657        /* ith bit indicates enabled/disabled for (i+1)th panel */
 658        u16 edp_s3d_feature;                                    /* 162 */
 659        u16 edp_t3_optimization;                                /* 165 */
 660        u64 edp_vswing_preemph;                                 /* 173 */
 661        u16 fast_link_training;                                 /* 182 */
 662        u16 dpcd_600h_write_required;                           /* 185 */
 663        struct edp_pwm_delays pwm_delays[16];                   /* 186 */
 664        u16 full_link_params_provided;                          /* 199 */
 665        struct edp_full_link_params full_link_params[16];       /* 199 */
 666} __packed;
 667
 668/*
 669 * Block 40 - LFP Data Block
 670 */
 671
 672/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 673#define MODE_MASK               0x3
 674
 675struct bdb_lvds_options {
 676        u8 panel_type;
 677        u8 panel_type2;                                         /* 212 */
 678        /* LVDS capabilities, stored in a dword */
 679        u8 pfit_mode:2;
 680        u8 pfit_text_mode_enhanced:1;
 681        u8 pfit_gfx_mode_enhanced:1;
 682        u8 pfit_ratio_auto:1;
 683        u8 pixel_dither:1;
 684        u8 lvds_edid:1;
 685        u8 rsvd2:1;
 686        u8 rsvd4;
 687        /* LVDS Panel channel bits stored here */
 688        u32 lvds_panel_channel_bits;
 689        /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 690        u16 ssc_bits;
 691        u16 ssc_freq;
 692        u16 ssc_ddt;
 693        /* Panel color depth defined here */
 694        u16 panel_color_depth;
 695        /* LVDS panel type bits stored here */
 696        u32 dps_panel_type_bits;
 697        /* LVDS backlight control type bits stored here */
 698        u32 blt_control_type_bits;
 699
 700        u16 lcdvcc_s0_enable;                                   /* 200 */
 701        u32 rotation;                                           /* 228 */
 702} __packed;
 703
 704/*
 705 * Block 41 - LFP Data Table Pointers
 706 */
 707
 708/* LFP pointer table contains entries to the struct below */
 709struct lvds_lfp_data_ptr {
 710        u16 fp_timing_offset; /* offsets are from start of bdb */
 711        u8 fp_table_size;
 712        u16 dvo_timing_offset;
 713        u8 dvo_table_size;
 714        u16 panel_pnp_id_offset;
 715        u8 pnp_table_size;
 716} __packed;
 717
 718struct bdb_lvds_lfp_data_ptrs {
 719        u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 720        struct lvds_lfp_data_ptr ptr[16];
 721} __packed;
 722
 723/*
 724 * Block 42 - LFP Data Tables
 725 */
 726
 727/* LFP data has 3 blocks per entry */
 728struct lvds_fp_timing {
 729        u16 x_res;
 730        u16 y_res;
 731        u32 lvds_reg;
 732        u32 lvds_reg_val;
 733        u32 pp_on_reg;
 734        u32 pp_on_reg_val;
 735        u32 pp_off_reg;
 736        u32 pp_off_reg_val;
 737        u32 pp_cycle_reg;
 738        u32 pp_cycle_reg_val;
 739        u32 pfit_reg;
 740        u32 pfit_reg_val;
 741        u16 terminator;
 742} __packed;
 743
 744struct lvds_pnp_id {
 745        u16 mfg_name;
 746        u16 product_code;
 747        u32 serial;
 748        u8 mfg_week;
 749        u8 mfg_year;
 750} __packed;
 751
 752struct lvds_lfp_data_entry {
 753        struct lvds_fp_timing fp_timing;
 754        struct lvds_dvo_timing dvo_timing;
 755        struct lvds_pnp_id pnp_id;
 756} __packed;
 757
 758struct bdb_lvds_lfp_data {
 759        struct lvds_lfp_data_entry data[16];
 760} __packed;
 761
 762/*
 763 * Block 43 - LFP Backlight Control Data Block
 764 */
 765
 766#define BDB_BACKLIGHT_TYPE_NONE 0
 767#define BDB_BACKLIGHT_TYPE_PWM  2
 768
 769struct lfp_backlight_data_entry {
 770        u8 type:2;
 771        u8 active_low_pwm:1;
 772        u8 obsolete1:5;
 773        u16 pwm_freq_hz;
 774        u8 min_brightness;
 775        u8 obsolete2;
 776        u8 obsolete3;
 777} __packed;
 778
 779struct lfp_backlight_control_method {
 780        u8 type:4;
 781        u8 controller:4;
 782} __packed;
 783
 784struct bdb_lfp_backlight_data {
 785        u8 entry_size;
 786        struct lfp_backlight_data_entry data[16];
 787        u8 level[16];
 788        struct lfp_backlight_control_method backlight_control[16];
 789} __packed;
 790
 791/*
 792 * Block 52 - MIPI Configuration Block
 793 */
 794
 795#define MAX_MIPI_CONFIGURATIONS 6
 796
 797struct bdb_mipi_config {
 798        struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 799        struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 800} __packed;
 801
 802/*
 803 * Block 53 - MIPI Sequence Block
 804 */
 805
 806struct bdb_mipi_sequence {
 807        u8 version;
 808        u8 data[0]; /* up to 6 variable length blocks */
 809} __packed;
 810
 811#endif /* _INTEL_VBT_DEFS_H_ */
 812