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28#include <linux/kernel.h>
29
30#include "i915_drv.h"
31#include "intel_drv.h"
32#include "intel_dsi.h"
33#include "intel_sideband.h"
34
35static const u16 lfsr_converts[] = {
36 426, 469, 234, 373, 442, 221, 110, 311, 411,
37 461, 486, 243, 377, 188, 350, 175, 343, 427, 213,
38 106, 53, 282, 397, 454, 227, 113, 56, 284, 142,
39 71, 35, 273, 136, 324, 418, 465, 488, 500, 506
40};
41
42
43static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
44 int lane_count)
45{
46 u32 dsi_clk_khz;
47 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
48
49
50
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
52
53 return dsi_clk_khz;
54}
55
56static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
57 struct intel_crtc_state *config,
58 int target_dsi_clk)
59{
60 unsigned int m_min, m_max, p_min = 2, p_max = 6;
61 unsigned int m, n, p;
62 unsigned int calc_m, calc_p;
63 int delta, ref_clk;
64
65
66 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
67 DRM_ERROR("DSI CLK Out of Range\n");
68 return -ECHRNG;
69 }
70
71 if (IS_CHERRYVIEW(dev_priv)) {
72 ref_clk = 100000;
73 n = 4;
74 m_min = 70;
75 m_max = 96;
76 } else {
77 ref_clk = 25000;
78 n = 1;
79 m_min = 62;
80 m_max = 92;
81 }
82
83 calc_p = p_min;
84 calc_m = m_min;
85 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
86
87 for (m = m_min; m <= m_max && delta; m++) {
88 for (p = p_min; p <= p_max && delta; p++) {
89
90
91
92
93 int calc_dsi_clk = (m * ref_clk) / (p * n);
94 int d = abs(target_dsi_clk - calc_dsi_clk);
95 if (d < delta) {
96 delta = d;
97 calc_m = m;
98 calc_p = p;
99 }
100 }
101 }
102
103
104 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
105 config->dsi_pll.div =
106 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
107 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
108
109 return 0;
110}
111
112
113
114
115
116int vlv_dsi_pll_compute(struct intel_encoder *encoder,
117 struct intel_crtc_state *config)
118{
119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
120 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
121 int ret;
122 u32 dsi_clk;
123
124 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
125 intel_dsi->lane_count);
126
127 ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
128 if (ret) {
129 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
130 return ret;
131 }
132
133 if (intel_dsi->ports & (1 << PORT_A))
134 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
135
136 if (intel_dsi->ports & (1 << PORT_C))
137 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
138
139 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
140
141 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
142 config->dsi_pll.div, config->dsi_pll.ctrl);
143
144 return 0;
145}
146
147void vlv_dsi_pll_enable(struct intel_encoder *encoder,
148 const struct intel_crtc_state *config)
149{
150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
151
152 DRM_DEBUG_KMS("\n");
153
154 vlv_cck_get(dev_priv);
155
156 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
157 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
158 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
159 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
160
161
162
163
164 usleep_range(10, 50);
165
166 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
167
168 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
169 DSI_PLL_LOCK, 20)) {
170
171 vlv_cck_put(dev_priv);
172 DRM_ERROR("DSI PLL lock failed\n");
173 return;
174 }
175 vlv_cck_put(dev_priv);
176
177 DRM_DEBUG_KMS("DSI PLL locked\n");
178}
179
180void vlv_dsi_pll_disable(struct intel_encoder *encoder)
181{
182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
183 u32 tmp;
184
185 DRM_DEBUG_KMS("\n");
186
187 vlv_cck_get(dev_priv);
188
189 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
190 tmp &= ~DSI_PLL_VCO_EN;
191 tmp |= DSI_PLL_LDO_GATE;
192 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
193
194 vlv_cck_put(dev_priv);
195}
196
197bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
198{
199 bool enabled;
200 u32 val;
201 u32 mask;
202
203 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
204 val = I915_READ(BXT_DSI_PLL_ENABLE);
205 enabled = (val & mask) == mask;
206
207 if (!enabled)
208 return false;
209
210
211
212
213
214
215
216
217
218 val = I915_READ(BXT_DSI_PLL_CTL);
219 if (IS_GEMINILAKE(dev_priv)) {
220 if (!(val & BXT_DSIA_16X_MASK)) {
221 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
222 enabled = false;
223 }
224 } else {
225 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
226 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
227 enabled = false;
228 }
229 }
230
231 return enabled;
232}
233
234void bxt_dsi_pll_disable(struct intel_encoder *encoder)
235{
236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
237 u32 val;
238
239 DRM_DEBUG_KMS("\n");
240
241 val = I915_READ(BXT_DSI_PLL_ENABLE);
242 val &= ~BXT_DSI_PLL_DO_ENABLE;
243 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
244
245
246
247
248
249 if (intel_wait_for_register(&dev_priv->uncore,
250 BXT_DSI_PLL_ENABLE,
251 BXT_DSI_PLL_LOCKED,
252 0,
253 1))
254 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
255}
256
257u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
258 struct intel_crtc_state *config)
259{
260 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
261 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
262 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
263 u32 dsi_clock, pclk;
264 u32 pll_ctl, pll_div;
265 u32 m = 0, p = 0, n;
266 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
267 int i;
268
269 DRM_DEBUG_KMS("\n");
270
271 vlv_cck_get(dev_priv);
272 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
273 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
274 vlv_cck_put(dev_priv);
275
276 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
277 config->dsi_pll.div = pll_div;
278
279
280 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
281 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
282
283
284 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
285 n = 1 << n;
286
287
288 pll_div &= DSI_PLL_M1_DIV_MASK;
289 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
290
291 while (pll_ctl) {
292 pll_ctl = pll_ctl >> 1;
293 p++;
294 }
295 p--;
296
297 if (!p) {
298 DRM_ERROR("wrong P1 divisor\n");
299 return 0;
300 }
301
302 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
303 if (lfsr_converts[i] == pll_div)
304 break;
305 }
306
307 if (i == ARRAY_SIZE(lfsr_converts)) {
308 DRM_ERROR("wrong m_seed programmed\n");
309 return 0;
310 }
311
312 m = i + 62;
313
314 dsi_clock = (m * refclk) / (p * n);
315
316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
317
318 return pclk;
319}
320
321u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
322 struct intel_crtc_state *config)
323{
324 u32 pclk;
325 u32 dsi_clk;
326 u32 dsi_ratio;
327 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
330
331 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
332
333 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
334
335 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
336
337 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
338
339 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
340 return pclk;
341}
342
343void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
344{
345 u32 temp;
346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
347 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
348
349 temp = I915_READ(MIPI_CTRL(port));
350 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
351 I915_WRITE(MIPI_CTRL(port), temp |
352 intel_dsi->escape_clk_div <<
353 ESCAPE_CLOCK_DIVIDER_SHIFT);
354}
355
356static void glk_dsi_program_esc_clock(struct drm_device *dev,
357 const struct intel_crtc_state *config)
358{
359 struct drm_i915_private *dev_priv = to_i915(dev);
360 u32 dsi_rate = 0;
361 u32 pll_ratio = 0;
362 u32 ddr_clk = 0;
363 u32 div1_value = 0;
364 u32 div2_value = 0;
365 u32 txesc1_div = 0;
366 u32 txesc2_div = 0;
367
368 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
369
370 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
371
372 ddr_clk = dsi_rate / 2;
373
374
375 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
376
377
378 if (div1_value <= 10)
379 txesc1_div = div1_value;
380 else if ((div1_value > 10) && (div1_value <= 20))
381 txesc1_div = DIV_ROUND_UP(div1_value, 2);
382 else if ((div1_value > 20) && (div1_value <= 30))
383 txesc1_div = DIV_ROUND_UP(div1_value, 4);
384 else if ((div1_value > 30) && (div1_value <= 40))
385 txesc1_div = DIV_ROUND_UP(div1_value, 6);
386 else if ((div1_value > 40) && (div1_value <= 50))
387 txesc1_div = DIV_ROUND_UP(div1_value, 8);
388 else
389 txesc1_div = 10;
390
391
392 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
393
394 if (div2_value < 10)
395 txesc2_div = div2_value;
396 else
397 txesc2_div = 10;
398
399 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
400 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
401}
402
403
404static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
405 const struct intel_crtc_state *config)
406{
407 struct drm_i915_private *dev_priv = to_i915(dev);
408 u32 tmp;
409 u32 dsi_rate = 0;
410 u32 pll_ratio = 0;
411 u32 rx_div;
412 u32 tx_div;
413 u32 rx_div_upper;
414 u32 rx_div_lower;
415 u32 mipi_8by3_divider;
416
417
418 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
419 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
420 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
421 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
422 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
423
424
425 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
426 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
427
428
429
430
431
432 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
433
434
435
436
437 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
438
439
440
441
442
443
444 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
445 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
446
447 mipi_8by3_divider = 0x2;
448
449 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
450 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
451 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
452 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
453
454 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
455}
456
457int bxt_dsi_pll_compute(struct intel_encoder *encoder,
458 struct intel_crtc_state *config)
459{
460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
461 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
462 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
463 u32 dsi_clk;
464
465 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
466 intel_dsi->lane_count);
467
468
469
470
471
472
473 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
474
475 if (IS_BROXTON(dev_priv)) {
476 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
477 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
478 } else {
479 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
480 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
481 }
482
483 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
484 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
485 return -ECHRNG;
486 } else
487 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
488
489
490
491
492
493
494 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
495
496
497
498
499 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
500 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
501
502 return 0;
503}
504
505void bxt_dsi_pll_enable(struct intel_encoder *encoder,
506 const struct intel_crtc_state *config)
507{
508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
509 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
510 enum port port;
511 u32 val;
512
513 DRM_DEBUG_KMS("\n");
514
515
516 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
517 POSTING_READ(BXT_DSI_PLL_CTL);
518
519
520 if (IS_BROXTON(dev_priv)) {
521 for_each_dsi_port(port, intel_dsi->ports)
522 bxt_dsi_program_clocks(encoder->base.dev, port, config);
523 } else {
524 glk_dsi_program_esc_clock(encoder->base.dev, config);
525 }
526
527
528 val = I915_READ(BXT_DSI_PLL_ENABLE);
529 val |= BXT_DSI_PLL_DO_ENABLE;
530 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
531
532
533 if (intel_wait_for_register(&dev_priv->uncore,
534 BXT_DSI_PLL_ENABLE,
535 BXT_DSI_PLL_LOCKED,
536 BXT_DSI_PLL_LOCKED,
537 1)) {
538 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
539 return;
540 }
541
542 DRM_DEBUG_KMS("DSI PLL locked\n");
543}
544
545void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
546{
547 u32 tmp;
548 struct drm_device *dev = encoder->base.dev;
549 struct drm_i915_private *dev_priv = to_i915(dev);
550
551
552 if (IS_BROXTON(dev_priv)) {
553 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
554 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
555 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
556 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
557 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
558 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
559 } else {
560 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
561 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
562 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
563
564 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
565 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
566 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
567 }
568 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
569}
570