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35#ifndef _GVT_DISPLAY_H_
36#define _GVT_DISPLAY_H_
37
38#define SBI_REG_MAX 20
39#define DPCD_SIZE 0x700
40
41#define intel_vgpu_port(vgpu, port) \
42 (&(vgpu->display.ports[port]))
43
44#define intel_vgpu_has_monitor_on_port(vgpu, port) \
45 (intel_vgpu_port(vgpu, port)->edid && \
46 intel_vgpu_port(vgpu, port)->edid->data_valid)
47
48#define intel_vgpu_port_is_dp(vgpu, port) \
49 ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
50 (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
51 (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
52 (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
53
54#define INTEL_GVT_MAX_UEVENT_VARS 3
55
56
57#define DPCD_SIZE 0x700
58
59
60#define DP_SET_POWER 0x600
61#define DP_SET_POWER_D0 0x1
62#define AUX_NATIVE_WRITE 0x8
63#define AUX_NATIVE_READ 0x9
64
65#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
66#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
67#define AUX_NATIVE_REPLY_NAK (0x1 << 4)
68#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
69
70#define AUX_BURST_SIZE 20
71
72
73#define DPCD_REV 0x000
74#define DPCD_MAX_LINK_RATE 0x001
75#define DPCD_MAX_LANE_COUNT 0x002
76
77#define DPCD_TRAINING_PATTERN_SET 0x102
78#define DPCD_SINK_COUNT 0x200
79#define DPCD_LANE0_1_STATUS 0x202
80#define DPCD_LANE2_3_STATUS 0x203
81#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
82#define DPCD_SINK_STATUS 0x205
83
84
85#define DPCD_TRAINING_PATTERN_SET_MASK 0x03
86#define DPCD_LINK_TRAINING_DISABLED 0x00
87#define DPCD_TRAINING_PATTERN_1 0x01
88#define DPCD_TRAINING_PATTERN_2 0x02
89
90#define DPCD_CP_READY_MASK (1 << 6)
91
92
93#define DPCD_LANES_CR_DONE 0x11
94#define DPCD_LANES_EQ_DONE 0x22
95#define DPCD_SYMBOL_LOCKED 0x44
96
97#define DPCD_INTERLANE_ALIGN_DONE 0x01
98
99#define DPCD_SINK_IN_SYNC 0x03
100
101
102#define SBI_RESPONSE_MASK 0x3
103#define SBI_RESPONSE_SHIFT 0x1
104#define SBI_STAT_MASK 0x1
105#define SBI_STAT_SHIFT 0x0
106#define SBI_OPCODE_SHIFT 8
107#define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
108#define SBI_CMD_IORD 2
109#define SBI_CMD_IOWR 3
110#define SBI_CMD_CRRD 6
111#define SBI_CMD_CRWR 7
112#define SBI_ADDR_OFFSET_SHIFT 16
113#define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
114
115struct intel_vgpu_sbi_register {
116 unsigned int offset;
117 u32 value;
118};
119
120struct intel_vgpu_sbi {
121 int number;
122 struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
123};
124
125enum intel_gvt_plane_type {
126 PRIMARY_PLANE = 0,
127 CURSOR_PLANE,
128 SPRITE_PLANE,
129 MAX_PLANE
130};
131
132struct intel_vgpu_dpcd_data {
133 bool data_valid;
134 u8 data[DPCD_SIZE];
135};
136
137enum intel_vgpu_port_type {
138 GVT_CRT = 0,
139 GVT_DP_A,
140 GVT_DP_B,
141 GVT_DP_C,
142 GVT_DP_D,
143 GVT_HDMI_B,
144 GVT_HDMI_C,
145 GVT_HDMI_D,
146 GVT_PORT_MAX
147};
148
149enum intel_vgpu_edid {
150 GVT_EDID_1024_768,
151 GVT_EDID_1920_1200,
152 GVT_EDID_NUM,
153};
154
155struct intel_vgpu_port {
156
157 struct intel_vgpu_edid_data *edid;
158
159 struct intel_vgpu_dpcd_data *dpcd;
160 int type;
161 enum intel_vgpu_edid id;
162};
163
164static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
165{
166 switch (id) {
167 case GVT_EDID_1024_768:
168 return "1024x768";
169 case GVT_EDID_1920_1200:
170 return "1920x1200";
171 default:
172 return "";
173 }
174}
175
176static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
177{
178 switch (id) {
179 case GVT_EDID_1024_768:
180 return 1024;
181 case GVT_EDID_1920_1200:
182 return 1920;
183 default:
184 return 0;
185 }
186}
187
188static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
189{
190 switch (id) {
191 case GVT_EDID_1024_768:
192 return 768;
193 case GVT_EDID_1920_1200:
194 return 1200;
195 default:
196 return 0;
197 }
198}
199
200void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
201void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
202
203int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
204void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
205void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
206
207int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
208
209#endif
210