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25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/sched/clock.h>
31
32#include <drm/drm_atomic.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_dp_dual_mode_helper.h>
35#include <drm/drm_dp_mst_helper.h>
36#include <drm/drm_encoder.h>
37#include <drm/drm_fb_helper.h>
38#include <drm/drm_probe_helper.h>
39#include <drm/drm_rect.h>
40#include <drm/drm_vblank.h>
41#include <drm/i915_drm.h>
42#include <drm/i915_mei_hdcp_interface.h>
43#include <media/cec-notifier.h>
44
45#include "i915_drv.h"
46
47struct drm_printer;
48
49
50
51
52
53
54
55enum intel_output_type {
56 INTEL_OUTPUT_UNUSED = 0,
57 INTEL_OUTPUT_ANALOG = 1,
58 INTEL_OUTPUT_DVO = 2,
59 INTEL_OUTPUT_SDVO = 3,
60 INTEL_OUTPUT_LVDS = 4,
61 INTEL_OUTPUT_TVOUT = 5,
62 INTEL_OUTPUT_HDMI = 6,
63 INTEL_OUTPUT_DP = 7,
64 INTEL_OUTPUT_EDP = 8,
65 INTEL_OUTPUT_DSI = 9,
66 INTEL_OUTPUT_DDI = 10,
67 INTEL_OUTPUT_DP_MST = 11,
68};
69
70struct intel_framebuffer {
71 struct drm_framebuffer base;
72 struct intel_rotation_info rot_info;
73
74
75 struct {
76 unsigned int x, y;
77 } normal[2];
78
79 struct {
80 unsigned int x, y;
81 unsigned int pitch;
82 } rotated[2];
83};
84
85struct intel_fbdev {
86 struct drm_fb_helper helper;
87 struct intel_framebuffer *fb;
88 struct i915_vma *vma;
89 unsigned long vma_flags;
90 async_cookie_t cookie;
91 int preferred_bpp;
92
93
94 bool hpd_suspended : 1;
95
96
97
98 bool hpd_waiting : 1;
99
100
101 struct mutex hpd_lock;
102};
103
104struct intel_encoder {
105 struct drm_encoder base;
106
107 enum intel_output_type type;
108 enum port port;
109 unsigned int cloneable;
110 bool (*hotplug)(struct intel_encoder *encoder,
111 struct intel_connector *connector);
112 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
113 struct intel_crtc_state *,
114 struct drm_connector_state *);
115 int (*compute_config)(struct intel_encoder *,
116 struct intel_crtc_state *,
117 struct drm_connector_state *);
118 void (*pre_pll_enable)(struct intel_encoder *,
119 const struct intel_crtc_state *,
120 const struct drm_connector_state *);
121 void (*pre_enable)(struct intel_encoder *,
122 const struct intel_crtc_state *,
123 const struct drm_connector_state *);
124 void (*enable)(struct intel_encoder *,
125 const struct intel_crtc_state *,
126 const struct drm_connector_state *);
127 void (*disable)(struct intel_encoder *,
128 const struct intel_crtc_state *,
129 const struct drm_connector_state *);
130 void (*post_disable)(struct intel_encoder *,
131 const struct intel_crtc_state *,
132 const struct drm_connector_state *);
133 void (*post_pll_disable)(struct intel_encoder *,
134 const struct intel_crtc_state *,
135 const struct drm_connector_state *);
136 void (*update_pipe)(struct intel_encoder *,
137 const struct intel_crtc_state *,
138 const struct drm_connector_state *);
139
140
141
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
143
144
145
146
147 void (*get_config)(struct intel_encoder *,
148 struct intel_crtc_state *pipe_config);
149
150
151
152
153 void (*get_power_domains)(struct intel_encoder *encoder,
154 struct intel_crtc_state *crtc_state);
155
156
157
158
159
160 void (*suspend)(struct intel_encoder *);
161 int crtc_mask;
162 enum hpd_pin hpd_pin;
163 enum intel_display_power_domain power_domain;
164
165 const struct drm_connector *audio_connector;
166};
167
168struct intel_panel {
169 struct drm_display_mode *fixed_mode;
170 struct drm_display_mode *downclock_mode;
171
172
173 struct {
174 bool present;
175 u32 level;
176 u32 min;
177 u32 max;
178 bool enabled;
179 bool combination_mode;
180 bool active_low_pwm;
181 bool alternate_pwm_increment;
182
183
184 bool util_pin_active_low;
185 u8 controller;
186 struct pwm_device *pwm;
187
188 struct backlight_device *device;
189
190
191 int (*setup)(struct intel_connector *connector, enum pipe pipe);
192 u32 (*get)(struct intel_connector *connector);
193 void (*set)(const struct drm_connector_state *conn_state, u32 level);
194 void (*disable)(const struct drm_connector_state *conn_state);
195 void (*enable)(const struct intel_crtc_state *crtc_state,
196 const struct drm_connector_state *conn_state);
197 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
198 void (*power)(struct intel_connector *, bool enable);
199 } backlight;
200};
201
202struct intel_digital_port;
203
204enum check_link_response {
205 HDCP_LINK_PROTECTED = 0,
206 HDCP_TOPOLOGY_CHANGE,
207 HDCP_LINK_INTEGRITY_FAILURE,
208 HDCP_REAUTH_REQUEST
209};
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236
237
238struct intel_hdcp_shim {
239
240 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
241
242
243 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
244
245
246
247
248
249
250
251 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
252 u8 *bstatus);
253
254
255 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
256 bool *repeater_present);
257
258
259 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
260
261
262 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
263 bool *ksv_ready);
264
265
266 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
267 int num_downstream, u8 *ksv_fifo);
268
269
270 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
271 int i, u32 *part);
272
273
274 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
275 bool enable);
276
277
278 bool (*check_link)(struct intel_digital_port *intel_dig_port);
279
280
281 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
282 bool *hdcp_capable);
283
284
285 enum hdcp_wired_protocol protocol;
286
287
288 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
289 bool *capable);
290
291
292 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
293 void *buf, size_t size);
294
295
296 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
297 u8 msg_id, void *buf, size_t size);
298
299
300
301
302
303
304 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
305 bool is_repeater, u8 type);
306
307
308 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
309};
310
311struct intel_hdcp {
312 const struct intel_hdcp_shim *shim;
313
314 struct mutex mutex;
315 u64 value;
316 struct delayed_work check_work;
317 struct work_struct prop_work;
318
319
320 bool hdcp_encrypted;
321
322
323
324 bool hdcp2_supported;
325
326
327 bool hdcp2_encrypted;
328
329
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332
333
334 u8 content_type;
335 struct hdcp_port_data port_data;
336
337 bool is_paired;
338 bool is_repeater;
339
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343
344
345 u32 seq_num_v;
346
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352
353 u32 seq_num_m;
354
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358
359 wait_queue_head_t cp_irq_queue;
360 atomic_t cp_irq_count;
361 int cp_irq_count_cached;
362};
363
364struct intel_connector {
365 struct drm_connector base;
366
367
368
369 struct intel_encoder *encoder;
370
371
372 u32 acpi_device_id;
373
374
375
376 bool (*get_hw_state)(struct intel_connector *);
377
378
379 struct intel_panel panel;
380
381
382 struct edid *edid;
383 struct edid *detect_edid;
384
385
386
387 u8 polled;
388
389 void *port;
390
391 struct intel_dp *mst_port;
392
393
394 struct work_struct modeset_retry_work;
395
396 struct intel_hdcp hdcp;
397};
398
399struct intel_digital_connector_state {
400 struct drm_connector_state base;
401
402 enum hdmi_force_audio force_audio;
403 int broadcast_rgb;
404};
405
406#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
407
408struct dpll {
409
410 int n;
411 int m1, m2;
412 int p1, p2;
413
414 int dot;
415 int vco;
416 int m;
417 int p;
418};
419
420struct intel_atomic_state {
421 struct drm_atomic_state base;
422
423 intel_wakeref_t wakeref;
424
425 struct {
426
427
428
429
430
431 struct intel_cdclk_state logical;
432
433
434
435
436
437 struct intel_cdclk_state actual;
438
439 int force_min_cdclk;
440 bool force_min_cdclk_changed;
441
442 enum pipe pipe;
443 } cdclk;
444
445 bool dpll_set, modeset;
446
447
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449
450
451
452
453
454
455 unsigned int active_pipe_changes;
456
457 unsigned int active_crtcs;
458
459 int min_cdclk[I915_MAX_PIPES];
460
461 u8 min_voltage_level[I915_MAX_PIPES];
462
463 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
464
465
466
467
468
469 bool skip_intermediate_wm;
470
471 bool rps_interactive;
472
473
474 struct skl_ddb_values wm_results;
475
476 struct i915_sw_fence commit_ready;
477
478 struct llist_node freed;
479};
480
481struct intel_plane_state {
482 struct drm_plane_state base;
483 struct i915_ggtt_view view;
484 struct i915_vma *vma;
485 unsigned long flags;
486#define PLANE_HAS_FENCE BIT(0)
487
488 struct {
489 u32 offset;
490
491
492
493
494
495 u32 stride;
496 int x, y;
497 } color_plane[2];
498
499
500 u32 ctl;
501
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503 u32 color_ctl;
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523 int scaler_id;
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531
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533 struct intel_plane *linked_plane;
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541
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543 u32 slave;
544
545 struct drm_intel_sprite_colorkey ckey;
546};
547
548struct intel_initial_plane_config {
549 struct intel_framebuffer *fb;
550 unsigned int tiling;
551 int size;
552 u32 base;
553 u8 rotation;
554};
555
556struct intel_scaler {
557 int in_use;
558 u32 mode;
559};
560
561struct intel_crtc_scaler_state {
562#define SKL_NUM_SCALERS 2
563 struct intel_scaler scalers[SKL_NUM_SCALERS];
564
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581
582#define SKL_CRTC_INDEX 31
583 unsigned scaler_users;
584
585
586 int scaler_id;
587};
588
589
590#define I915_MODE_FLAG_INHERITED (1<<0)
591
592#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
593
594#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
595
596struct intel_pipe_wm {
597 struct intel_wm_level wm[5];
598 u32 linetime;
599 bool fbc_wm_enabled;
600 bool pipe_enabled;
601 bool sprites_enabled;
602 bool sprites_scaled;
603};
604
605struct skl_plane_wm {
606 struct skl_wm_level wm[8];
607 struct skl_wm_level uv_wm[8];
608 struct skl_wm_level trans_wm;
609 bool is_planar;
610};
611
612struct skl_pipe_wm {
613 struct skl_plane_wm planes[I915_MAX_PLANES];
614 u32 linetime;
615};
616
617enum vlv_wm_level {
618 VLV_WM_LEVEL_PM2,
619 VLV_WM_LEVEL_PM5,
620 VLV_WM_LEVEL_DDR_DVFS,
621 NUM_VLV_WM_LEVELS,
622};
623
624struct vlv_wm_state {
625 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
626 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
627 u8 num_levels;
628 bool cxsr;
629};
630
631struct vlv_fifo_state {
632 u16 plane[I915_MAX_PLANES];
633};
634
635enum g4x_wm_level {
636 G4X_WM_LEVEL_NORMAL,
637 G4X_WM_LEVEL_SR,
638 G4X_WM_LEVEL_HPLL,
639 NUM_G4X_WM_LEVELS,
640};
641
642struct g4x_wm_state {
643 struct g4x_pipe_wm wm;
644 struct g4x_sr_wm sr;
645 struct g4x_sr_wm hpll;
646 bool cxsr;
647 bool hpll_en;
648 bool fbc_en;
649};
650
651struct intel_crtc_wm_state {
652 union {
653 struct {
654
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660
661 struct intel_pipe_wm intermediate;
662
663
664
665
666
667 struct intel_pipe_wm optimal;
668 } ilk;
669
670 struct {
671
672 struct skl_pipe_wm optimal;
673 struct skl_ddb_entry ddb;
674 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
675 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
676 } skl;
677
678 struct {
679
680 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
681
682 struct vlv_wm_state intermediate;
683
684 struct vlv_wm_state optimal;
685
686 struct vlv_fifo_state fifo_state;
687 } vlv;
688
689 struct {
690
691 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
692
693 struct g4x_wm_state intermediate;
694
695 struct g4x_wm_state optimal;
696 } g4x;
697 };
698
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702
703
704
705 bool need_postvbl_update;
706};
707
708enum intel_output_format {
709 INTEL_OUTPUT_FORMAT_INVALID,
710 INTEL_OUTPUT_FORMAT_RGB,
711 INTEL_OUTPUT_FORMAT_YCBCR420,
712 INTEL_OUTPUT_FORMAT_YCBCR444,
713};
714
715struct intel_crtc_state {
716 struct drm_crtc_state base;
717
718
719
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724
725
726#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
727 unsigned long quirks;
728
729 unsigned fb_bits;
730 bool update_pipe;
731 bool disable_cxsr;
732 bool update_wm_pre, update_wm_post;
733 bool fb_changed;
734 bool fifo_changed;
735
736
737
738
739 int pipe_src_w, pipe_src_h;
740
741
742
743
744
745 unsigned int pixel_rate;
746
747
748
749 bool has_pch_encoder;
750
751
752 bool has_infoframe;
753
754
755
756
757 enum transcoder cpu_transcoder;
758
759
760
761
762
763 bool limited_color_range;
764
765
766
767
768 unsigned int output_types;
769
770
771 bool has_hdmi_sink;
772
773
774
775 bool has_audio;
776
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781 bool dither;
782
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787
788
789 bool dither_force_disable;
790
791
792 bool clock_set;
793
794
795
796 bool sdvo_tv_clock;
797
798
799
800
801
802
803 bool bw_constrained;
804
805
806
807 struct dpll dpll;
808
809
810 struct intel_shared_dpll *shared_dpll;
811
812
813 struct intel_dpll_hw_state dpll_hw_state;
814
815
816 struct {
817 u32 ctrl, div;
818 } dsi_pll;
819
820 int pipe_bpp;
821 struct intel_link_m_n dp_m_n;
822
823
824 struct intel_link_m_n dp_m2_n2;
825 bool has_drrs;
826
827 bool has_psr;
828 bool has_psr2;
829
830
831
832
833
834
835 int port_clock;
836
837
838 unsigned pixel_multiplier;
839
840 u8 lane_count;
841
842
843
844
845
846 u8 lane_lat_optim_mask;
847
848
849 u8 min_voltage_level;
850
851
852 struct {
853 u32 control;
854 u32 pgm_ratios;
855 u32 lvds_border_bits;
856 } gmch_pfit;
857
858
859 struct {
860 u32 pos;
861 u32 size;
862 bool enabled;
863 bool force_thru;
864 } pch_pfit;
865
866
867 int fdi_lanes;
868 struct intel_link_m_n fdi_m_n;
869
870 bool ips_enabled;
871
872 bool crc_enabled;
873
874 bool enable_fbc;
875
876 bool double_wide;
877
878 int pbn;
879
880 struct intel_crtc_scaler_state scaler_state;
881
882
883 enum pipe hsw_workaround_pipe;
884
885
886 bool disable_lp_wm;
887
888 struct intel_crtc_wm_state wm;
889
890 u32 data_rate[I915_MAX_PLANES];
891
892
893 u32 gamma_mode;
894
895 union {
896
897 u32 csc_mode;
898
899
900 u32 cgm_mode;
901 };
902
903
904 u8 active_planes;
905 u8 nv12_planes;
906 u8 c8_planes;
907
908
909 u8 update_planes;
910
911 struct {
912 u32 enable;
913 u32 gcp;
914 union hdmi_infoframe avi;
915 union hdmi_infoframe spd;
916 union hdmi_infoframe hdmi;
917 union hdmi_infoframe drm;
918 } infoframes;
919
920
921 bool hdmi_scrambling;
922
923
924 bool hdmi_high_tmds_clock_ratio;
925
926
927 enum intel_output_format output_format;
928
929
930 bool lspcon_downsampling;
931
932
933 bool gamma_enable;
934
935
936 bool csc_enable;
937
938
939 struct {
940 bool compression_enable;
941 bool dsc_split;
942 u16 compressed_bpp;
943 u8 slice_count;
944 } dsc_params;
945 struct drm_dsc_config dp_dsc_cfg;
946
947
948 bool fec_enable;
949};
950
951struct intel_crtc {
952 struct drm_crtc base;
953 enum pipe pipe;
954
955
956
957
958
959 bool active;
960 u8 plane_ids_mask;
961 unsigned long long enabled_power_domains;
962 struct intel_overlay *overlay;
963
964 struct intel_crtc_state *config;
965
966
967 bool cpu_fifo_underrun_disabled;
968 bool pch_fifo_underrun_disabled;
969
970
971 struct {
972
973 union {
974 struct intel_pipe_wm ilk;
975 struct vlv_wm_state vlv;
976 struct g4x_wm_state g4x;
977 } active;
978 } wm;
979
980 int scanline_offset;
981
982 struct {
983 unsigned start_vbl_count;
984 ktime_t start_vbl_time;
985 int min_vbl, max_vbl;
986 int scanline_start;
987 } debug;
988
989
990 int num_scalers;
991};
992
993struct intel_plane {
994 struct drm_plane base;
995 enum i9xx_plane_id i9xx_plane;
996 enum plane_id id;
997 enum pipe pipe;
998 bool has_fbc;
999 bool has_ccs;
1000 u32 frontbuffer_bit;
1001
1002 struct {
1003 u32 base, cntl, size;
1004 } cursor;
1005
1006
1007
1008
1009
1010
1011
1012 unsigned int (*max_stride)(struct intel_plane *plane,
1013 u32 pixel_format, u64 modifier,
1014 unsigned int rotation);
1015 void (*update_plane)(struct intel_plane *plane,
1016 const struct intel_crtc_state *crtc_state,
1017 const struct intel_plane_state *plane_state);
1018 void (*update_slave)(struct intel_plane *plane,
1019 const struct intel_crtc_state *crtc_state,
1020 const struct intel_plane_state *plane_state);
1021 void (*disable_plane)(struct intel_plane *plane,
1022 const struct intel_crtc_state *crtc_state);
1023 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1024 int (*check_plane)(struct intel_crtc_state *crtc_state,
1025 struct intel_plane_state *plane_state);
1026};
1027
1028struct intel_watermark_params {
1029 u16 fifo_size;
1030 u16 max_wm;
1031 u8 default_wm;
1032 u8 guard_size;
1033 u8 cacheline_size;
1034};
1035
1036struct cxsr_latency {
1037 bool is_desktop : 1;
1038 bool is_ddr3 : 1;
1039 u16 fsb_freq;
1040 u16 mem_freq;
1041 u16 display_sr;
1042 u16 display_hpll_disable;
1043 u16 cursor_sr;
1044 u16 cursor_hpll_disable;
1045};
1046
1047#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1048#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1049#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1050#define to_intel_connector(x) container_of(x, struct intel_connector, base)
1051#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1052#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1053#define to_intel_plane(x) container_of(x, struct intel_plane, base)
1054#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1055#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1056
1057struct intel_hdmi {
1058 i915_reg_t hdmi_reg;
1059 int ddc_bus;
1060 struct {
1061 enum drm_dp_dual_mode_type type;
1062 int max_tmds_clock;
1063 } dp_dual_mode;
1064 bool has_hdmi_sink;
1065 bool has_audio;
1066 struct intel_connector *attached_connector;
1067 struct cec_notifier *cec_notifier;
1068};
1069
1070struct intel_dp_mst_encoder;
1071#define DP_MAX_DOWNSTREAM_PORTS 0x10
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087enum link_m_n_set {
1088
1089 M1_N1 = 0,
1090 M2_N2
1091};
1092
1093struct intel_dp_compliance_data {
1094 unsigned long edid;
1095 u8 video_pattern;
1096 u16 hdisplay, vdisplay;
1097 u8 bpc;
1098};
1099
1100struct intel_dp_compliance {
1101 unsigned long test_type;
1102 struct intel_dp_compliance_data test_data;
1103 bool test_active;
1104 int test_link_rate;
1105 u8 test_lane_count;
1106};
1107
1108struct intel_dp {
1109 i915_reg_t output_reg;
1110 u32 DP;
1111 int link_rate;
1112 u8 lane_count;
1113 u8 sink_count;
1114 bool link_mst;
1115 bool link_trained;
1116 bool has_audio;
1117 bool reset_link_params;
1118 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1119 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1120 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1121 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1122 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1123 u8 fec_capable;
1124
1125 int num_source_rates;
1126 const int *source_rates;
1127
1128 int num_sink_rates;
1129 int sink_rates[DP_MAX_SUPPORTED_RATES];
1130 bool use_rate_select;
1131
1132 int num_common_rates;
1133 int common_rates[DP_MAX_SUPPORTED_RATES];
1134
1135 int max_link_lane_count;
1136
1137 int max_link_rate;
1138
1139 struct drm_dp_desc desc;
1140 struct drm_dp_aux aux;
1141 u8 train_set[4];
1142 int panel_power_up_delay;
1143 int panel_power_down_delay;
1144 int panel_power_cycle_delay;
1145 int backlight_on_delay;
1146 int backlight_off_delay;
1147 struct delayed_work panel_vdd_work;
1148 bool want_panel_vdd;
1149 unsigned long last_power_on;
1150 unsigned long last_backlight_off;
1151 ktime_t panel_power_off_time;
1152
1153 struct notifier_block edp_notifier;
1154
1155
1156
1157
1158
1159 enum pipe pps_pipe;
1160
1161
1162
1163
1164
1165 enum pipe active_pipe;
1166
1167
1168
1169
1170 bool pps_reset;
1171 struct edp_power_seq pps_delays;
1172
1173 bool can_mst;
1174 bool is_mst;
1175 int active_mst_links;
1176
1177 struct intel_connector *attached_connector;
1178
1179
1180 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1181 struct drm_dp_mst_topology_mgr mst_mgr;
1182
1183 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1184
1185
1186
1187
1188 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1189 u32 aux_clock_divider);
1190
1191 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1192 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1193
1194
1195 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1196
1197
1198 struct intel_dp_compliance compliance;
1199
1200
1201 bool force_dsc_en;
1202};
1203
1204enum lspcon_vendor {
1205 LSPCON_VENDOR_MCA,
1206 LSPCON_VENDOR_PARADE
1207};
1208
1209struct intel_lspcon {
1210 bool active;
1211 enum drm_lspcon_mode mode;
1212 enum lspcon_vendor vendor;
1213};
1214
1215struct intel_digital_port {
1216 struct intel_encoder base;
1217 u32 saved_port_bits;
1218 struct intel_dp dp;
1219 struct intel_hdmi hdmi;
1220 struct intel_lspcon lspcon;
1221 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1222 bool release_cl2_override;
1223 u8 max_lanes;
1224
1225 enum aux_ch aux_ch;
1226 enum intel_display_power_domain ddi_io_power_domain;
1227 bool tc_legacy_port:1;
1228 enum tc_port_type tc_type;
1229
1230 void (*write_infoframe)(struct intel_encoder *encoder,
1231 const struct intel_crtc_state *crtc_state,
1232 unsigned int type,
1233 const void *frame, ssize_t len);
1234 void (*read_infoframe)(struct intel_encoder *encoder,
1235 const struct intel_crtc_state *crtc_state,
1236 unsigned int type,
1237 void *frame, ssize_t len);
1238 void (*set_infoframes)(struct intel_encoder *encoder,
1239 bool enable,
1240 const struct intel_crtc_state *crtc_state,
1241 const struct drm_connector_state *conn_state);
1242 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1243 const struct intel_crtc_state *pipe_config);
1244};
1245
1246struct intel_dp_mst_encoder {
1247 struct intel_encoder base;
1248 enum pipe pipe;
1249 struct intel_digital_port *primary;
1250 struct intel_connector *connector;
1251};
1252
1253static inline enum dpio_channel
1254vlv_dport_to_channel(struct intel_digital_port *dport)
1255{
1256 switch (dport->base.port) {
1257 case PORT_B:
1258 case PORT_D:
1259 return DPIO_CH0;
1260 case PORT_C:
1261 return DPIO_CH1;
1262 default:
1263 BUG();
1264 }
1265}
1266
1267static inline enum dpio_phy
1268vlv_dport_to_phy(struct intel_digital_port *dport)
1269{
1270 switch (dport->base.port) {
1271 case PORT_B:
1272 case PORT_C:
1273 return DPIO_PHY0;
1274 case PORT_D:
1275 return DPIO_PHY1;
1276 default:
1277 BUG();
1278 }
1279}
1280
1281static inline enum dpio_channel
1282vlv_pipe_to_channel(enum pipe pipe)
1283{
1284 switch (pipe) {
1285 case PIPE_A:
1286 case PIPE_C:
1287 return DPIO_CH0;
1288 case PIPE_B:
1289 return DPIO_CH1;
1290 default:
1291 BUG();
1292 }
1293}
1294
1295static inline struct intel_crtc *
1296intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1297{
1298 return dev_priv->pipe_to_crtc_mapping[pipe];
1299}
1300
1301static inline struct intel_crtc *
1302intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1303{
1304 return dev_priv->plane_to_crtc_mapping[plane];
1305}
1306
1307struct intel_load_detect_pipe {
1308 struct drm_atomic_state *restore_state;
1309};
1310
1311static inline struct intel_encoder *
1312intel_attached_encoder(struct drm_connector *connector)
1313{
1314 return to_intel_connector(connector)->encoder;
1315}
1316
1317static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1318{
1319 switch (encoder->type) {
1320 case INTEL_OUTPUT_DDI:
1321 case INTEL_OUTPUT_DP:
1322 case INTEL_OUTPUT_EDP:
1323 case INTEL_OUTPUT_HDMI:
1324 return true;
1325 default:
1326 return false;
1327 }
1328}
1329
1330static inline struct intel_digital_port *
1331enc_to_dig_port(struct drm_encoder *encoder)
1332{
1333 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1334
1335 if (intel_encoder_is_dig_port(intel_encoder))
1336 return container_of(encoder, struct intel_digital_port,
1337 base.base);
1338 else
1339 return NULL;
1340}
1341
1342static inline struct intel_digital_port *
1343conn_to_dig_port(struct intel_connector *connector)
1344{
1345 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1346}
1347
1348static inline struct intel_dp_mst_encoder *
1349enc_to_mst(struct drm_encoder *encoder)
1350{
1351 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1352}
1353
1354static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1355{
1356 return &enc_to_dig_port(encoder)->dp;
1357}
1358
1359static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1360{
1361 switch (encoder->type) {
1362 case INTEL_OUTPUT_DP:
1363 case INTEL_OUTPUT_EDP:
1364 return true;
1365 case INTEL_OUTPUT_DDI:
1366
1367 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1368 default:
1369 return false;
1370 }
1371}
1372
1373static inline struct intel_lspcon *
1374enc_to_intel_lspcon(struct drm_encoder *encoder)
1375{
1376 return &enc_to_dig_port(encoder)->lspcon;
1377}
1378
1379static inline struct intel_digital_port *
1380dp_to_dig_port(struct intel_dp *intel_dp)
1381{
1382 return container_of(intel_dp, struct intel_digital_port, dp);
1383}
1384
1385static inline struct intel_lspcon *
1386dp_to_lspcon(struct intel_dp *intel_dp)
1387{
1388 return &dp_to_dig_port(intel_dp)->lspcon;
1389}
1390
1391static inline struct drm_i915_private *
1392dp_to_i915(struct intel_dp *intel_dp)
1393{
1394 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1395}
1396
1397static inline struct intel_digital_port *
1398hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1399{
1400 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1401}
1402
1403static inline struct intel_plane_state *
1404intel_atomic_get_plane_state(struct intel_atomic_state *state,
1405 struct intel_plane *plane)
1406{
1407 struct drm_plane_state *ret =
1408 drm_atomic_get_plane_state(&state->base, &plane->base);
1409
1410 if (IS_ERR(ret))
1411 return ERR_CAST(ret);
1412
1413 return to_intel_plane_state(ret);
1414}
1415
1416static inline struct intel_plane_state *
1417intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1418 struct intel_plane *plane)
1419{
1420 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1421 &plane->base));
1422}
1423
1424static inline struct intel_plane_state *
1425intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1426 struct intel_plane *plane)
1427{
1428 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1429 &plane->base));
1430}
1431
1432static inline struct intel_crtc_state *
1433intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1434 struct intel_crtc *crtc)
1435{
1436 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1437 &crtc->base));
1438}
1439
1440static inline struct intel_crtc_state *
1441intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1442 struct intel_crtc *crtc)
1443{
1444 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1445 &crtc->base));
1446}
1447
1448
1449void intel_plane_destroy(struct drm_plane *plane);
1450void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1451void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1452enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1453int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1454int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1455 const char *name, u32 reg, int ref_freq);
1456int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1457 const char *name, u32 reg);
1458void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1459void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1460void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1461unsigned int intel_fb_xy_to_linear(int x, int y,
1462 const struct intel_plane_state *state,
1463 int plane);
1464unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1465 int color_plane, unsigned int height);
1466void intel_add_fb_offsets(int *x, int *y,
1467 const struct intel_plane_state *state, int plane);
1468unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1469unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
1470bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1471int intel_display_suspend(struct drm_device *dev);
1472void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1473void intel_encoder_destroy(struct drm_encoder *encoder);
1474struct drm_display_mode *
1475intel_encoder_current_mode(struct intel_encoder *encoder);
1476bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1477bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1478enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1479 enum port port);
1480int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *file_priv);
1482enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1483 enum pipe pipe);
1484static inline bool
1485intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1486 enum intel_output_type type)
1487{
1488 return crtc_state->output_types & (1 << type);
1489}
1490static inline bool
1491intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1492{
1493 return crtc_state->output_types &
1494 ((1 << INTEL_OUTPUT_DP) |
1495 (1 << INTEL_OUTPUT_DP_MST) |
1496 (1 << INTEL_OUTPUT_EDP));
1497}
1498static inline void
1499intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 drm_wait_one_vblank(&dev_priv->drm, pipe);
1502}
1503static inline void
1504intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1505{
1506 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1507
1508 if (crtc->active)
1509 intel_wait_for_vblank(dev_priv, pipe);
1510}
1511
1512u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1513
1514int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1515void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1516 struct intel_digital_port *dport,
1517 unsigned int expected_mask);
1518int intel_get_load_detect_pipe(struct drm_connector *connector,
1519 const struct drm_display_mode *mode,
1520 struct intel_load_detect_pipe *old,
1521 struct drm_modeset_acquire_ctx *ctx);
1522void intel_release_load_detect_pipe(struct drm_connector *connector,
1523 struct intel_load_detect_pipe *old,
1524 struct drm_modeset_acquire_ctx *ctx);
1525struct i915_vma *
1526intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1527 const struct i915_ggtt_view *view,
1528 bool uses_fence,
1529 unsigned long *out_flags);
1530void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1531struct drm_framebuffer *
1532intel_framebuffer_create(struct drm_i915_gem_object *obj,
1533 struct drm_mode_fb_cmd2 *mode_cmd);
1534int intel_prepare_plane_fb(struct drm_plane *plane,
1535 struct drm_plane_state *new_state);
1536void intel_cleanup_plane_fb(struct drm_plane *plane,
1537 struct drm_plane_state *old_state);
1538
1539void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1540 enum pipe pipe);
1541
1542int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1543 const struct dpll *dpll);
1544void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1545int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1546bool intel_fuzzy_clock_check(int clock1, int clock2);
1547
1548
1549void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1550 enum pipe pipe);
1551void assert_pll(struct drm_i915_private *dev_priv,
1552 enum pipe pipe, bool state);
1553#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1554#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1555void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1556#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1557#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1558void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1559 enum pipe pipe, bool state);
1560#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1561#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1562void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1563#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1564#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1565void intel_prepare_reset(struct drm_i915_private *dev_priv);
1566void intel_finish_reset(struct drm_i915_private *dev_priv);
1567void intel_dp_get_m_n(struct intel_crtc *crtc,
1568 struct intel_crtc_state *pipe_config);
1569void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1570 enum link_m_n_set m_n);
1571void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
1572 const struct intel_crtc_state *crtc_state);
1573int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1574bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1575 struct dpll *best_clock);
1576int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1577
1578bool intel_crtc_active(struct intel_crtc *crtc);
1579bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1580void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1581void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1582enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1583enum intel_display_power_domain
1584intel_aux_power_domain(struct intel_digital_port *dig_port);
1585void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1586 struct intel_crtc_state *pipe_config);
1587void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1588 struct intel_crtc_state *crtc_state);
1589
1590u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1591int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1592int skl_max_scale(const struct intel_crtc_state *crtc_state,
1593 u32 pixel_format);
1594
1595static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1596{
1597 return i915_ggtt_offset(state->vma);
1598}
1599
1600u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1601 const struct intel_plane_state *plane_state);
1602u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1603u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1604 const struct intel_plane_state *plane_state);
1605u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1606u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1607 int plane);
1608int skl_check_plane_surface(struct intel_plane_state *plane_state);
1609int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1610int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1611unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1612 u32 pixel_format, u64 modifier,
1613 unsigned int rotation);
1614int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
1615
1616#endif
1617