1/* 2 * Copyright © 2016-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef _INTEL_GUC_CT_H_ 25#define _INTEL_GUC_CT_H_ 26 27struct intel_guc; 28struct i915_vma; 29 30#include "intel_guc_fwif.h" 31 32/** 33 * DOC: Command Transport (CT). 34 * 35 * Buffer based command transport is a replacement for MMIO based mechanism. 36 * It can be used to perform both host-2-guc and guc-to-host communication. 37 */ 38 39/** Represents single command transport buffer. 40 * 41 * A single command transport buffer consists of two parts, the header 42 * record (command transport buffer descriptor) and the actual buffer which 43 * holds the commands. 44 * 45 * @desc: pointer to the buffer descriptor 46 * @cmds: pointer to the commands buffer 47 */ 48struct intel_guc_ct_buffer { 49 struct guc_ct_buffer_desc *desc; 50 u32 *cmds; 51}; 52 53/** Represents pair of command transport buffers. 54 * 55 * Buffers go in pairs to allow bi-directional communication. 56 * To simplify the code we place both of them in the same vma. 57 * Buffers from the same pair must share unique owner id. 58 * 59 * @vma: pointer to the vma with pair of CT buffers 60 * @ctbs: buffers for sending(0) and receiving(1) commands 61 * @owner: unique identifier 62 * @next_fence: fence to be used with next send command 63 */ 64struct intel_guc_ct_channel { 65 struct i915_vma *vma; 66 struct intel_guc_ct_buffer ctbs[2]; 67 u32 owner; 68 u32 next_fence; 69 bool enabled; 70}; 71 72/** Holds all command transport channels. 73 * 74 * @host_channel: main channel used by the host 75 */ 76struct intel_guc_ct { 77 struct intel_guc_ct_channel host_channel; 78 /* other channels are tbd */ 79 80 /** @lock: protects pending requests list */ 81 spinlock_t lock; 82 83 /** @pending_requests: list of requests waiting for response */ 84 struct list_head pending_requests; 85 86 /** @incoming_requests: list of incoming requests */ 87 struct list_head incoming_requests; 88 89 /** @worker: worker for handling incoming requests */ 90 struct work_struct worker; 91}; 92 93void intel_guc_ct_init_early(struct intel_guc_ct *ct); 94int intel_guc_ct_init(struct intel_guc_ct *ct); 95void intel_guc_ct_fini(struct intel_guc_ct *ct); 96int intel_guc_ct_enable(struct intel_guc_ct *ct); 97void intel_guc_ct_disable(struct intel_guc_ct *ct); 98 99static inline void intel_guc_ct_stop(struct intel_guc_ct *ct) 100{ 101 ct->host_channel.enabled = false; 102} 103 104#endif /* _INTEL_GUC_CT_H_ */ 105