LXR linux/drivers/gpu/drm/i915/intel_guc

   1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *    Vinit Azad <vinit.azad@intel.com>
  25 *    Ben Widawsky <ben@bwidawsk.net>
  26 *    Dave Gordon <david.s.gordon@intel.com>
  27 *    Alex Dai <yu.dai@intel.com>
  28 */
  29
  30#include "intel_guc_fw.h"
  31#include "i915_drv.h"
  32
  33#define __MAKE_GUC_FW_PATH(KEY) \
  34        "i915/" \
  35        __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
  36        __stringify(KEY##_GUC_FW_MAJOR) "." \
  37        __stringify(KEY##_GUC_FW_MINOR) "." \
  38        __stringify(KEY##_GUC_FW_PATCH) ".bin"
  39
  40#define SKL_GUC_FW_PREFIX skl
  41#define SKL_GUC_FW_MAJOR 32
  42#define SKL_GUC_FW_MINOR 0
  43#define SKL_GUC_FW_PATCH 3
  44#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
  45MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
  46
  47#define BXT_GUC_FW_PREFIX bxt
  48#define BXT_GUC_FW_MAJOR 32
  49#define BXT_GUC_FW_MINOR 0
  50#define BXT_GUC_FW_PATCH 3
  51#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
  52MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
  53
  54#define KBL_GUC_FW_PREFIX kbl
  55#define KBL_GUC_FW_MAJOR 32
  56#define KBL_GUC_FW_MINOR 0
  57#define KBL_GUC_FW_PATCH 3
  58#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
  59MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
  60
  61#define GLK_GUC_FW_PREFIX glk
  62#define GLK_GUC_FW_MAJOR 32
  63#define GLK_GUC_FW_MINOR 0
  64#define GLK_GUC_FW_PATCH 3
  65#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
  66MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
  67
  68#define ICL_GUC_FW_PREFIX icl
  69#define ICL_GUC_FW_MAJOR 32
  70#define ICL_GUC_FW_MINOR 0
  71#define ICL_GUC_FW_PATCH 3
  72#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
  73MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
  74
  75static void guc_fw_select(struct intel_uc_fw *guc_fw)
  76{
  77        struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
  78        struct drm_i915_private *i915 = guc_to_i915(guc);
  79
  80        GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
  81
  82        if (!HAS_GUC(i915))
  83                return;
  84
  85        if (i915_modparams.guc_firmware_path) {
  86                guc_fw->path = i915_modparams.guc_firmware_path;
  87                guc_fw->major_ver_wanted = 0;
  88                guc_fw->minor_ver_wanted = 0;
  89        } else if (IS_ICELAKE(i915)) {
  90                guc_fw->path = ICL_GUC_FIRMWARE_PATH;
  91                guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
  92                guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
  93        } else if (IS_GEMINILAKE(i915)) {
  94                guc_fw->path = GLK_GUC_FIRMWARE_PATH;
  95                guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
  96                guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
  97        } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
  98                guc_fw->path = KBL_GUC_FIRMWARE_PATH;
  99                guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
 100                guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
 101        } else if (IS_BROXTON(i915)) {
 102                guc_fw->path = BXT_GUC_FIRMWARE_PATH;
 103                guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
 104                guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
 105        } else if (IS_SKYLAKE(i915)) {
 106                guc_fw->path = SKL_GUC_FIRMWARE_PATH;
 107                guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
 108                guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
 109        }
 110}
 111
 112/**
 113 * intel_guc_fw_init_early() - initializes GuC firmware struct
 114 * @guc: intel_guc struct
 115 *
 116 * On platforms with GuC selects firmware for uploading
 117 */
 118void intel_guc_fw_init_early(struct intel_guc *guc)
 119{
 120        struct intel_uc_fw *guc_fw = &guc->fw;
 121
 122        intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
 123        guc_fw_select(guc_fw);
 124}
 125
 126static void guc_prepare_xfer(struct intel_guc *guc)
 127{
 128        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 129
 130        /* Must program this register before loading the ucode with DMA */
 131        I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
 132                                     GUC_ENABLE_READ_CACHE_LOGIC |
 133                                     GUC_ENABLE_MIA_CACHING |
 134                                     GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
 135                                     GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
 136                                     GUC_ENABLE_MIA_CLOCK_GATING);
 137
 138        if (IS_GEN9_LP(dev_priv))
 139                I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 140        else
 141                I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 142
 143        if (IS_GEN(dev_priv, 9)) {
 144                /* DOP Clock Gating Enable for GuC clocks */
 145                I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 146                                            I915_READ(GEN7_MISCCPCTL)));
 147
 148                /* allows for 5us (in 10ns units) before GT can go to RC6 */
 149                I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 150        }
 151}
 152
 153/* Copy RSA signature from the fw image to HW for verification */
 154static void guc_xfer_rsa(struct intel_guc *guc)
 155{
 156        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 157        struct intel_uc_fw *fw = &guc->fw;
 158        struct sg_table *pages = fw->obj->mm.pages;
 159        u32 rsa[UOS_RSA_SCRATCH_COUNT];
 160        int i;
 161
 162        sg_pcopy_to_buffer(pages->sgl, pages->nents,
 163                           rsa, sizeof(rsa), fw->rsa_offset);
 164
 165        for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
 166                I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 167}
 168
 169static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
 170{
 171        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 172
 173        /* Did we complete the xfer? */
 174        *status = I915_READ(DMA_CTRL);
 175        return !(*status & START_DMA);
 176}
 177
 178/*
 179 * Read the GuC status register (GUC_STATUS) and store it in the
 180 * specified location; then return a boolean indicating whether
 181 * the value matches either of two values representing completion
 182 * of the GuC boot process.
 183 *
 184 * This is used for polling the GuC status in a wait_for()
 185 * loop below.
 186 */
 187static inline bool guc_ready(struct intel_guc *guc, u32 *status)
 188{
 189        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 190        u32 val = I915_READ(GUC_STATUS);
 191        u32 uk_val = val & GS_UKERNEL_MASK;
 192
 193        *status = val;
 194        return (uk_val == GS_UKERNEL_READY) ||
 195                ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
 196}
 197
 198static int guc_wait_ucode(struct intel_guc *guc)
 199{
 200        u32 status;
 201        int ret;
 202
 203        /*
 204         * Wait for the GuC to start up.
 205         * NB: Docs recommend not using the interrupt for completion.
 206         * Measurements indicate this should take no more than 20ms, so a
 207         * timeout here indicates that the GuC has failed and is unusable.
 208         * (Higher levels of the driver may decide to reset the GuC and
 209         * attempt the ucode load again if this happens.)
 210         */
 211        ret = wait_for(guc_ready(guc, &status), 100);
 212        DRM_DEBUG_DRIVER("GuC status %#x\n", status);
 213
 214        if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 215                DRM_ERROR("GuC firmware signature verification failed\n");
 216                ret = -ENOEXEC;
 217        }
 218
 219        if (ret == 0 && !guc_xfer_completed(guc, &status)) {
 220                DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
 221                          status);
 222                ret = -ENXIO;
 223        }
 224
 225        return ret;
 226}
 227
 228/*
 229 * Transfer the firmware image to RAM for execution by the microcontroller.
 230 *
 231 * Architecturally, the DMA engine is bidirectional, and can potentially even
 232 * transfer between GTT locations. This functionality is left out of the API
 233 * for now as there is no need for it.
 234 */
 235static int guc_xfer_ucode(struct intel_guc *guc)
 236{
 237        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 238        struct intel_uc_fw *guc_fw = &guc->fw;
 239        unsigned long offset;
 240
 241        /*
 242         * The header plus uCode will be copied to WOPCM via DMA, excluding any
 243         * other components
 244         */
 245        I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 246
 247        /* Set the source address for the new blob */
 248        offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
 249        I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 250        I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 251
 252        /*
 253         * Set the DMA destination. Current uCode expects the code to be
 254         * loaded at 8k; locations below this are used for the stack.
 255         */
 256        I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 257        I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 258
 259        /* Finally start the DMA */
 260        I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 261
 262        return guc_wait_ucode(guc);
 263}
 264/*
 265 * Load the GuC firmware blob into the MinuteIA.
 266 */
 267static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
 268{
 269        struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
 270        struct drm_i915_private *dev_priv = guc_to_i915(guc);
 271        int ret;
 272
 273        GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 274
 275        intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 276
 277        guc_prepare_xfer(guc);
 278
 279        /*
 280         * Note that GuC needs the CSS header plus uKernel code to be copied
 281         * by the DMA engine in one operation, whereas the RSA signature is
 282         * loaded via MMIO.
 283         */
 284        guc_xfer_rsa(guc);
 285
 286        ret = guc_xfer_ucode(guc);
 287
 288        intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 289
 290        return ret;
 291}
 292
 293/**
 294 * intel_guc_fw_upload() - load GuC uCode to device
 295 * @guc: intel_guc structure
 296 *
 297 * Called from intel_uc_init_hw() during driver load, resume from sleep and
 298 * after a GPU reset.
 299 *
 300 * The firmware image should have already been fetched into memory, so only
 301 * check that fetch succeeded, and then transfer the image to the h/w.
 302 *
 303 * Return:      non-zero code on error
 304 */
 305int intel_guc_fw_upload(struct intel_guc *guc)
 306{
 307        return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
 308}
 309