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23#ifndef _INTEL_GUC_FWIF_H
24#define _INTEL_GUC_FWIF_H
25
26#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
27#define GUC_CLIENT_PRIORITY_HIGH 1
28#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
29#define GUC_CLIENT_PRIORITY_NORMAL 3
30#define GUC_CLIENT_PRIORITY_NUM 4
31
32#define GUC_MAX_STAGE_DESCRIPTORS 1024
33#define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
34
35#define GUC_RENDER_ENGINE 0
36#define GUC_VIDEO_ENGINE 1
37#define GUC_BLITTER_ENGINE 2
38#define GUC_VIDEOENHANCE_ENGINE 3
39#define GUC_VIDEO_ENGINE2 4
40#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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46
47#define GUC_MAX_ENGINE_CLASSES 5
48#define GUC_MAX_INSTANCES_PER_CLASS 4
49
50#define GUC_DOORBELL_INVALID 256
51
52#define GUC_DB_SIZE (PAGE_SIZE)
53#define GUC_WQ_SIZE (PAGE_SIZE * 2)
54
55
56#define WQ_STATUS_ACTIVE 1
57#define WQ_STATUS_SUSPENDED 2
58#define WQ_STATUS_CMD_ERROR 3
59#define WQ_STATUS_ENGINE_ID_NOT_USED 4
60#define WQ_STATUS_SUSPENDED_FROM_RESET 5
61#define WQ_TYPE_SHIFT 0
62#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
63#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
64#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
65#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
66#define WQ_TARGET_SHIFT 10
67#define WQ_LEN_SHIFT 16
68#define WQ_NO_WCFLUSH_WAIT (1 << 27)
69#define WQ_PRESENT_WORKLOAD (1 << 28)
70
71#define WQ_RING_TAIL_SHIFT 20
72#define WQ_RING_TAIL_MAX 0x7FF
73#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
74
75#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
76#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
77#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
78#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
79#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
80#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
81#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
82#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
83
84
85#define GUC_CTL_CTXINFO 0
86#define GUC_CTL_CTXNUM_IN16_SHIFT 0
87#define GUC_CTL_BASE_ADDR_SHIFT 12
88
89#define GUC_CTL_LOG_PARAMS 1
90#define GUC_LOG_VALID (1 << 0)
91#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
92#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
93#define GUC_LOG_CRASH_SHIFT 4
94#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
95#define GUC_LOG_DPC_SHIFT 6
96#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
97#define GUC_LOG_ISR_SHIFT 9
98#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
99#define GUC_LOG_BUF_ADDR_SHIFT 12
100
101#define GUC_CTL_WA 2
102#define GUC_CTL_FEATURE 3
103#define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
104
105#define GUC_CTL_DEBUG 4
106#define GUC_LOG_VERBOSITY_SHIFT 0
107#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
108#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
109#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
110#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
111
112#define GUC_LOG_VERBOSITY_MIN 0
113#define GUC_LOG_VERBOSITY_MAX 3
114#define GUC_LOG_VERBOSITY_MASK 0x0000000f
115#define GUC_LOG_DESTINATION_MASK (3 << 4)
116#define GUC_LOG_DISABLED (1 << 6)
117#define GUC_PROFILE_ENABLED (1 << 7)
118
119#define GUC_CTL_ADS 5
120#define GUC_ADS_ADDR_SHIFT 1
121#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
122
123#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2)
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163struct uc_css_header {
164 u32 module_type;
165
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167 u32 header_size_dw;
168 u32 header_version;
169 u32 module_id;
170 u32 module_vendor;
171 u32 date;
172#define CSS_DATE_DAY (0xFF << 0)
173#define CSS_DATE_MONTH (0xFF << 8)
174#define CSS_DATE_YEAR (0xFFFF << 16)
175 u32 size_dw;
176 u32 key_size_dw;
177 u32 modulus_size_dw;
178 u32 exponent_size_dw;
179 u32 time;
180#define CSS_TIME_HOUR (0xFF << 0)
181#define CSS_DATE_MIN (0xFF << 8)
182#define CSS_DATE_SEC (0xFFFF << 16)
183 char username[8];
184 char buildnumber[12];
185 u32 sw_version;
186#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
187#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
188#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
189#define CSS_SW_VERSION_HUC_MAJOR (0xFFFF << 16)
190#define CSS_SW_VERSION_HUC_MINOR (0xFFFF << 0)
191 u32 reserved[14];
192 u32 header_info;
193} __packed;
194
195
196struct guc_wq_item {
197 u32 header;
198 u32 context_desc;
199 u32 submit_element_info;
200 u32 fence_id;
201} __packed;
202
203struct guc_process_desc {
204 u32 stage_id;
205 u64 db_base_addr;
206 u32 head;
207 u32 tail;
208 u32 error_offset;
209 u64 wq_base_addr;
210 u32 wq_size_bytes;
211 u32 wq_status;
212 u32 engine_presence;
213 u32 priority;
214 u32 reserved[30];
215} __packed;
216
217
218#define GUC_ELC_CTXID_OFFSET 0
219#define GUC_ELC_ENGINE_OFFSET 29
220
221
222struct guc_execlist_context {
223 u32 context_desc;
224 u32 context_id;
225 u32 ring_status;
226 u32 ring_lrca;
227 u32 ring_begin;
228 u32 ring_end;
229 u32 ring_next_free_location;
230 u32 ring_current_tail_pointer_value;
231 u8 engine_state_submit_value;
232 u8 engine_state_wait_value;
233 u16 pagefault_count;
234 u16 engine_submit_queue_count;
235} __packed;
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246struct guc_stage_desc {
247 u32 sched_common_area;
248 u32 stage_id;
249 u32 pas_id;
250 u8 engines_used;
251 u64 db_trigger_cpu;
252 u32 db_trigger_uk;
253 u64 db_trigger_phy;
254 u16 db_id;
255
256 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
257
258 u8 attribute;
259
260 u32 priority;
261
262 u32 wq_sampled_tail_offset;
263 u32 wq_total_submit_enqueues;
264
265 u32 process_desc;
266 u32 wq_addr;
267 u32 wq_size;
268
269 u32 engine_presence;
270
271 u8 engine_suspended;
272
273 u8 reserved0[3];
274 u64 reserved1[1];
275
276 u64 desc_private;
277} __packed;
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335struct guc_ct_buffer_desc {
336 u32 addr;
337 u64 host_private;
338 u32 size;
339 u32 head;
340 u32 tail;
341 u32 is_in_error;
342 u32 fence;
343 u32 status;
344 u32 owner;
345 u32 owner_sub_id;
346 u32 reserved[5];
347} __packed;
348
349
350#define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
351#define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
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365#define GUC_CT_MSG_LEN_SHIFT 0
366#define GUC_CT_MSG_LEN_MASK 0x1F
367#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
368#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
369#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
370#define GUC_CT_MSG_SEND_STATUS (1 << 10)
371#define GUC_CT_MSG_ACTION_SHIFT 16
372#define GUC_CT_MSG_ACTION_MASK 0xFFFF
373
374#define GUC_FORCEWAKE_RENDER (1 << 0)
375#define GUC_FORCEWAKE_MEDIA (1 << 1)
376
377#define GUC_POWER_UNSPECIFIED 0
378#define GUC_POWER_D0 1
379#define GUC_POWER_D1 2
380#define GUC_POWER_D2 3
381#define GUC_POWER_D3 4
382
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385
386#define POLICY_RESET_ENGINE (1<<0)
387
388#define POLICY_PREEMPT_TO_IDLE (1<<1)
389
390#define POLICY_MAX_NUM_WI 15
391#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
392#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
393#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
394#define POLICY_DEFAULT_FAULT_TIME_US 250000
395
396struct guc_policy {
397
398 u32 execution_quantum;
399
400
401 u32 preemption_time;
402
403
404 u32 fault_time;
405 u32 policy_flags;
406 u32 reserved[8];
407} __packed;
408
409struct guc_policies {
410 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
411 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
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415 u32 dpc_promote_time;
416
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418 u32 is_valid;
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422 u32 max_num_work_items;
423
424 u32 reserved[4];
425} __packed;
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430#define GUC_REGSET_MAX_REGISTERS 64
431#define GUC_S3_SAVE_SPACE_PAGES 10
432
433struct guc_mmio_reg {
434 u32 offset;
435 u32 value;
436 u32 flags;
437#define GUC_REGSET_MASKED (1 << 0)
438} __packed;
439
440struct guc_mmio_regset {
441 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
442 u32 values_valid;
443 u32 number_of_registers;
444} __packed;
445
446
447struct guc_mmio_reg_state {
448 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
449 u32 reserved[98];
450} __packed;
451
452
453struct guc_gt_system_info {
454 u32 slice_enabled;
455 u32 rcs_enabled;
456 u32 reserved0;
457 u32 bcs_enabled;
458 u32 vdbox_enable_mask;
459 u32 vdbox_sfc_support_mask;
460 u32 vebox_enable_mask;
461 u32 reserved[9];
462} __packed;
463
464
465struct guc_ct_pool_entry {
466 struct guc_ct_buffer_desc desc;
467 u32 reserved[7];
468} __packed;
469
470#define GUC_CT_POOL_SIZE 2
471
472struct guc_clients_info {
473 u32 clients_num;
474 u32 reserved0[13];
475 u32 ct_pool_addr;
476 u32 ct_pool_count;
477 u32 reserved[4];
478} __packed;
479
480
481struct guc_ads {
482 u32 reg_state_addr;
483 u32 reg_state_buffer;
484 u32 scheduler_policies;
485 u32 gt_system_info;
486 u32 clients_info;
487 u32 control_data;
488 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
489 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
490 u32 reserved[16];
491} __packed;
492
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494
495enum guc_log_buffer_type {
496 GUC_ISR_LOG_BUFFER,
497 GUC_DPC_LOG_BUFFER,
498 GUC_CRASH_DUMP_LOG_BUFFER,
499 GUC_MAX_LOG_BUFFER
500};
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523struct guc_log_buffer_state {
524 u32 marker[2];
525 u32 read_ptr;
526 u32 write_ptr;
527 u32 size;
528 u32 sampled_write_ptr;
529 union {
530 struct {
531 u32 flush_to_file:1;
532 u32 buffer_full_cnt:4;
533 u32 reserved:27;
534 };
535 u32 flags;
536 };
537 u32 version;
538} __packed;
539
540struct guc_ctx_report {
541 u32 report_return_status;
542 u32 reserved1[64];
543 u32 affected_count;
544 u32 reserved2[2];
545} __packed;
546
547
548struct guc_shared_ctx_data {
549 u32 addr_of_last_preempted_data_low;
550 u32 addr_of_last_preempted_data_high;
551 u32 addr_of_last_preempted_data_high_tmp;
552 u32 padding;
553 u32 is_mapped_to_proxy;
554 u32 proxy_ctx_id;
555 u32 engine_reset_ctx_id;
556 u32 media_reset_count;
557 u32 reserved1[8];
558 u32 uk_last_ctx_switch_reason;
559 u32 was_reset;
560 u32 lrca_gpu_addr;
561 u64 execlist_ctx;
562 u32 reserved2[66];
563 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
564} __packed;
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607#define GUC_MAX_MMIO_MSG_LEN 8
608
609#define INTEL_GUC_MSG_TYPE_SHIFT 28
610#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
611#define INTEL_GUC_MSG_DATA_SHIFT 16
612#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
613#define INTEL_GUC_MSG_CODE_SHIFT 0
614#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
615
616#define __INTEL_GUC_MSG_GET(T, m) \
617 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
618#define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
619#define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
620#define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
621
622enum intel_guc_msg_type {
623 INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
624 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
625};
626
627#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
628 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
629#define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
630#define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
631
632enum intel_guc_action {
633 INTEL_GUC_ACTION_DEFAULT = 0x0,
634 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
635 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
636 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
637 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
638 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
639 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
640 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
641 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
642 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
643 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
644 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
645 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
646 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
647 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
648 INTEL_GUC_ACTION_LIMIT
649};
650
651enum intel_guc_preempt_options {
652 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
653 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
654};
655
656enum intel_guc_report_status {
657 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
658 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
659 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
660 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
661};
662
663enum intel_guc_sleep_state_status {
664 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
665 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
666 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
667#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
668};
669
670#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
671#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
672#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
673#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
674
675enum intel_guc_response_status {
676 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
677 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
678};
679
680#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
681 (typecheck(u32, (m)) && \
682 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
683 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
684 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
685
686
687enum intel_guc_recv_message {
688 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
689 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
690};
691
692#endif
693