1/* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25#ifndef _INTEL_GUC_SUBMISSION_H_ 26#define _INTEL_GUC_SUBMISSION_H_ 27 28#include <linux/spinlock.h> 29 30#include "gt/intel_engine_types.h" 31 32#include "i915_gem.h" 33#include "i915_selftest.h" 34 35struct drm_i915_private; 36 37/* 38 * This structure primarily describes the GEM object shared with the GuC. 39 * The specs sometimes refer to this object as a "GuC context", but we use 40 * the term "client" to avoid confusion with hardware contexts. This 41 * GEM object is held for the entire lifetime of our interaction with 42 * the GuC, being allocated before the GuC is loaded with its firmware. 43 * Because there's no way to update the address used by the GuC after 44 * initialisation, the shared object must stay pinned into the GGTT as 45 * long as the GuC is in use. We also keep the first page (only) mapped 46 * into kernel address space, as it includes shared data that must be 47 * updated on every request submission. 48 * 49 * The single GEM object described here is actually made up of several 50 * separate areas, as far as the GuC is concerned. The first page (kept 51 * kmap'd) includes the "process descriptor" which holds sequence data for 52 * the doorbell, and one cacheline which actually *is* the doorbell; a 53 * write to this will "ring the doorbell" (i.e. send an interrupt to the 54 * GuC). The subsequent pages of the client object constitute the work 55 * queue (a circular array of work items), again described in the process 56 * descriptor. Work queue pages are mapped momentarily as required. 57 */ 58struct intel_guc_client { 59 struct i915_vma *vma; 60 void *vaddr; 61 struct i915_gem_context *owner; 62 struct intel_guc *guc; 63 64 /* bitmap of (host) engine ids */ 65 u32 engines; 66 u32 priority; 67 u32 stage_id; 68 u32 proc_desc_offset; 69 70 u16 doorbell_id; 71 unsigned long doorbell_offset; 72 73 /* Protects GuC client's WQ access */ 74 spinlock_t wq_lock; 75 /* Per-engine counts of GuC submissions */ 76 u64 submissions[I915_NUM_ENGINES]; 77 78 /* For testing purposes, use nop WQ items instead of real ones */ 79 I915_SELFTEST_DECLARE(bool use_nop_wqi); 80}; 81 82int intel_guc_submission_init(struct intel_guc *guc); 83int intel_guc_submission_enable(struct intel_guc *guc); 84void intel_guc_submission_disable(struct intel_guc *guc); 85void intel_guc_submission_fini(struct intel_guc *guc); 86int intel_guc_preempt_work_create(struct intel_guc *guc); 87void intel_guc_preempt_work_destroy(struct intel_guc *guc); 88 89#endif 90