LXR linux/drivers/gpu/drm/i915/intel

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright © 2019 Intel Corporation
   4 */
   5
   6#ifndef __INTEL_PM_H__
   7#define __INTEL_PM_H__
   8
   9#include <linux/types.h>
  10
  11#include "i915_reg.h"
  12
  13struct drm_atomic_state;
  14struct drm_device;
  15struct drm_i915_private;
  16struct i915_request;
  17struct intel_crtc;
  18struct intel_crtc_state;
  19struct intel_plane;
  20struct skl_ddb_allocation;
  21struct skl_ddb_entry;
  22struct skl_pipe_wm;
  23struct skl_wm_level;
  24
  25void intel_init_clock_gating(struct drm_i915_private *dev_priv);
  26void intel_suspend_hw(struct drm_i915_private *dev_priv);
  27int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
  28void intel_update_watermarks(struct intel_crtc *crtc);
  29void intel_init_pm(struct drm_i915_private *dev_priv);
  30void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
  31void intel_pm_setup(struct drm_i915_private *dev_priv);
  32void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  33void intel_gpu_ips_teardown(void);
  34void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
  35void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
  36void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
  37void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
  38void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
  39void gen6_rps_busy(struct drm_i915_private *dev_priv);
  40void gen6_rps_idle(struct drm_i915_private *dev_priv);
  41void gen6_rps_boost(struct i915_request *rq);
  42void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
  43void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
  44void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
  45void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
  46void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
  47                               struct skl_ddb_entry *ddb_y,
  48                               struct skl_ddb_entry *ddb_uv);
  49void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  50                          struct skl_ddb_allocation *ddb /* out */);
  51void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
  52                              struct skl_pipe_wm *out);
  53void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
  54void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
  55bool intel_can_enable_sagv(struct drm_atomic_state *state);
  56int intel_enable_sagv(struct drm_i915_private *dev_priv);
  57int intel_disable_sagv(struct drm_i915_private *dev_priv);
  58bool skl_wm_level_equals(const struct skl_wm_level *l1,
  59                         const struct skl_wm_level *l2);
  60bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
  61                                 const struct skl_ddb_entry *entries,
  62                                 int num_entries, int ignore_idx);
  63void skl_write_plane_wm(struct intel_plane *plane,
  64                        const struct intel_crtc_state *crtc_state);
  65void skl_write_cursor_wm(struct intel_plane *plane,
  66                         const struct intel_crtc_state *crtc_state);
  67bool ilk_disable_lp_wm(struct drm_device *dev);
  68int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
  69                                  struct intel_crtc_state *cstate);
  70void intel_init_ipc(struct drm_i915_private *dev_priv);
  71void intel_enable_ipc(struct drm_i915_private *dev_priv);
  72
  73int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
  74int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
  75u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
  76u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
  77
  78u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
  79
  80unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  81unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  82unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  83void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  84
  85bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
  86int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
  87void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive);
  88bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
  89
  90#endif /* __INTEL_PM_H__ */
  91