1
2
3
4#include <linux/regulator/consumer.h>
5#include <linux/reset.h>
6#include <linux/clk.h>
7#include <linux/dma-mapping.h>
8#include <linux/platform_device.h>
9
10#include "lima_device.h"
11#include "lima_gp.h"
12#include "lima_pp.h"
13#include "lima_mmu.h"
14#include "lima_pmu.h"
15#include "lima_l2_cache.h"
16#include "lima_dlbu.h"
17#include "lima_bcast.h"
18#include "lima_vm.h"
19
20struct lima_ip_desc {
21 char *name;
22 char *irq_name;
23 bool must_have[lima_gpu_num];
24 int offset[lima_gpu_num];
25
26 int (*init)(struct lima_ip *ip);
27 void (*fini)(struct lima_ip *ip);
28};
29
30#define LIMA_IP_DESC(ipname, mst0, mst1, off0, off1, func, irq) \
31 [lima_ip_##ipname] = { \
32 .name = #ipname, \
33 .irq_name = irq, \
34 .must_have = { \
35 [lima_gpu_mali400] = mst0, \
36 [lima_gpu_mali450] = mst1, \
37 }, \
38 .offset = { \
39 [lima_gpu_mali400] = off0, \
40 [lima_gpu_mali450] = off1, \
41 }, \
42 .init = lima_##func##_init, \
43 .fini = lima_##func##_fini, \
44 }
45
46static struct lima_ip_desc lima_ip_desc[lima_ip_num] = {
47 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
48 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
49 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
50 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
51 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
52 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
53 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
54 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
55 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
56 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
57 LIMA_IP_DESC(pp5, false, false, -1, 0x2A000, pp, "pp5"),
58 LIMA_IP_DESC(pp6, false, false, -1, 0x2C000, pp, "pp6"),
59 LIMA_IP_DESC(pp7, false, false, -1, 0x2E000, pp, "pp7"),
60 LIMA_IP_DESC(gpmmu, true, true, 0x03000, 0x03000, mmu, "gpmmu"),
61 LIMA_IP_DESC(ppmmu0, true, true, 0x04000, 0x04000, mmu, "ppmmu0"),
62 LIMA_IP_DESC(ppmmu1, false, false, 0x05000, 0x05000, mmu, "ppmmu1"),
63 LIMA_IP_DESC(ppmmu2, false, false, 0x06000, 0x06000, mmu, "ppmmu2"),
64 LIMA_IP_DESC(ppmmu3, false, false, 0x07000, 0x07000, mmu, "ppmmu3"),
65 LIMA_IP_DESC(ppmmu4, false, false, -1, 0x1C000, mmu, "ppmmu4"),
66 LIMA_IP_DESC(ppmmu5, false, false, -1, 0x1D000, mmu, "ppmmu5"),
67 LIMA_IP_DESC(ppmmu6, false, false, -1, 0x1E000, mmu, "ppmmu6"),
68 LIMA_IP_DESC(ppmmu7, false, false, -1, 0x1F000, mmu, "ppmmu7"),
69 LIMA_IP_DESC(dlbu, false, true, -1, 0x14000, dlbu, NULL),
70 LIMA_IP_DESC(bcast, false, true, -1, 0x13000, bcast, NULL),
71 LIMA_IP_DESC(pp_bcast, false, true, -1, 0x16000, pp_bcast, "pp"),
72 LIMA_IP_DESC(ppmmu_bcast, false, true, -1, 0x15000, mmu, NULL),
73};
74
75const char *lima_ip_name(struct lima_ip *ip)
76{
77 return lima_ip_desc[ip->id].name;
78}
79
80static int lima_clk_init(struct lima_device *dev)
81{
82 int err;
83 unsigned long bus_rate, gpu_rate;
84
85 dev->clk_bus = devm_clk_get(dev->dev, "bus");
86 if (IS_ERR(dev->clk_bus)) {
87 dev_err(dev->dev, "get bus clk failed %ld\n", PTR_ERR(dev->clk_bus));
88 return PTR_ERR(dev->clk_bus);
89 }
90
91 dev->clk_gpu = devm_clk_get(dev->dev, "core");
92 if (IS_ERR(dev->clk_gpu)) {
93 dev_err(dev->dev, "get core clk failed %ld\n", PTR_ERR(dev->clk_gpu));
94 return PTR_ERR(dev->clk_gpu);
95 }
96
97 bus_rate = clk_get_rate(dev->clk_bus);
98 dev_info(dev->dev, "bus rate = %lu\n", bus_rate);
99
100 gpu_rate = clk_get_rate(dev->clk_gpu);
101 dev_info(dev->dev, "mod rate = %lu", gpu_rate);
102
103 err = clk_prepare_enable(dev->clk_bus);
104 if (err)
105 return err;
106
107 err = clk_prepare_enable(dev->clk_gpu);
108 if (err)
109 goto error_out0;
110
111 dev->reset = devm_reset_control_get_optional(dev->dev, NULL);
112 if (IS_ERR(dev->reset)) {
113 err = PTR_ERR(dev->reset);
114 goto error_out1;
115 } else if (dev->reset != NULL) {
116 err = reset_control_deassert(dev->reset);
117 if (err)
118 goto error_out1;
119 }
120
121 return 0;
122
123error_out1:
124 clk_disable_unprepare(dev->clk_gpu);
125error_out0:
126 clk_disable_unprepare(dev->clk_bus);
127 return err;
128}
129
130static void lima_clk_fini(struct lima_device *dev)
131{
132 if (dev->reset != NULL)
133 reset_control_assert(dev->reset);
134 clk_disable_unprepare(dev->clk_gpu);
135 clk_disable_unprepare(dev->clk_bus);
136}
137
138static int lima_regulator_init(struct lima_device *dev)
139{
140 int ret;
141
142 dev->regulator = devm_regulator_get_optional(dev->dev, "mali");
143 if (IS_ERR(dev->regulator)) {
144 ret = PTR_ERR(dev->regulator);
145 dev->regulator = NULL;
146 if (ret == -ENODEV)
147 return 0;
148 dev_err(dev->dev, "failed to get regulator: %d\n", ret);
149 return ret;
150 }
151
152 ret = regulator_enable(dev->regulator);
153 if (ret < 0) {
154 dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
155 return ret;
156 }
157
158 return 0;
159}
160
161static void lima_regulator_fini(struct lima_device *dev)
162{
163 if (dev->regulator)
164 regulator_disable(dev->regulator);
165}
166
167static int lima_init_ip(struct lima_device *dev, int index)
168{
169 struct lima_ip_desc *desc = lima_ip_desc + index;
170 struct lima_ip *ip = dev->ip + index;
171 int offset = desc->offset[dev->id];
172 bool must = desc->must_have[dev->id];
173 int err;
174
175 if (offset < 0)
176 return 0;
177
178 ip->dev = dev;
179 ip->id = index;
180 ip->iomem = dev->iomem + offset;
181 if (desc->irq_name) {
182 err = platform_get_irq_byname(dev->pdev, desc->irq_name);
183 if (err < 0)
184 goto out;
185 ip->irq = err;
186 }
187
188 err = desc->init(ip);
189 if (!err) {
190 ip->present = true;
191 return 0;
192 }
193
194out:
195 return must ? err : 0;
196}
197
198static void lima_fini_ip(struct lima_device *ldev, int index)
199{
200 struct lima_ip_desc *desc = lima_ip_desc + index;
201 struct lima_ip *ip = ldev->ip + index;
202
203 if (ip->present)
204 desc->fini(ip);
205}
206
207static int lima_init_gp_pipe(struct lima_device *dev)
208{
209 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
210 int err;
211
212 err = lima_sched_pipe_init(pipe, "gp");
213 if (err)
214 return err;
215
216 pipe->l2_cache[pipe->num_l2_cache++] = dev->ip + lima_ip_l2_cache0;
217 pipe->mmu[pipe->num_mmu++] = dev->ip + lima_ip_gpmmu;
218 pipe->processor[pipe->num_processor++] = dev->ip + lima_ip_gp;
219
220 err = lima_gp_pipe_init(dev);
221 if (err) {
222 lima_sched_pipe_fini(pipe);
223 return err;
224 }
225
226 return 0;
227}
228
229static void lima_fini_gp_pipe(struct lima_device *dev)
230{
231 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
232
233 lima_gp_pipe_fini(dev);
234 lima_sched_pipe_fini(pipe);
235}
236
237static int lima_init_pp_pipe(struct lima_device *dev)
238{
239 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
240 int err, i;
241
242 err = lima_sched_pipe_init(pipe, "pp");
243 if (err)
244 return err;
245
246 for (i = 0; i < LIMA_SCHED_PIPE_MAX_PROCESSOR; i++) {
247 struct lima_ip *pp = dev->ip + lima_ip_pp0 + i;
248 struct lima_ip *ppmmu = dev->ip + lima_ip_ppmmu0 + i;
249 struct lima_ip *l2_cache;
250
251 if (dev->id == lima_gpu_mali400)
252 l2_cache = dev->ip + lima_ip_l2_cache0;
253 else
254 l2_cache = dev->ip + lima_ip_l2_cache1 + (i >> 2);
255
256 if (pp->present && ppmmu->present && l2_cache->present) {
257 pipe->mmu[pipe->num_mmu++] = ppmmu;
258 pipe->processor[pipe->num_processor++] = pp;
259 if (!pipe->l2_cache[i >> 2])
260 pipe->l2_cache[pipe->num_l2_cache++] = l2_cache;
261 }
262 }
263
264 if (dev->ip[lima_ip_bcast].present) {
265 pipe->bcast_processor = dev->ip + lima_ip_pp_bcast;
266 pipe->bcast_mmu = dev->ip + lima_ip_ppmmu_bcast;
267 }
268
269 err = lima_pp_pipe_init(dev);
270 if (err) {
271 lima_sched_pipe_fini(pipe);
272 return err;
273 }
274
275 return 0;
276}
277
278static void lima_fini_pp_pipe(struct lima_device *dev)
279{
280 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
281
282 lima_pp_pipe_fini(dev);
283 lima_sched_pipe_fini(pipe);
284}
285
286int lima_device_init(struct lima_device *ldev)
287{
288 int err, i;
289 struct resource *res;
290
291 dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32));
292
293 err = lima_clk_init(ldev);
294 if (err) {
295 dev_err(ldev->dev, "clk init fail %d\n", err);
296 return err;
297 }
298
299 err = lima_regulator_init(ldev);
300 if (err) {
301 dev_err(ldev->dev, "regulator init fail %d\n", err);
302 goto err_out0;
303 }
304
305 ldev->empty_vm = lima_vm_create(ldev);
306 if (!ldev->empty_vm) {
307 err = -ENOMEM;
308 goto err_out1;
309 }
310
311 ldev->va_start = 0;
312 if (ldev->id == lima_gpu_mali450) {
313 ldev->va_end = LIMA_VA_RESERVE_START;
314 ldev->dlbu_cpu = dma_alloc_wc(
315 ldev->dev, LIMA_PAGE_SIZE,
316 &ldev->dlbu_dma, GFP_KERNEL);
317 if (!ldev->dlbu_cpu) {
318 err = -ENOMEM;
319 goto err_out2;
320 }
321 } else
322 ldev->va_end = LIMA_VA_RESERVE_END;
323
324 res = platform_get_resource(ldev->pdev, IORESOURCE_MEM, 0);
325 ldev->iomem = devm_ioremap_resource(ldev->dev, res);
326 if (IS_ERR(ldev->iomem)) {
327 dev_err(ldev->dev, "fail to ioremap iomem\n");
328 err = PTR_ERR(ldev->iomem);
329 goto err_out3;
330 }
331
332 for (i = 0; i < lima_ip_num; i++) {
333 err = lima_init_ip(ldev, i);
334 if (err)
335 goto err_out4;
336 }
337
338 err = lima_init_gp_pipe(ldev);
339 if (err)
340 goto err_out4;
341
342 err = lima_init_pp_pipe(ldev);
343 if (err)
344 goto err_out5;
345
346 return 0;
347
348err_out5:
349 lima_fini_gp_pipe(ldev);
350err_out4:
351 while (--i >= 0)
352 lima_fini_ip(ldev, i);
353err_out3:
354 if (ldev->dlbu_cpu)
355 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
356 ldev->dlbu_cpu, ldev->dlbu_dma);
357err_out2:
358 lima_vm_put(ldev->empty_vm);
359err_out1:
360 lima_regulator_fini(ldev);
361err_out0:
362 lima_clk_fini(ldev);
363 return err;
364}
365
366void lima_device_fini(struct lima_device *ldev)
367{
368 int i;
369
370 lima_fini_pp_pipe(ldev);
371 lima_fini_gp_pipe(ldev);
372
373 for (i = lima_ip_num - 1; i >= 0; i--)
374 lima_fini_ip(ldev, i);
375
376 if (ldev->dlbu_cpu)
377 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
378 ldev->dlbu_cpu, ldev->dlbu_dma);
379
380 lima_vm_put(ldev->empty_vm);
381
382 lima_regulator_fini(ldev);
383
384 lima_clk_fini(ldev);
385}
386
