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5
6#include <drm/drmP.h>
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_mipi_dsi.h>
9#include <drm/drm_panel.h>
10#include <drm/drm_of.h>
11#include <drm/drm_probe_helper.h>
12#include <linux/clk.h>
13#include <linux/component.h>
14#include <linux/iopoll.h>
15#include <linux/irq.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/phy/phy.h>
19#include <linux/platform_device.h>
20#include <video/mipi_display.h>
21#include <video/videomode.h>
22
23#include "mtk_drm_ddp_comp.h"
24
25#define DSI_START 0x00
26
27#define DSI_INTEN 0x08
28
29#define DSI_INTSTA 0x0c
30#define LPRX_RD_RDY_INT_FLAG BIT(0)
31#define CMD_DONE_INT_FLAG BIT(1)
32#define TE_RDY_INT_FLAG BIT(2)
33#define VM_DONE_INT_FLAG BIT(3)
34#define EXT_TE_RDY_INT_FLAG BIT(4)
35#define DSI_BUSY BIT(31)
36
37#define DSI_CON_CTRL 0x10
38#define DSI_RESET BIT(0)
39#define DSI_EN BIT(1)
40
41#define DSI_MODE_CTRL 0x14
42#define MODE (3)
43#define CMD_MODE 0
44#define SYNC_PULSE_MODE 1
45#define SYNC_EVENT_MODE 2
46#define BURST_MODE 3
47#define FRM_MODE BIT(16)
48#define MIX_MODE BIT(17)
49
50#define DSI_TXRX_CTRL 0x18
51#define VC_NUM BIT(1)
52#define LANE_NUM (0xf << 2)
53#define DIS_EOT BIT(6)
54#define NULL_EN BIT(7)
55#define TE_FREERUN BIT(8)
56#define EXT_TE_EN BIT(9)
57#define EXT_TE_EDGE BIT(10)
58#define MAX_RTN_SIZE (0xf << 12)
59#define HSTX_CKLP_EN BIT(16)
60
61#define DSI_PSCTRL 0x1c
62#define DSI_PS_WC 0x3fff
63#define DSI_PS_SEL (3 << 16)
64#define PACKED_PS_16BIT_RGB565 (0 << 16)
65#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
66#define PACKED_PS_18BIT_RGB666 (2 << 16)
67#define PACKED_PS_24BIT_RGB888 (3 << 16)
68
69#define DSI_VSA_NL 0x20
70#define DSI_VBP_NL 0x24
71#define DSI_VFP_NL 0x28
72#define DSI_VACT_NL 0x2C
73#define DSI_HSA_WC 0x50
74#define DSI_HBP_WC 0x54
75#define DSI_HFP_WC 0x58
76
77#define DSI_CMDQ_SIZE 0x60
78#define CMDQ_SIZE 0x3f
79
80#define DSI_HSTX_CKL_WC 0x64
81
82#define DSI_RX_DATA0 0x74
83#define DSI_RX_DATA1 0x78
84#define DSI_RX_DATA2 0x7c
85#define DSI_RX_DATA3 0x80
86
87#define DSI_RACK 0x84
88#define RACK BIT(0)
89
90#define DSI_PHY_LCCON 0x104
91#define LC_HS_TX_EN BIT(0)
92#define LC_ULPM_EN BIT(1)
93#define LC_WAKEUP_EN BIT(2)
94
95#define DSI_PHY_LD0CON 0x108
96#define LD0_HS_TX_EN BIT(0)
97#define LD0_ULPM_EN BIT(1)
98#define LD0_WAKEUP_EN BIT(2)
99
100#define DSI_PHY_TIMECON0 0x110
101#define LPX (0xff << 0)
102#define HS_PREP (0xff << 8)
103#define HS_ZERO (0xff << 16)
104#define HS_TRAIL (0xff << 24)
105
106#define DSI_PHY_TIMECON1 0x114
107#define TA_GO (0xff << 0)
108#define TA_SURE (0xff << 8)
109#define TA_GET (0xff << 16)
110#define DA_HS_EXIT (0xff << 24)
111
112#define DSI_PHY_TIMECON2 0x118
113#define CONT_DET (0xff << 0)
114#define CLK_ZERO (0xff << 16)
115#define CLK_TRAIL (0xff << 24)
116
117#define DSI_PHY_TIMECON3 0x11c
118#define CLK_HS_PREP (0xff << 0)
119#define CLK_HS_POST (0xff << 8)
120#define CLK_HS_EXIT (0xff << 16)
121
122#define DSI_VM_CMD_CON 0x130
123#define VM_CMD_EN BIT(0)
124#define TS_VFP_EN BIT(5)
125
126#define DSI_CMDQ0 0x180
127#define CONFIG (0xff << 0)
128#define SHORT_PACKET 0
129#define LONG_PACKET 2
130#define BTA BIT(2)
131#define DATA_ID (0xff << 8)
132#define DATA_0 (0xff << 16)
133#define DATA_1 (0xff << 24)
134
135#define T_LPX 5
136#define T_HS_PREP 6
137#define T_HS_TRAIL 8
138#define T_HS_EXIT 7
139#define T_HS_ZERO 10
140
141#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
142
143#define MTK_DSI_HOST_IS_READ(type) \
144 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
145 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
146 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
147 (type == MIPI_DSI_DCS_READ))
148
149struct phy;
150
151struct mtk_dsi {
152 struct mtk_ddp_comp ddp_comp;
153 struct device *dev;
154 struct mipi_dsi_host host;
155 struct drm_encoder encoder;
156 struct drm_connector conn;
157 struct drm_panel *panel;
158 struct drm_bridge *bridge;
159 struct phy *phy;
160
161 void __iomem *regs;
162
163 struct clk *engine_clk;
164 struct clk *digital_clk;
165 struct clk *hs_clk;
166
167 u32 data_rate;
168
169 unsigned long mode_flags;
170 enum mipi_dsi_pixel_format format;
171 unsigned int lanes;
172 struct videomode vm;
173 int refcount;
174 bool enabled;
175 u32 irq_data;
176 wait_queue_head_t irq_wait_queue;
177};
178
179static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
180{
181 return container_of(e, struct mtk_dsi, encoder);
182}
183
184static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
185{
186 return container_of(c, struct mtk_dsi, conn);
187}
188
189static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
190{
191 return container_of(h, struct mtk_dsi, host);
192}
193
194static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
195{
196 u32 temp = readl(dsi->regs + offset);
197
198 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
199}
200
201static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
202{
203 u32 timcon0, timcon1, timcon2, timcon3;
204 u32 ui, cycle_time;
205
206 ui = 1000 / dsi->data_rate + 0x01;
207 cycle_time = 8000 / dsi->data_rate + 0x01;
208
209 timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
210 timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
211 T_HS_EXIT << 24;
212 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
213 (NS_TO_CYCLE(0x150, cycle_time) << 16);
214 timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
215 NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
216
217 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
218 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
219 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
220 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
221}
222
223static void mtk_dsi_enable(struct mtk_dsi *dsi)
224{
225 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
226}
227
228static void mtk_dsi_disable(struct mtk_dsi *dsi)
229{
230 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
231}
232
233static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
234{
235 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
236 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
237}
238
239static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
240{
241 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
242 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
243}
244
245static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
246{
247 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
248 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
249 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
250}
251
252static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
253{
254 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
255 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
256}
257
258static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
259{
260 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
261 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
262 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
263}
264
265static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
266{
267 u32 tmp_reg1;
268
269 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
270 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
271}
272
273static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
274{
275 if (enter && !mtk_dsi_clk_hs_state(dsi))
276 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
277 else if (!enter && mtk_dsi_clk_hs_state(dsi))
278 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
279}
280
281static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
282{
283 u32 vid_mode = CMD_MODE;
284
285 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
286 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
287 vid_mode = BURST_MODE;
288 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
289 vid_mode = SYNC_PULSE_MODE;
290 else
291 vid_mode = SYNC_EVENT_MODE;
292 }
293
294 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
295}
296
297static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
298{
299 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
300 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
301}
302
303static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
304{
305 struct videomode *vm = &dsi->vm;
306 u32 dsi_buf_bpp, ps_wc;
307 u32 ps_bpp_mode;
308
309 if (dsi->format == MIPI_DSI_FMT_RGB565)
310 dsi_buf_bpp = 2;
311 else
312 dsi_buf_bpp = 3;
313
314 ps_wc = vm->hactive * dsi_buf_bpp;
315 ps_bpp_mode = ps_wc;
316
317 switch (dsi->format) {
318 case MIPI_DSI_FMT_RGB888:
319 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
320 break;
321 case MIPI_DSI_FMT_RGB666:
322 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
323 break;
324 case MIPI_DSI_FMT_RGB666_PACKED:
325 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
326 break;
327 case MIPI_DSI_FMT_RGB565:
328 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
329 break;
330 }
331
332 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
333 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
334 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
335}
336
337static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
338{
339 u32 tmp_reg;
340
341 switch (dsi->lanes) {
342 case 1:
343 tmp_reg = 1 << 2;
344 break;
345 case 2:
346 tmp_reg = 3 << 2;
347 break;
348 case 3:
349 tmp_reg = 7 << 2;
350 break;
351 case 4:
352 tmp_reg = 0xf << 2;
353 break;
354 default:
355 tmp_reg = 0xf << 2;
356 break;
357 }
358
359 tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
360 tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
361
362 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
363}
364
365static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
366{
367 u32 dsi_tmp_buf_bpp;
368 u32 tmp_reg;
369
370 switch (dsi->format) {
371 case MIPI_DSI_FMT_RGB888:
372 tmp_reg = PACKED_PS_24BIT_RGB888;
373 dsi_tmp_buf_bpp = 3;
374 break;
375 case MIPI_DSI_FMT_RGB666:
376 tmp_reg = LOOSELY_PS_18BIT_RGB666;
377 dsi_tmp_buf_bpp = 3;
378 break;
379 case MIPI_DSI_FMT_RGB666_PACKED:
380 tmp_reg = PACKED_PS_18BIT_RGB666;
381 dsi_tmp_buf_bpp = 3;
382 break;
383 case MIPI_DSI_FMT_RGB565:
384 tmp_reg = PACKED_PS_16BIT_RGB565;
385 dsi_tmp_buf_bpp = 2;
386 break;
387 default:
388 tmp_reg = PACKED_PS_24BIT_RGB888;
389 dsi_tmp_buf_bpp = 3;
390 break;
391 }
392
393 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
394 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
395}
396
397static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
398{
399 u32 horizontal_sync_active_byte;
400 u32 horizontal_backporch_byte;
401 u32 horizontal_frontporch_byte;
402 u32 dsi_tmp_buf_bpp;
403
404 struct videomode *vm = &dsi->vm;
405
406 if (dsi->format == MIPI_DSI_FMT_RGB565)
407 dsi_tmp_buf_bpp = 2;
408 else
409 dsi_tmp_buf_bpp = 3;
410
411 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
412 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
413 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
414 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
415
416 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
417
418 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
419 horizontal_backporch_byte =
420 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
421 else
422 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
423 dsi_tmp_buf_bpp - 10);
424
425 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
426
427 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
428 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
429 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
430
431 mtk_dsi_ps_control(dsi);
432}
433
434static void mtk_dsi_start(struct mtk_dsi *dsi)
435{
436 writel(0, dsi->regs + DSI_START);
437 writel(1, dsi->regs + DSI_START);
438}
439
440static void mtk_dsi_stop(struct mtk_dsi *dsi)
441{
442 writel(0, dsi->regs + DSI_START);
443}
444
445static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
446{
447 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
448}
449
450static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
451{
452 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
453
454 writel(inten, dsi->regs + DSI_INTEN);
455}
456
457static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
458{
459 dsi->irq_data |= irq_bit;
460}
461
462static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
463{
464 dsi->irq_data &= ~irq_bit;
465}
466
467static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
468 unsigned int timeout)
469{
470 s32 ret = 0;
471 unsigned long jiffies = msecs_to_jiffies(timeout);
472
473 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
474 dsi->irq_data & irq_flag,
475 jiffies);
476 if (ret == 0) {
477 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
478
479 mtk_dsi_enable(dsi);
480 mtk_dsi_reset_engine(dsi);
481 }
482
483 return ret;
484}
485
486static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
487{
488 struct mtk_dsi *dsi = dev_id;
489 u32 status, tmp;
490 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
491
492 status = readl(dsi->regs + DSI_INTSTA) & flag;
493
494 if (status) {
495 do {
496 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
497 tmp = readl(dsi->regs + DSI_INTSTA);
498 } while (tmp & DSI_BUSY);
499
500 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
501 mtk_dsi_irq_data_set(dsi, status);
502 wake_up_interruptible(&dsi->irq_wait_queue);
503 }
504
505 return IRQ_HANDLED;
506}
507
508static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
509{
510 mtk_dsi_irq_data_clear(dsi, irq_flag);
511 mtk_dsi_set_cmd_mode(dsi);
512
513 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
514 DRM_ERROR("failed to switch cmd mode\n");
515 return -ETIME;
516 } else {
517 return 0;
518 }
519}
520
521static int mtk_dsi_poweron(struct mtk_dsi *dsi)
522{
523 struct device *dev = dsi->dev;
524 int ret;
525 u64 pixel_clock, total_bits;
526 u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
527
528 if (++dsi->refcount != 1)
529 return 0;
530
531 switch (dsi->format) {
532 case MIPI_DSI_FMT_RGB565:
533 bit_per_pixel = 16;
534 break;
535 case MIPI_DSI_FMT_RGB666_PACKED:
536 bit_per_pixel = 18;
537 break;
538 case MIPI_DSI_FMT_RGB666:
539 case MIPI_DSI_FMT_RGB888:
540 default:
541 bit_per_pixel = 24;
542 break;
543 }
544
545
546
547
548
549
550
551 pixel_clock = dsi->vm.pixelclock;
552 htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
553 dsi->vm.hsync_len;
554 htotal_bits = htotal * bit_per_pixel;
555
556 overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
557 T_HS_EXIT;
558 overhead_bits = overhead_cycles * dsi->lanes * 8;
559 total_bits = htotal_bits + overhead_bits;
560
561 dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
562 htotal * dsi->lanes);
563
564 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
565 if (ret < 0) {
566 dev_err(dev, "Failed to set data rate: %d\n", ret);
567 goto err_refcount;
568 }
569
570 phy_power_on(dsi->phy);
571
572 ret = clk_prepare_enable(dsi->engine_clk);
573 if (ret < 0) {
574 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
575 goto err_phy_power_off;
576 }
577
578 ret = clk_prepare_enable(dsi->digital_clk);
579 if (ret < 0) {
580 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
581 goto err_disable_engine_clk;
582 }
583
584 mtk_dsi_enable(dsi);
585 mtk_dsi_reset_engine(dsi);
586 mtk_dsi_phy_timconfig(dsi);
587
588 mtk_dsi_rxtx_control(dsi);
589 mtk_dsi_ps_control_vact(dsi);
590 mtk_dsi_set_vm_cmd(dsi);
591 mtk_dsi_config_vdo_timing(dsi);
592 mtk_dsi_set_interrupt_enable(dsi);
593
594 mtk_dsi_clk_ulp_mode_leave(dsi);
595 mtk_dsi_lane0_ulp_mode_leave(dsi);
596 mtk_dsi_clk_hs_mode(dsi, 0);
597
598 if (dsi->panel) {
599 if (drm_panel_prepare(dsi->panel)) {
600 DRM_ERROR("failed to prepare the panel\n");
601 goto err_disable_digital_clk;
602 }
603 }
604
605 return 0;
606err_disable_digital_clk:
607 clk_disable_unprepare(dsi->digital_clk);
608err_disable_engine_clk:
609 clk_disable_unprepare(dsi->engine_clk);
610err_phy_power_off:
611 phy_power_off(dsi->phy);
612err_refcount:
613 dsi->refcount--;
614 return ret;
615}
616
617static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
618{
619 if (WARN_ON(dsi->refcount == 0))
620 return;
621
622 if (--dsi->refcount != 0)
623 return;
624
625
626
627
628
629
630
631
632 mtk_dsi_stop(dsi);
633
634 if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
635 if (dsi->panel) {
636 if (drm_panel_unprepare(dsi->panel)) {
637 DRM_ERROR("failed to unprepare the panel\n");
638 return;
639 }
640 }
641 }
642
643 mtk_dsi_reset_engine(dsi);
644 mtk_dsi_lane0_ulp_mode_enter(dsi);
645 mtk_dsi_clk_ulp_mode_enter(dsi);
646
647 mtk_dsi_disable(dsi);
648
649 clk_disable_unprepare(dsi->engine_clk);
650 clk_disable_unprepare(dsi->digital_clk);
651
652 phy_power_off(dsi->phy);
653}
654
655static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
656{
657 int ret;
658
659 if (dsi->enabled)
660 return;
661
662 ret = mtk_dsi_poweron(dsi);
663 if (ret < 0) {
664 DRM_ERROR("failed to power on dsi\n");
665 return;
666 }
667
668 mtk_dsi_set_mode(dsi);
669 mtk_dsi_clk_hs_mode(dsi, 1);
670
671 mtk_dsi_start(dsi);
672
673 if (dsi->panel) {
674 if (drm_panel_enable(dsi->panel)) {
675 DRM_ERROR("failed to enable the panel\n");
676 goto err_dsi_power_off;
677 }
678 }
679
680 dsi->enabled = true;
681
682 return;
683err_dsi_power_off:
684 mtk_dsi_stop(dsi);
685 mtk_dsi_poweroff(dsi);
686}
687
688static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
689{
690 if (!dsi->enabled)
691 return;
692
693 if (dsi->panel) {
694 if (drm_panel_disable(dsi->panel)) {
695 DRM_ERROR("failed to disable the panel\n");
696 return;
697 }
698 }
699
700 mtk_dsi_poweroff(dsi);
701
702 dsi->enabled = false;
703}
704
705static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
706{
707 drm_encoder_cleanup(encoder);
708}
709
710static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
711 .destroy = mtk_dsi_encoder_destroy,
712};
713
714static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
715 const struct drm_display_mode *mode,
716 struct drm_display_mode *adjusted_mode)
717{
718 return true;
719}
720
721static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
722 struct drm_display_mode *mode,
723 struct drm_display_mode *adjusted)
724{
725 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
726
727 drm_display_mode_to_videomode(adjusted, &dsi->vm);
728}
729
730static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
731{
732 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
733
734 mtk_output_dsi_disable(dsi);
735}
736
737static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
738{
739 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
740
741 mtk_output_dsi_enable(dsi);
742}
743
744static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
745{
746 struct mtk_dsi *dsi = connector_to_dsi(connector);
747
748 return drm_panel_get_modes(dsi->panel);
749}
750
751static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
752 .mode_fixup = mtk_dsi_encoder_mode_fixup,
753 .mode_set = mtk_dsi_encoder_mode_set,
754 .disable = mtk_dsi_encoder_disable,
755 .enable = mtk_dsi_encoder_enable,
756};
757
758static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
759 .fill_modes = drm_helper_probe_single_connector_modes,
760 .destroy = drm_connector_cleanup,
761 .reset = drm_atomic_helper_connector_reset,
762 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
763 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
764};
765
766static const struct drm_connector_helper_funcs
767 mtk_dsi_connector_helper_funcs = {
768 .get_modes = mtk_dsi_connector_get_modes,
769};
770
771static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
772{
773 int ret;
774
775 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
776 DRM_MODE_CONNECTOR_DSI);
777 if (ret) {
778 DRM_ERROR("Failed to connector init to drm\n");
779 return ret;
780 }
781
782 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
783
784 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
785 drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
786
787 if (dsi->panel) {
788 ret = drm_panel_attach(dsi->panel, &dsi->conn);
789 if (ret) {
790 DRM_ERROR("Failed to attach panel to drm\n");
791 goto err_connector_cleanup;
792 }
793 }
794
795 return 0;
796
797err_connector_cleanup:
798 drm_connector_cleanup(&dsi->conn);
799 return ret;
800}
801
802static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
803{
804 int ret;
805
806 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
807 DRM_MODE_ENCODER_DSI, NULL);
808 if (ret) {
809 DRM_ERROR("Failed to encoder init to drm\n");
810 return ret;
811 }
812 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
813
814
815
816
817
818 dsi->encoder.possible_crtcs = 1;
819
820
821 if (dsi->bridge) {
822 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
823 if (ret) {
824 DRM_ERROR("Failed to attach bridge to drm\n");
825 goto err_encoder_cleanup;
826 }
827 } else {
828
829 ret = mtk_dsi_create_connector(drm, dsi);
830 if (ret)
831 goto err_encoder_cleanup;
832 }
833
834 return 0;
835
836err_encoder_cleanup:
837 drm_encoder_cleanup(&dsi->encoder);
838 return ret;
839}
840
841static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
842{
843 drm_encoder_cleanup(&dsi->encoder);
844
845 if (dsi->conn.dev)
846 drm_connector_cleanup(&dsi->conn);
847 if (dsi->panel)
848 drm_panel_detach(dsi->panel);
849}
850
851static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
852{
853 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
854
855 mtk_dsi_poweron(dsi);
856}
857
858static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
859{
860 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
861
862 mtk_dsi_poweroff(dsi);
863}
864
865static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
866 .start = mtk_dsi_ddp_start,
867 .stop = mtk_dsi_ddp_stop,
868};
869
870static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
871 struct mipi_dsi_device *device)
872{
873 struct mtk_dsi *dsi = host_to_dsi(host);
874
875 dsi->lanes = device->lanes;
876 dsi->format = device->format;
877 dsi->mode_flags = device->mode_flags;
878
879 if (dsi->conn.dev)
880 drm_helper_hpd_irq_event(dsi->conn.dev);
881
882 return 0;
883}
884
885static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
886 struct mipi_dsi_device *device)
887{
888 struct mtk_dsi *dsi = host_to_dsi(host);
889
890 if (dsi->conn.dev)
891 drm_helper_hpd_irq_event(dsi->conn.dev);
892
893 return 0;
894}
895
896static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
897{
898 int ret;
899 u32 val;
900
901 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
902 4, 2000000);
903 if (ret) {
904 DRM_WARN("polling dsi wait not busy timeout!\n");
905
906 mtk_dsi_enable(dsi);
907 mtk_dsi_reset_engine(dsi);
908 }
909}
910
911static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
912{
913 switch (type) {
914 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
915 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
916 return 1;
917 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
918 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
919 return 2;
920 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
921 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
922 return read_data[1] + read_data[2] * 16;
923 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
924 DRM_INFO("type is 0x02, try again\n");
925 break;
926 default:
927 DRM_INFO("type(0x%x) not recognized\n", type);
928 break;
929 }
930
931 return 0;
932}
933
934static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
935{
936 const char *tx_buf = msg->tx_buf;
937 u8 config, cmdq_size, cmdq_off, type = msg->type;
938 u32 reg_val, cmdq_mask, i;
939
940 if (MTK_DSI_HOST_IS_READ(type))
941 config = BTA;
942 else
943 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
944
945 if (msg->tx_len > 2) {
946 cmdq_size = 1 + (msg->tx_len + 3) / 4;
947 cmdq_off = 4;
948 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
949 reg_val = (msg->tx_len << 16) | (type << 8) | config;
950 } else {
951 cmdq_size = 1;
952 cmdq_off = 2;
953 cmdq_mask = CONFIG | DATA_ID;
954 reg_val = (type << 8) | config;
955 }
956
957 for (i = 0; i < msg->tx_len; i++)
958 writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
959
960 mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
961 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
962}
963
964static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
965 const struct mipi_dsi_msg *msg, u8 flag)
966{
967 mtk_dsi_wait_for_idle(dsi);
968 mtk_dsi_irq_data_clear(dsi, flag);
969 mtk_dsi_cmdq(dsi, msg);
970 mtk_dsi_start(dsi);
971
972 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
973 return -ETIME;
974 else
975 return 0;
976}
977
978static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
979 const struct mipi_dsi_msg *msg)
980{
981 struct mtk_dsi *dsi = host_to_dsi(host);
982 u32 recv_cnt, i;
983 u8 read_data[16];
984 void *src_addr;
985 u8 irq_flag = CMD_DONE_INT_FLAG;
986
987 if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
988 DRM_ERROR("dsi engine is not command mode\n");
989 return -EINVAL;
990 }
991
992 if (MTK_DSI_HOST_IS_READ(msg->type))
993 irq_flag |= LPRX_RD_RDY_INT_FLAG;
994
995 if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
996 return -ETIME;
997
998 if (!MTK_DSI_HOST_IS_READ(msg->type))
999 return 0;
1000
1001 if (!msg->rx_buf) {
1002 DRM_ERROR("dsi receive buffer size may be NULL\n");
1003 return -EINVAL;
1004 }
1005
1006 for (i = 0; i < 16; i++)
1007 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1008
1009 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1010
1011 if (recv_cnt > 2)
1012 src_addr = &read_data[4];
1013 else
1014 src_addr = &read_data[1];
1015
1016 if (recv_cnt > 10)
1017 recv_cnt = 10;
1018
1019 if (recv_cnt > msg->rx_len)
1020 recv_cnt = msg->rx_len;
1021
1022 if (recv_cnt)
1023 memcpy(msg->rx_buf, src_addr, recv_cnt);
1024
1025 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1026 recv_cnt, *((u8 *)(msg->tx_buf)));
1027
1028 return recv_cnt;
1029}
1030
1031static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1032 .attach = mtk_dsi_host_attach,
1033 .detach = mtk_dsi_host_detach,
1034 .transfer = mtk_dsi_host_transfer,
1035};
1036
1037static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1038{
1039 int ret;
1040 struct drm_device *drm = data;
1041 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1042
1043 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1044 if (ret < 0) {
1045 dev_err(dev, "Failed to register component %pOF: %d\n",
1046 dev->of_node, ret);
1047 return ret;
1048 }
1049
1050 ret = mipi_dsi_host_register(&dsi->host);
1051 if (ret < 0) {
1052 dev_err(dev, "failed to register DSI host: %d\n", ret);
1053 goto err_ddp_comp_unregister;
1054 }
1055
1056 ret = mtk_dsi_create_conn_enc(drm, dsi);
1057 if (ret) {
1058 DRM_ERROR("Encoder create failed with %d\n", ret);
1059 goto err_unregister;
1060 }
1061
1062 return 0;
1063
1064err_unregister:
1065 mipi_dsi_host_unregister(&dsi->host);
1066err_ddp_comp_unregister:
1067 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1068 return ret;
1069}
1070
1071static void mtk_dsi_unbind(struct device *dev, struct device *master,
1072 void *data)
1073{
1074 struct drm_device *drm = data;
1075 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1076
1077 mtk_dsi_destroy_conn_enc(dsi);
1078 mipi_dsi_host_unregister(&dsi->host);
1079 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1080}
1081
1082static const struct component_ops mtk_dsi_component_ops = {
1083 .bind = mtk_dsi_bind,
1084 .unbind = mtk_dsi_unbind,
1085};
1086
1087static int mtk_dsi_probe(struct platform_device *pdev)
1088{
1089 struct mtk_dsi *dsi;
1090 struct device *dev = &pdev->dev;
1091 struct resource *regs;
1092 int irq_num;
1093 int comp_id;
1094 int ret;
1095
1096 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1097 if (!dsi)
1098 return -ENOMEM;
1099
1100 dsi->host.ops = &mtk_dsi_ops;
1101 dsi->host.dev = dev;
1102
1103 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1104 &dsi->panel, &dsi->bridge);
1105 if (ret)
1106 return ret;
1107
1108 dsi->engine_clk = devm_clk_get(dev, "engine");
1109 if (IS_ERR(dsi->engine_clk)) {
1110 ret = PTR_ERR(dsi->engine_clk);
1111 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1112 return ret;
1113 }
1114
1115 dsi->digital_clk = devm_clk_get(dev, "digital");
1116 if (IS_ERR(dsi->digital_clk)) {
1117 ret = PTR_ERR(dsi->digital_clk);
1118 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1119 return ret;
1120 }
1121
1122 dsi->hs_clk = devm_clk_get(dev, "hs");
1123 if (IS_ERR(dsi->hs_clk)) {
1124 ret = PTR_ERR(dsi->hs_clk);
1125 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1126 return ret;
1127 }
1128
1129 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 dsi->regs = devm_ioremap_resource(dev, regs);
1131 if (IS_ERR(dsi->regs)) {
1132 ret = PTR_ERR(dsi->regs);
1133 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1134 return ret;
1135 }
1136
1137 dsi->phy = devm_phy_get(dev, "dphy");
1138 if (IS_ERR(dsi->phy)) {
1139 ret = PTR_ERR(dsi->phy);
1140 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1141 return ret;
1142 }
1143
1144 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1145 if (comp_id < 0) {
1146 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1147 return comp_id;
1148 }
1149
1150 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1151 &mtk_dsi_funcs);
1152 if (ret) {
1153 dev_err(dev, "Failed to initialize component: %d\n", ret);
1154 return ret;
1155 }
1156
1157 irq_num = platform_get_irq(pdev, 0);
1158 if (irq_num < 0) {
1159 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1160 return -EPROBE_DEFER;
1161 }
1162
1163 irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1164 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1165 IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1166 if (ret) {
1167 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1168 return -EPROBE_DEFER;
1169 }
1170
1171 init_waitqueue_head(&dsi->irq_wait_queue);
1172
1173 platform_set_drvdata(pdev, dsi);
1174
1175 return component_add(&pdev->dev, &mtk_dsi_component_ops);
1176}
1177
1178static int mtk_dsi_remove(struct platform_device *pdev)
1179{
1180 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1181
1182 mtk_output_dsi_disable(dsi);
1183 component_del(&pdev->dev, &mtk_dsi_component_ops);
1184
1185 return 0;
1186}
1187
1188static const struct of_device_id mtk_dsi_of_match[] = {
1189 { .compatible = "mediatek,mt2701-dsi" },
1190 { .compatible = "mediatek,mt8173-dsi" },
1191 { },
1192};
1193
1194struct platform_driver mtk_dsi_driver = {
1195 .probe = mtk_dsi_probe,
1196 .remove = mtk_dsi_remove,
1197 .driver = {
1198 .name = "mtk-dsi",
1199 .of_match_table = mtk_dsi_of_match,
1200 },
1201};
1202
