1
2
3
4
5
6#include <drm/drmP.h>
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_crtc.h>
9#include <drm/drm_probe_helper.h>
10#include <drm/drm_edid.h>
11#include <linux/arm-smccc.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/hdmi.h>
15#include <linux/i2c.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/mfd/syscon.h>
19#include <linux/of_platform.h>
20#include <linux/of.h>
21#include <linux/of_gpio.h>
22#include <linux/of_graph.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
26#include <sound/hdmi-codec.h>
27#include "mtk_cec.h"
28#include "mtk_hdmi.h"
29#include "mtk_hdmi_regs.h"
30
31#define NCTS_BYTES 7
32
33enum mtk_hdmi_clk_id {
34 MTK_HDMI_CLK_HDMI_PIXEL,
35 MTK_HDMI_CLK_HDMI_PLL,
36 MTK_HDMI_CLK_AUD_BCLK,
37 MTK_HDMI_CLK_AUD_SPDIF,
38 MTK_HDMI_CLK_COUNT
39};
40
41enum hdmi_aud_input_type {
42 HDMI_AUD_INPUT_I2S = 0,
43 HDMI_AUD_INPUT_SPDIF,
44};
45
46enum hdmi_aud_i2s_fmt {
47 HDMI_I2S_MODE_RJT_24BIT = 0,
48 HDMI_I2S_MODE_RJT_16BIT,
49 HDMI_I2S_MODE_LJT_24BIT,
50 HDMI_I2S_MODE_LJT_16BIT,
51 HDMI_I2S_MODE_I2S_24BIT,
52 HDMI_I2S_MODE_I2S_16BIT
53};
54
55enum hdmi_aud_mclk {
56 HDMI_AUD_MCLK_128FS,
57 HDMI_AUD_MCLK_192FS,
58 HDMI_AUD_MCLK_256FS,
59 HDMI_AUD_MCLK_384FS,
60 HDMI_AUD_MCLK_512FS,
61 HDMI_AUD_MCLK_768FS,
62 HDMI_AUD_MCLK_1152FS,
63};
64
65enum hdmi_aud_channel_type {
66 HDMI_AUD_CHAN_TYPE_1_0 = 0,
67 HDMI_AUD_CHAN_TYPE_1_1,
68 HDMI_AUD_CHAN_TYPE_2_0,
69 HDMI_AUD_CHAN_TYPE_2_1,
70 HDMI_AUD_CHAN_TYPE_3_0,
71 HDMI_AUD_CHAN_TYPE_3_1,
72 HDMI_AUD_CHAN_TYPE_4_0,
73 HDMI_AUD_CHAN_TYPE_4_1,
74 HDMI_AUD_CHAN_TYPE_5_0,
75 HDMI_AUD_CHAN_TYPE_5_1,
76 HDMI_AUD_CHAN_TYPE_6_0,
77 HDMI_AUD_CHAN_TYPE_6_1,
78 HDMI_AUD_CHAN_TYPE_7_0,
79 HDMI_AUD_CHAN_TYPE_7_1,
80 HDMI_AUD_CHAN_TYPE_3_0_LRS,
81 HDMI_AUD_CHAN_TYPE_3_1_LRS,
82 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
83 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
84 HDMI_AUD_CHAN_TYPE_6_1_CS,
85 HDMI_AUD_CHAN_TYPE_6_1_CH,
86 HDMI_AUD_CHAN_TYPE_6_1_OH,
87 HDMI_AUD_CHAN_TYPE_6_1_CHR,
88 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
89 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
90 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
91 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
92 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
93 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
94 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
95 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
96 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
97 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
98 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
99 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
100 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
102 HDMI_AUD_CHAN_TYPE_6_0_CS,
103 HDMI_AUD_CHAN_TYPE_6_0_CH,
104 HDMI_AUD_CHAN_TYPE_6_0_OH,
105 HDMI_AUD_CHAN_TYPE_6_0_CHR,
106 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
107 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
108 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
109 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
110 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
111 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
112 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
113 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
114 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
115 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
116 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
117 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
118 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
120 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
121 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
122};
123
124enum hdmi_aud_channel_swap_type {
125 HDMI_AUD_SWAP_LR,
126 HDMI_AUD_SWAP_LFE_CC,
127 HDMI_AUD_SWAP_LSRS,
128 HDMI_AUD_SWAP_RLS_RRS,
129 HDMI_AUD_SWAP_LR_STATUS,
130};
131
132struct hdmi_audio_param {
133 enum hdmi_audio_coding_type aud_codec;
134 enum hdmi_audio_sample_size aud_sampe_size;
135 enum hdmi_aud_input_type aud_input_type;
136 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
137 enum hdmi_aud_mclk aud_mclk;
138 enum hdmi_aud_channel_type aud_input_chan_type;
139 struct hdmi_codec_params codec_params;
140};
141
142struct mtk_hdmi {
143 struct drm_bridge bridge;
144 struct drm_bridge *next_bridge;
145 struct drm_connector conn;
146 struct device *dev;
147 struct phy *phy;
148 struct device *cec_dev;
149 struct i2c_adapter *ddc_adpt;
150 struct clk *clk[MTK_HDMI_CLK_COUNT];
151 struct drm_display_mode mode;
152 bool dvi_mode;
153 u32 min_clock;
154 u32 max_clock;
155 u32 max_hdisplay;
156 u32 max_vdisplay;
157 u32 ibias;
158 u32 ibias_up;
159 struct regmap *sys_regmap;
160 unsigned int sys_offset;
161 void __iomem *regs;
162 enum hdmi_colorspace csp;
163 struct hdmi_audio_param aud_param;
164 bool audio_enable;
165 bool powered;
166 bool enabled;
167};
168
169static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
170{
171 return container_of(b, struct mtk_hdmi, bridge);
172}
173
174static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
175{
176 return container_of(c, struct mtk_hdmi, conn);
177}
178
179static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
180{
181 return readl(hdmi->regs + offset);
182}
183
184static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
185{
186 writel(val, hdmi->regs + offset);
187}
188
189static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
190{
191 void __iomem *reg = hdmi->regs + offset;
192 u32 tmp;
193
194 tmp = readl(reg);
195 tmp &= ~bits;
196 writel(tmp, reg);
197}
198
199static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
200{
201 void __iomem *reg = hdmi->regs + offset;
202 u32 tmp;
203
204 tmp = readl(reg);
205 tmp |= bits;
206 writel(tmp, reg);
207}
208
209static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
210{
211 void __iomem *reg = hdmi->regs + offset;
212 u32 tmp;
213
214 tmp = readl(reg);
215 tmp = (tmp & ~mask) | (val & mask);
216 writel(tmp, reg);
217}
218
219static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
220{
221 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
222 VIDEO_SOURCE_SEL);
223}
224
225static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
226{
227 struct arm_smccc_res res;
228 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
229
230
231
232
233
234
235
236 if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
237 regmap_update_bits(hdmi->sys_regmap,
238 hdmi->sys_offset + HDMI_SYS_CFG20,
239 0x80008005, enable ? 0x80000005 : 0x8000);
240 else
241 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
242 0x80000000, 0, 0, 0, 0, 0, &res);
243
244 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
245 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
246 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
247 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
248}
249
250static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
251{
252 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
253 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
254}
255
256static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
257{
258 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
259}
260
261static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
262{
263 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
264}
265
266static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
267{
268 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
269 HDMI_RST, HDMI_RST);
270 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
271 HDMI_RST, 0);
272 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
273 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
274 ANLG_ON, ANLG_ON);
275}
276
277static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
278{
279 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
280 CFG2_NOTICE_EN);
281}
282
283static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
284{
285 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
286}
287
288static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
289{
290 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
291}
292
293static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
294 u8 len)
295{
296 u32 ctrl_reg = GRL_CTRL;
297 int i;
298 u8 *frame_data;
299 enum hdmi_infoframe_type frame_type;
300 u8 frame_ver;
301 u8 frame_len;
302 u8 checksum;
303 int ctrl_frame_en = 0;
304
305 frame_type = *buffer;
306 buffer += 1;
307 frame_ver = *buffer;
308 buffer += 1;
309 frame_len = *buffer;
310 buffer += 1;
311 checksum = *buffer;
312 buffer += 1;
313 frame_data = buffer;
314
315 dev_dbg(hdmi->dev,
316 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
317 frame_type, frame_ver, frame_len, checksum);
318
319 switch (frame_type) {
320 case HDMI_INFOFRAME_TYPE_AVI:
321 ctrl_frame_en = CTRL_AVI_EN;
322 ctrl_reg = GRL_CTRL;
323 break;
324 case HDMI_INFOFRAME_TYPE_SPD:
325 ctrl_frame_en = CTRL_SPD_EN;
326 ctrl_reg = GRL_CTRL;
327 break;
328 case HDMI_INFOFRAME_TYPE_AUDIO:
329 ctrl_frame_en = CTRL_AUDIO_EN;
330 ctrl_reg = GRL_CTRL;
331 break;
332 case HDMI_INFOFRAME_TYPE_VENDOR:
333 ctrl_frame_en = VS_EN;
334 ctrl_reg = GRL_ACP_ISRC_CTRL;
335 break;
336 default:
337 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
338 return;
339 }
340 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
341 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
342 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
343 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
344
345 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
346 for (i = 0; i < frame_len; i++)
347 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
348
349 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
350}
351
352static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
353{
354 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
355 AUDIO_PACKET_OFF);
356}
357
358static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
359{
360 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
361 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
362 usleep_range(2000, 4000);
363 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
364 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
365}
366
367static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
368{
369 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
370 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
371 COLOR_8BIT_MODE);
372}
373
374static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
375{
376 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
377 usleep_range(2000, 4000);
378 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
379}
380
381static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
382{
383 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
384 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
385 usleep_range(2000, 4000);
386 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
387 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
388}
389
390static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
391{
392 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
393 CTS_CTRL_SOFT);
394}
395
396static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
397 bool enable)
398{
399 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
400 NCTS_WRI_ANYTIME);
401}
402
403static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
404 struct drm_display_mode *mode)
405{
406 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
407
408 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
409 mode->clock == 74250 &&
410 mode->vdisplay == 1080)
411 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
412 else
413 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
414}
415
416static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
417 enum hdmi_aud_channel_swap_type swap)
418{
419 u8 swap_bit;
420
421 switch (swap) {
422 case HDMI_AUD_SWAP_LR:
423 swap_bit = LR_SWAP;
424 break;
425 case HDMI_AUD_SWAP_LFE_CC:
426 swap_bit = LFE_CC_SWAP;
427 break;
428 case HDMI_AUD_SWAP_LSRS:
429 swap_bit = LSRS_SWAP;
430 break;
431 case HDMI_AUD_SWAP_RLS_RRS:
432 swap_bit = RLS_RRS_SWAP;
433 break;
434 case HDMI_AUD_SWAP_LR_STATUS:
435 swap_bit = LR_STATUS_SWAP;
436 break;
437 default:
438 swap_bit = LFE_CC_SWAP;
439 break;
440 }
441 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
442}
443
444static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
445 enum hdmi_audio_sample_size bit_num)
446{
447 u32 val;
448
449 switch (bit_num) {
450 case HDMI_AUDIO_SAMPLE_SIZE_16:
451 val = AOUT_16BIT;
452 break;
453 case HDMI_AUDIO_SAMPLE_SIZE_20:
454 val = AOUT_20BIT;
455 break;
456 case HDMI_AUDIO_SAMPLE_SIZE_24:
457 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
458 val = AOUT_24BIT;
459 break;
460 }
461
462 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
463}
464
465static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
466 enum hdmi_aud_i2s_fmt i2s_fmt)
467{
468 u32 val;
469
470 val = mtk_hdmi_read(hdmi, GRL_CFG0);
471 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
472
473 switch (i2s_fmt) {
474 case HDMI_I2S_MODE_RJT_24BIT:
475 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
476 break;
477 case HDMI_I2S_MODE_RJT_16BIT:
478 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
479 break;
480 case HDMI_I2S_MODE_LJT_24BIT:
481 default:
482 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
483 break;
484 case HDMI_I2S_MODE_LJT_16BIT:
485 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
486 break;
487 case HDMI_I2S_MODE_I2S_24BIT:
488 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
489 break;
490 case HDMI_I2S_MODE_I2S_16BIT:
491 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
492 break;
493 }
494 mtk_hdmi_write(hdmi, GRL_CFG0, val);
495}
496
497static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
498{
499 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
500 u8 val;
501
502
503 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
504
505 if (dst)
506 val = DST_NORMAL_DOUBLE | SACD_DST;
507 else
508 val = 0;
509
510 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
511}
512
513static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
514 enum hdmi_aud_channel_type channel_type,
515 u8 channel_count)
516{
517 unsigned int ch_switch;
518 u8 i2s_uv;
519
520 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
521 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
522 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
523 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
524
525 if (channel_count == 2) {
526 i2s_uv = I2S_UV_CH_EN(0);
527 } else if (channel_count == 3 || channel_count == 4) {
528 if (channel_count == 4 &&
529 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
530 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
531 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
532 else
533 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
534 } else if (channel_count == 6 || channel_count == 5) {
535 if (channel_count == 6 &&
536 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
537 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
538 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
539 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
540 } else {
541 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
542 I2S_UV_CH_EN(0);
543 }
544 } else if (channel_count == 8 || channel_count == 7) {
545 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
546 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
547 } else {
548 i2s_uv = I2S_UV_CH_EN(0);
549 }
550
551 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
552 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
553 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
554 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
555}
556
557static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
558 enum hdmi_aud_input_type input_type)
559{
560 u32 val;
561
562 val = mtk_hdmi_read(hdmi, GRL_CFG1);
563 if (input_type == HDMI_AUD_INPUT_I2S &&
564 (val & CFG1_SPDIF) == CFG1_SPDIF) {
565 val &= ~CFG1_SPDIF;
566 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
567 (val & CFG1_SPDIF) == 0) {
568 val |= CFG1_SPDIF;
569 }
570 mtk_hdmi_write(hdmi, GRL_CFG1, val);
571}
572
573static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
574 u8 *channel_status)
575{
576 int i;
577
578 for (i = 0; i < 5; i++) {
579 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
580 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
581 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
582 }
583 for (; i < 24; i++) {
584 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
585 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
586 }
587}
588
589static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
590{
591 u32 val;
592
593 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
594 if (val & MIX_CTRL_SRC_EN) {
595 val &= ~MIX_CTRL_SRC_EN;
596 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
597 usleep_range(255, 512);
598 val |= MIX_CTRL_SRC_EN;
599 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
600 }
601}
602
603static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
604{
605 u32 val;
606
607 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
608 val &= ~MIX_CTRL_SRC_EN;
609 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
610 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
611}
612
613static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
614 enum hdmi_aud_mclk mclk)
615{
616 u32 val;
617
618 val = mtk_hdmi_read(hdmi, GRL_CFG5);
619 val &= CFG5_CD_RATIO_MASK;
620
621 switch (mclk) {
622 case HDMI_AUD_MCLK_128FS:
623 val |= CFG5_FS128;
624 break;
625 case HDMI_AUD_MCLK_256FS:
626 val |= CFG5_FS256;
627 break;
628 case HDMI_AUD_MCLK_384FS:
629 val |= CFG5_FS384;
630 break;
631 case HDMI_AUD_MCLK_512FS:
632 val |= CFG5_FS512;
633 break;
634 case HDMI_AUD_MCLK_768FS:
635 val |= CFG5_FS768;
636 break;
637 default:
638 val |= CFG5_FS256;
639 break;
640 }
641 mtk_hdmi_write(hdmi, GRL_CFG5, val);
642}
643
644struct hdmi_acr_n {
645 unsigned int clock;
646 unsigned int n[3];
647};
648
649
650static const struct hdmi_acr_n hdmi_rec_n_table[] = {
651
652 { 25175, { 4576, 7007, 6864 } },
653 { 74176, { 11648, 17836, 11648 } },
654 { 148352, { 11648, 8918, 5824 } },
655 { 296703, { 5824, 4459, 5824 } },
656 { 297000, { 3072, 4704, 5120 } },
657 { 0, { 4096, 6272, 6144 } },
658};
659
660
661
662
663
664
665static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
666{
667 const struct hdmi_acr_n *recommended;
668 unsigned int i;
669
670 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
671 if (clock == hdmi_rec_n_table[i].clock)
672 break;
673 }
674 recommended = hdmi_rec_n_table + i;
675
676 switch (freq) {
677 case 32000:
678 return recommended->n[0];
679 case 44100:
680 return recommended->n[1];
681 case 48000:
682 return recommended->n[2];
683 case 88200:
684 return recommended->n[1] * 2;
685 case 96000:
686 return recommended->n[2] * 2;
687 case 176400:
688 return recommended->n[1] * 4;
689 case 192000:
690 return recommended->n[2] * 4;
691 default:
692 return (128 * freq) / 1000;
693 }
694}
695
696static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
697{
698 switch (clock) {
699 case 25175:
700 return 25174825;
701 case 74176:
702 return 74175824;
703 case 148352:
704 return 148351648;
705 case 296703:
706 return 296703297;
707 default:
708 return clock * 1000;
709 }
710}
711
712static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
713 unsigned int tmds_clock, unsigned int n)
714{
715 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
716 128 * audio_sample_rate);
717}
718
719static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
720 unsigned int cts)
721{
722 unsigned char val[NCTS_BYTES];
723 int i;
724
725 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
726 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
727 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
728 memset(val, 0, sizeof(val));
729
730 val[0] = (cts >> 24) & 0xff;
731 val[1] = (cts >> 16) & 0xff;
732 val[2] = (cts >> 8) & 0xff;
733 val[3] = cts & 0xff;
734
735 val[4] = (n >> 16) & 0xff;
736 val[5] = (n >> 8) & 0xff;
737 val[6] = n & 0xff;
738
739 for (i = 0; i < NCTS_BYTES; i++)
740 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
741}
742
743static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
744 unsigned int sample_rate,
745 unsigned int clock)
746{
747 unsigned int n, cts;
748
749 n = hdmi_recommended_n(sample_rate, clock);
750 cts = hdmi_expected_cts(sample_rate, clock, n);
751
752 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
753 __func__, sample_rate, clock, n, cts);
754
755 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
756 AUDIO_I2S_NCTS_SEL);
757 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
758}
759
760static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
761{
762 switch (channel_type) {
763 case HDMI_AUD_CHAN_TYPE_1_0:
764 case HDMI_AUD_CHAN_TYPE_1_1:
765 case HDMI_AUD_CHAN_TYPE_2_0:
766 return 2;
767 case HDMI_AUD_CHAN_TYPE_2_1:
768 case HDMI_AUD_CHAN_TYPE_3_0:
769 return 3;
770 case HDMI_AUD_CHAN_TYPE_3_1:
771 case HDMI_AUD_CHAN_TYPE_4_0:
772 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
773 return 4;
774 case HDMI_AUD_CHAN_TYPE_4_1:
775 case HDMI_AUD_CHAN_TYPE_5_0:
776 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
777 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
778 return 5;
779 case HDMI_AUD_CHAN_TYPE_5_1:
780 case HDMI_AUD_CHAN_TYPE_6_0:
781 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
782 case HDMI_AUD_CHAN_TYPE_6_0_CS:
783 case HDMI_AUD_CHAN_TYPE_6_0_CH:
784 case HDMI_AUD_CHAN_TYPE_6_0_OH:
785 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
786 return 6;
787 case HDMI_AUD_CHAN_TYPE_6_1:
788 case HDMI_AUD_CHAN_TYPE_6_1_CS:
789 case HDMI_AUD_CHAN_TYPE_6_1_CH:
790 case HDMI_AUD_CHAN_TYPE_6_1_OH:
791 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
792 case HDMI_AUD_CHAN_TYPE_7_0:
793 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
794 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
795 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
796 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
797 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
798 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
799 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
800 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
801 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
802 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
803 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
804 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
805 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
806 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
807 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
808 return 7;
809 case HDMI_AUD_CHAN_TYPE_7_1:
810 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
811 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
812 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
813 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
814 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
815 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
816 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
817 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
818 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
819 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
820 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
821 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
822 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
823 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
824 return 8;
825 default:
826 return 2;
827 }
828}
829
830static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
831{
832 unsigned long rate;
833 int ret;
834
835
836 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
837 if (ret) {
838 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
839 ret);
840 return ret;
841 }
842
843 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
844
845 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
846 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
847 rate);
848 else
849 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
850
851 mtk_hdmi_hw_config_sys(hdmi);
852 mtk_hdmi_hw_set_deep_color_mode(hdmi);
853 return 0;
854}
855
856static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
857 struct drm_display_mode *mode)
858{
859 mtk_hdmi_hw_reset(hdmi);
860 mtk_hdmi_hw_enable_notice(hdmi, true);
861 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
862 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
863 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
864
865 mtk_hdmi_hw_msic_setting(hdmi, mode);
866}
867
868static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
869{
870 mtk_hdmi_hw_send_aud_packet(hdmi, enable);
871 return 0;
872}
873
874static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
875{
876 mtk_hdmi_hw_ncts_enable(hdmi, on);
877 return 0;
878}
879
880static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
881{
882 enum hdmi_aud_channel_type chan_type;
883 u8 chan_count;
884 bool dst;
885
886 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
887 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
888
889 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
890 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
891 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
892 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
893 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
894 }
895
896 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
897 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
898
899 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
900 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
901 mtk_hdmi_hw_audio_config(hdmi, dst);
902
903 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
904 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
905 else
906 chan_type = hdmi->aud_param.aud_input_chan_type;
907 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
908 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
909 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
910
911 return 0;
912}
913
914static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
915 struct drm_display_mode *display_mode)
916{
917 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
918
919 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
920 mtk_hdmi_hw_aud_src_disable(hdmi);
921 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
922
923 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
924 switch (sample_rate) {
925 case 32000:
926 case 44100:
927 case 48000:
928 case 88200:
929 case 96000:
930 break;
931 default:
932 return -EINVAL;
933 }
934 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
935 } else {
936 switch (sample_rate) {
937 case 32000:
938 case 44100:
939 case 48000:
940 break;
941 default:
942 return -EINVAL;
943 }
944 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
945 }
946
947 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
948
949 mtk_hdmi_hw_aud_src_reenable(hdmi);
950 return 0;
951}
952
953static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
954 struct drm_display_mode *display_mode)
955{
956 mtk_hdmi_hw_aud_mute(hdmi);
957 mtk_hdmi_aud_enable_packet(hdmi, false);
958
959 mtk_hdmi_aud_set_input(hdmi);
960 mtk_hdmi_aud_set_src(hdmi, display_mode);
961 mtk_hdmi_hw_aud_set_channel_status(hdmi,
962 hdmi->aud_param.codec_params.iec.status);
963
964 usleep_range(50, 100);
965
966 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
967 mtk_hdmi_aud_enable_packet(hdmi, true);
968 mtk_hdmi_hw_aud_unmute(hdmi);
969 return 0;
970}
971
972static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
973 struct drm_display_mode *mode)
974{
975 struct hdmi_avi_infoframe frame;
976 u8 buffer[17];
977 ssize_t err;
978
979 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
980 &hdmi->conn, mode);
981 if (err < 0) {
982 dev_err(hdmi->dev,
983 "Failed to get AVI infoframe from mode: %zd\n", err);
984 return err;
985 }
986
987 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
988 if (err < 0) {
989 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
990 return err;
991 }
992
993 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
994 return 0;
995}
996
997static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
998 const char *vendor,
999 const char *product)
1000{
1001 struct hdmi_spd_infoframe frame;
1002 u8 buffer[29];
1003 ssize_t err;
1004
1005 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1006 if (err < 0) {
1007 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1008 err);
1009 return err;
1010 }
1011
1012 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1013 if (err < 0) {
1014 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1015 return err;
1016 }
1017
1018 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1019 return 0;
1020}
1021
1022static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1023{
1024 struct hdmi_audio_infoframe frame;
1025 u8 buffer[14];
1026 ssize_t err;
1027
1028 err = hdmi_audio_infoframe_init(&frame);
1029 if (err < 0) {
1030 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1031 err);
1032 return err;
1033 }
1034
1035 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1036 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1037 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1038 frame.channels = mtk_hdmi_aud_get_chnl_count(
1039 hdmi->aud_param.aud_input_chan_type);
1040
1041 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1042 if (err < 0) {
1043 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1044 err);
1045 return err;
1046 }
1047
1048 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1049 return 0;
1050}
1051
1052static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1053 struct drm_display_mode *mode)
1054{
1055 struct hdmi_vendor_infoframe frame;
1056 u8 buffer[10];
1057 ssize_t err;
1058
1059 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1060 &hdmi->conn, mode);
1061 if (err) {
1062 dev_err(hdmi->dev,
1063 "Failed to get vendor infoframe from mode: %zd\n", err);
1064 return err;
1065 }
1066
1067 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1068 if (err < 0) {
1069 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1070 err);
1071 return err;
1072 }
1073
1074 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1075 return 0;
1076}
1077
1078static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1079{
1080 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1081
1082 hdmi->csp = HDMI_COLORSPACE_RGB;
1083 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1084 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1085 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1086 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1087 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1088 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1089
1090 return 0;
1091}
1092
1093static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1094{
1095 mtk_hdmi_aud_enable_packet(hdmi, true);
1096 hdmi->audio_enable = true;
1097}
1098
1099static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1100{
1101 mtk_hdmi_aud_enable_packet(hdmi, false);
1102 hdmi->audio_enable = false;
1103}
1104
1105static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1106 struct hdmi_audio_param *param)
1107{
1108 if (!hdmi->audio_enable) {
1109 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1110 return -EINVAL;
1111 }
1112 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1113 param->aud_codec, param->aud_input_type,
1114 param->aud_input_chan_type, param->codec_params.sample_rate);
1115 memcpy(&hdmi->aud_param, param, sizeof(*param));
1116 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1117}
1118
1119static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1120 struct drm_display_mode *mode)
1121{
1122 int ret;
1123
1124 mtk_hdmi_hw_vid_black(hdmi, true);
1125 mtk_hdmi_hw_aud_mute(hdmi);
1126 mtk_hdmi_hw_send_av_mute(hdmi);
1127 phy_power_off(hdmi->phy);
1128
1129 ret = mtk_hdmi_video_change_vpll(hdmi,
1130 mode->clock * 1000);
1131 if (ret) {
1132 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1133 return ret;
1134 }
1135 mtk_hdmi_video_set_display_mode(hdmi, mode);
1136
1137 phy_power_on(hdmi->phy);
1138 mtk_hdmi_aud_output_config(hdmi, mode);
1139
1140 mtk_hdmi_hw_vid_black(hdmi, false);
1141 mtk_hdmi_hw_aud_unmute(hdmi);
1142 mtk_hdmi_hw_send_av_unmute(hdmi);
1143
1144 return 0;
1145}
1146
1147static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1148 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1149 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1150 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1151 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1152};
1153
1154static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1155 struct device_node *np)
1156{
1157 int i;
1158
1159 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1160 hdmi->clk[i] = of_clk_get_by_name(np,
1161 mtk_hdmi_clk_names[i]);
1162 if (IS_ERR(hdmi->clk[i]))
1163 return PTR_ERR(hdmi->clk[i]);
1164 }
1165 return 0;
1166}
1167
1168static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1169{
1170 int ret;
1171
1172 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1173 if (ret)
1174 return ret;
1175
1176 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1177 if (ret)
1178 goto err;
1179
1180 return 0;
1181err:
1182 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1183 return ret;
1184}
1185
1186static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1187{
1188 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1189 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1190}
1191
1192static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1193 bool force)
1194{
1195 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1196
1197 return mtk_cec_hpd_high(hdmi->cec_dev) ?
1198 connector_status_connected : connector_status_disconnected;
1199}
1200
1201static void hdmi_conn_destroy(struct drm_connector *conn)
1202{
1203 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1204
1205 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1206
1207 drm_connector_cleanup(conn);
1208}
1209
1210static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1211{
1212 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1213 struct edid *edid;
1214 int ret;
1215
1216 if (!hdmi->ddc_adpt)
1217 return -ENODEV;
1218
1219 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1220 if (!edid)
1221 return -ENODEV;
1222
1223 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1224
1225 drm_connector_update_edid_property(conn, edid);
1226
1227 ret = drm_add_edid_modes(conn, edid);
1228 kfree(edid);
1229 return ret;
1230}
1231
1232static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1233 struct drm_display_mode *mode)
1234{
1235 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1236
1237 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1238 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1239 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1240
1241 if (hdmi->bridge.next) {
1242 struct drm_display_mode adjusted_mode;
1243
1244 drm_mode_copy(&adjusted_mode, mode);
1245 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1246 &adjusted_mode))
1247 return MODE_BAD;
1248 }
1249
1250 if (mode->clock < 27000)
1251 return MODE_CLOCK_LOW;
1252 if (mode->clock > 297000)
1253 return MODE_CLOCK_HIGH;
1254
1255 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1256}
1257
1258static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1259{
1260 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1261
1262 return hdmi->bridge.encoder;
1263}
1264
1265static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1266 .detect = hdmi_conn_detect,
1267 .fill_modes = drm_helper_probe_single_connector_modes,
1268 .destroy = hdmi_conn_destroy,
1269 .reset = drm_atomic_helper_connector_reset,
1270 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1271 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1272};
1273
1274static const struct drm_connector_helper_funcs
1275 mtk_hdmi_connector_helper_funcs = {
1276 .get_modes = mtk_hdmi_conn_get_modes,
1277 .mode_valid = mtk_hdmi_conn_mode_valid,
1278 .best_encoder = mtk_hdmi_conn_best_enc,
1279};
1280
1281static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1282{
1283 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1284
1285 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1286 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1287}
1288
1289
1290
1291
1292
1293static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1294{
1295 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1296 int ret;
1297
1298 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1299 &mtk_hdmi_connector_funcs,
1300 DRM_MODE_CONNECTOR_HDMIA);
1301 if (ret) {
1302 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1303 return ret;
1304 }
1305 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1306
1307 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1308 hdmi->conn.interlace_allowed = true;
1309 hdmi->conn.doublescan_allowed = false;
1310
1311 ret = drm_connector_attach_encoder(&hdmi->conn,
1312 bridge->encoder);
1313 if (ret) {
1314 dev_err(hdmi->dev,
1315 "Failed to attach connector to encoder: %d\n", ret);
1316 return ret;
1317 }
1318
1319 if (hdmi->next_bridge) {
1320 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1321 bridge);
1322 if (ret) {
1323 dev_err(hdmi->dev,
1324 "Failed to attach external bridge: %d\n", ret);
1325 return ret;
1326 }
1327 }
1328
1329 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1330
1331 return 0;
1332}
1333
1334static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1335 const struct drm_display_mode *mode,
1336 struct drm_display_mode *adjusted_mode)
1337{
1338 return true;
1339}
1340
1341static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1342{
1343 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1344
1345 if (!hdmi->enabled)
1346 return;
1347
1348 phy_power_off(hdmi->phy);
1349 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1350 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1351
1352 hdmi->enabled = false;
1353}
1354
1355static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1356{
1357 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1358
1359 if (!hdmi->powered)
1360 return;
1361
1362 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1363 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1364
1365 hdmi->powered = false;
1366}
1367
1368static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1369 const struct drm_display_mode *mode,
1370 const struct drm_display_mode *adjusted_mode)
1371{
1372 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1373
1374 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1375 adjusted_mode->name, adjusted_mode->hdisplay);
1376 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1377 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1378 adjusted_mode->htotal);
1379 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1380 adjusted_mode->hskew, adjusted_mode->vdisplay);
1381 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1382 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1383 adjusted_mode->vtotal);
1384 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1385 adjusted_mode->vscan, adjusted_mode->flags);
1386
1387 drm_mode_copy(&hdmi->mode, adjusted_mode);
1388}
1389
1390static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1391{
1392 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1393
1394 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1395 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1396
1397 hdmi->powered = true;
1398}
1399
1400static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1401 struct drm_display_mode *mode)
1402{
1403 mtk_hdmi_setup_audio_infoframe(hdmi);
1404 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1405 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1406 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1407 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1408}
1409
1410static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1411{
1412 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1413
1414 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1415 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1416 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1417 phy_power_on(hdmi->phy);
1418 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1419
1420 hdmi->enabled = true;
1421}
1422
1423static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1424 .attach = mtk_hdmi_bridge_attach,
1425 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1426 .disable = mtk_hdmi_bridge_disable,
1427 .post_disable = mtk_hdmi_bridge_post_disable,
1428 .mode_set = mtk_hdmi_bridge_mode_set,
1429 .pre_enable = mtk_hdmi_bridge_pre_enable,
1430 .enable = mtk_hdmi_bridge_enable,
1431};
1432
1433static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1434 struct platform_device *pdev)
1435{
1436 struct device *dev = &pdev->dev;
1437 struct device_node *np = dev->of_node;
1438 struct device_node *cec_np, *remote, *i2c_np;
1439 struct platform_device *cec_pdev;
1440 struct regmap *regmap;
1441 struct resource *mem;
1442 int ret;
1443
1444 ret = mtk_hdmi_get_all_clk(hdmi, np);
1445 if (ret) {
1446 dev_err(dev, "Failed to get clocks: %d\n", ret);
1447 return ret;
1448 }
1449
1450
1451 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1452 if (!cec_np) {
1453 dev_err(dev, "Failed to find CEC node\n");
1454 return -EINVAL;
1455 }
1456
1457 cec_pdev = of_find_device_by_node(cec_np);
1458 if (!cec_pdev) {
1459 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1460 cec_np);
1461 of_node_put(cec_np);
1462 return -EPROBE_DEFER;
1463 }
1464 of_node_put(cec_np);
1465 hdmi->cec_dev = &cec_pdev->dev;
1466
1467
1468
1469
1470
1471
1472 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1473 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1474 &hdmi->sys_offset);
1475 if (IS_ERR(regmap))
1476 ret = PTR_ERR(regmap);
1477 if (ret) {
1478 dev_err(dev,
1479 "Failed to get system configuration registers: %d\n",
1480 ret);
1481 return ret;
1482 }
1483 hdmi->sys_regmap = regmap;
1484
1485 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486 hdmi->regs = devm_ioremap_resource(dev, mem);
1487 if (IS_ERR(hdmi->regs))
1488 return PTR_ERR(hdmi->regs);
1489
1490 remote = of_graph_get_remote_node(np, 1, 0);
1491 if (!remote)
1492 return -EINVAL;
1493
1494 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1495 hdmi->next_bridge = of_drm_find_bridge(remote);
1496 if (!hdmi->next_bridge) {
1497 dev_err(dev, "Waiting for external bridge\n");
1498 of_node_put(remote);
1499 return -EPROBE_DEFER;
1500 }
1501 }
1502
1503 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1504 if (!i2c_np) {
1505 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1506 remote);
1507 of_node_put(remote);
1508 return -EINVAL;
1509 }
1510 of_node_put(remote);
1511
1512 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1513 of_node_put(i2c_np);
1514 if (!hdmi->ddc_adpt) {
1515 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1516 return -EINVAL;
1517 }
1518
1519 return 0;
1520}
1521
1522
1523
1524
1525
1526static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1527 struct hdmi_codec_daifmt *daifmt,
1528 struct hdmi_codec_params *params)
1529{
1530 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1531 struct hdmi_audio_param hdmi_params;
1532 unsigned int chan = params->cea.channels;
1533
1534 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1535 params->sample_rate, params->sample_width, chan);
1536
1537 if (!hdmi->bridge.encoder)
1538 return -ENODEV;
1539
1540 switch (chan) {
1541 case 2:
1542 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1543 break;
1544 case 4:
1545 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1546 break;
1547 case 6:
1548 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1549 break;
1550 case 8:
1551 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1552 break;
1553 default:
1554 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1555 return -EINVAL;
1556 }
1557
1558 switch (params->sample_rate) {
1559 case 32000:
1560 case 44100:
1561 case 48000:
1562 case 88200:
1563 case 96000:
1564 case 176400:
1565 case 192000:
1566 break;
1567 default:
1568 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1569 params->sample_rate);
1570 return -EINVAL;
1571 }
1572
1573 switch (daifmt->fmt) {
1574 case HDMI_I2S:
1575 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1576 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1577 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1578 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1579 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1580 break;
1581 case HDMI_SPDIF:
1582 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1583 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1584 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1585 break;
1586 default:
1587 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1588 daifmt->fmt);
1589 return -EINVAL;
1590 }
1591
1592 memcpy(&hdmi_params.codec_params, params,
1593 sizeof(hdmi_params.codec_params));
1594
1595 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1596
1597 return 0;
1598}
1599
1600static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1601{
1602 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1603
1604 dev_dbg(dev, "%s\n", __func__);
1605
1606 mtk_hdmi_audio_enable(hdmi);
1607
1608 return 0;
1609}
1610
1611static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1612{
1613 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1614
1615 dev_dbg(dev, "%s\n", __func__);
1616
1617 mtk_hdmi_audio_disable(hdmi);
1618}
1619
1620static int
1621mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1622{
1623 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1624
1625 dev_dbg(dev, "%s(%d)\n", __func__, enable);
1626
1627 if (enable)
1628 mtk_hdmi_hw_aud_mute(hdmi);
1629 else
1630 mtk_hdmi_hw_aud_unmute(hdmi);
1631
1632 return 0;
1633}
1634
1635static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1636{
1637 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1638
1639 dev_dbg(dev, "%s\n", __func__);
1640
1641 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1642
1643 return 0;
1644}
1645
1646static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1647 .hw_params = mtk_hdmi_audio_hw_params,
1648 .audio_startup = mtk_hdmi_audio_startup,
1649 .audio_shutdown = mtk_hdmi_audio_shutdown,
1650 .digital_mute = mtk_hdmi_audio_digital_mute,
1651 .get_eld = mtk_hdmi_audio_get_eld,
1652};
1653
1654static void mtk_hdmi_register_audio_driver(struct device *dev)
1655{
1656 struct hdmi_codec_pdata codec_data = {
1657 .ops = &mtk_hdmi_audio_codec_ops,
1658 .max_i2s_channels = 2,
1659 .i2s = 1,
1660 };
1661 struct platform_device *pdev;
1662
1663 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1664 PLATFORM_DEVID_AUTO, &codec_data,
1665 sizeof(codec_data));
1666 if (IS_ERR(pdev))
1667 return;
1668
1669 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1670}
1671
1672static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1673{
1674 struct mtk_hdmi *hdmi;
1675 struct device *dev = &pdev->dev;
1676 int ret;
1677
1678 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1679 if (!hdmi)
1680 return -ENOMEM;
1681
1682 hdmi->dev = dev;
1683
1684 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1685 if (ret)
1686 return ret;
1687
1688 hdmi->phy = devm_phy_get(dev, "hdmi");
1689 if (IS_ERR(hdmi->phy)) {
1690 ret = PTR_ERR(hdmi->phy);
1691 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1692 return ret;
1693 }
1694
1695 platform_set_drvdata(pdev, hdmi);
1696
1697 ret = mtk_hdmi_output_init(hdmi);
1698 if (ret) {
1699 dev_err(dev, "Failed to initialize hdmi output\n");
1700 return ret;
1701 }
1702
1703 mtk_hdmi_register_audio_driver(dev);
1704
1705 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1706 hdmi->bridge.of_node = pdev->dev.of_node;
1707 drm_bridge_add(&hdmi->bridge);
1708
1709 ret = mtk_hdmi_clk_enable_audio(hdmi);
1710 if (ret) {
1711 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1712 goto err_bridge_remove;
1713 }
1714
1715 dev_dbg(dev, "mediatek hdmi probe success\n");
1716 return 0;
1717
1718err_bridge_remove:
1719 drm_bridge_remove(&hdmi->bridge);
1720 return ret;
1721}
1722
1723static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1724{
1725 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1726
1727 drm_bridge_remove(&hdmi->bridge);
1728 mtk_hdmi_clk_disable_audio(hdmi);
1729 return 0;
1730}
1731
1732#ifdef CONFIG_PM_SLEEP
1733static int mtk_hdmi_suspend(struct device *dev)
1734{
1735 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1736
1737 mtk_hdmi_clk_disable_audio(hdmi);
1738 dev_dbg(dev, "hdmi suspend success!\n");
1739 return 0;
1740}
1741
1742static int mtk_hdmi_resume(struct device *dev)
1743{
1744 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1745 int ret = 0;
1746
1747 ret = mtk_hdmi_clk_enable_audio(hdmi);
1748 if (ret) {
1749 dev_err(dev, "hdmi resume failed!\n");
1750 return ret;
1751 }
1752
1753 dev_dbg(dev, "hdmi resume success!\n");
1754 return 0;
1755}
1756#endif
1757static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1758 mtk_hdmi_suspend, mtk_hdmi_resume);
1759
1760static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1761 { .compatible = "mediatek,mt8173-hdmi", },
1762 {}
1763};
1764
1765static struct platform_driver mtk_hdmi_driver = {
1766 .probe = mtk_drm_hdmi_probe,
1767 .remove = mtk_drm_hdmi_remove,
1768 .driver = {
1769 .name = "mediatek-drm-hdmi",
1770 .of_match_table = mtk_drm_hdmi_of_ids,
1771 .pm = &mtk_hdmi_pm_ops,
1772 },
1773};
1774
1775static struct platform_driver * const mtk_hdmi_drivers[] = {
1776 &mtk_hdmi_phy_driver,
1777 &mtk_hdmi_ddc_driver,
1778 &mtk_cec_driver,
1779 &mtk_hdmi_driver,
1780};
1781
1782static int __init mtk_hdmitx_init(void)
1783{
1784 return platform_register_drivers(mtk_hdmi_drivers,
1785 ARRAY_SIZE(mtk_hdmi_drivers));
1786}
1787
1788static void __exit mtk_hdmitx_exit(void)
1789{
1790 platform_unregister_drivers(mtk_hdmi_drivers,
1791 ARRAY_SIZE(mtk_hdmi_drivers));
1792}
1793
1794module_init(mtk_hdmitx_init);
1795module_exit(mtk_hdmitx_exit);
1796
1797MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1798MODULE_DESCRIPTION("MediaTek HDMI Driver");
1799MODULE_LICENSE("GPL v2");
1800
