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9#ifndef __ADRENO_GPU_H__
10#define __ADRENO_GPU_H__
11
12#include <linux/firmware.h>
13#include <linux/iopoll.h>
14
15#include "msm_gpu.h"
16
17#include "adreno_common.xml.h"
18#include "adreno_pm4.xml.h"
19
20#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
21#define REG_SKIP ~0
22#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
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28
29
30enum adreno_regs {
31 REG_ADRENO_CP_RB_BASE,
32 REG_ADRENO_CP_RB_BASE_HI,
33 REG_ADRENO_CP_RB_RPTR_ADDR,
34 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
35 REG_ADRENO_CP_RB_RPTR,
36 REG_ADRENO_CP_RB_WPTR,
37 REG_ADRENO_CP_RB_CNTL,
38 REG_ADRENO_REGISTER_MAX,
39};
40
41enum {
42 ADRENO_FW_PM4 = 0,
43 ADRENO_FW_SQE = 0,
44 ADRENO_FW_PFP = 1,
45 ADRENO_FW_GMU = 1,
46 ADRENO_FW_GPMU = 2,
47 ADRENO_FW_MAX,
48};
49
50enum adreno_quirks {
51 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
52 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
53 ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
54};
55
56struct adreno_rev {
57 uint8_t core;
58 uint8_t major;
59 uint8_t minor;
60 uint8_t patchid;
61};
62
63#define ADRENO_REV(core, major, minor, patchid) \
64 ((struct adreno_rev){ core, major, minor, patchid })
65
66struct adreno_gpu_funcs {
67 struct msm_gpu_funcs base;
68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
69};
70
71struct adreno_info {
72 struct adreno_rev rev;
73 uint32_t revn;
74 const char *name;
75 const char *fw[ADRENO_FW_MAX];
76 uint32_t gmem;
77 enum adreno_quirks quirks;
78 struct msm_gpu *(*init)(struct drm_device *dev);
79 const char *zapfw;
80 u32 inactive_period;
81};
82
83const struct adreno_info *adreno_info(struct adreno_rev rev);
84
85struct adreno_gpu {
86 struct msm_gpu base;
87 struct adreno_rev rev;
88 const struct adreno_info *info;
89 uint32_t gmem;
90 uint32_t revn;
91 const struct adreno_gpu_funcs *funcs;
92
93
94 const unsigned int *registers;
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109
110 enum {
111 FW_LOCATION_UNKNOWN = 0,
112 FW_LOCATION_NEW,
113 FW_LOCATION_LEGACY,
114 FW_LOCATION_HELPER,
115 } fwloc;
116
117
118 const struct firmware *fw[ADRENO_FW_MAX];
119
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123
124
125 const unsigned int *reg_offsets;
126};
127#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
128
129
130struct adreno_platform_config {
131 struct adreno_rev rev;
132};
133
134#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
135
136#define spin_until(X) ({ \
137 int __ret = -ETIMEDOUT; \
138 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
139 do { \
140 if (X) { \
141 __ret = 0; \
142 break; \
143 } \
144 } while (time_before(jiffies, __t)); \
145 __ret; \
146})
147
148static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
149{
150 return (gpu->revn < 300);
151}
152
153static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
154{
155 return (gpu->revn < 210);
156}
157
158static inline bool adreno_is_a225(struct adreno_gpu *gpu)
159{
160 return gpu->revn == 225;
161}
162
163static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
164{
165 return (gpu->revn >= 300) && (gpu->revn < 400);
166}
167
168static inline bool adreno_is_a305(struct adreno_gpu *gpu)
169{
170 return gpu->revn == 305;
171}
172
173static inline bool adreno_is_a306(struct adreno_gpu *gpu)
174{
175
176 return gpu->revn == 307;
177}
178
179static inline bool adreno_is_a320(struct adreno_gpu *gpu)
180{
181 return gpu->revn == 320;
182}
183
184static inline bool adreno_is_a330(struct adreno_gpu *gpu)
185{
186 return gpu->revn == 330;
187}
188
189static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
190{
191 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
192}
193
194static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
195{
196 return (gpu->revn >= 400) && (gpu->revn < 500);
197}
198
199static inline int adreno_is_a420(struct adreno_gpu *gpu)
200{
201 return gpu->revn == 420;
202}
203
204static inline int adreno_is_a430(struct adreno_gpu *gpu)
205{
206 return gpu->revn == 430;
207}
208
209static inline int adreno_is_a530(struct adreno_gpu *gpu)
210{
211 return gpu->revn == 530;
212}
213
214static inline int adreno_is_a540(struct adreno_gpu *gpu)
215{
216 return gpu->revn == 540;
217}
218
219int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
220const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
221 const char *fwname);
222struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
223 const struct firmware *fw, u64 *iova);
224int adreno_hw_init(struct msm_gpu *gpu);
225void adreno_recover(struct msm_gpu *gpu);
226void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
227 struct msm_file_private *ctx);
228void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
229bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
230#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
231void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
232 struct drm_printer *p);
233#endif
234void adreno_dump_info(struct msm_gpu *gpu);
235void adreno_dump(struct msm_gpu *gpu);
236void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
237struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
238
239int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
240 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
241 int nr_rings);
242void adreno_gpu_cleanup(struct adreno_gpu *gpu);
243int adreno_load_fw(struct adreno_gpu *adreno_gpu);
244
245void adreno_gpu_state_destroy(struct msm_gpu_state *state);
246
247int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
248int adreno_gpu_state_put(struct msm_gpu_state *state);
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253
254int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
255
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257
258static inline void
259OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
260{
261 adreno_wait_ring(ring, cnt+1);
262 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
263}
264
265
266static inline void
267OUT_PKT2(struct msm_ringbuffer *ring)
268{
269 adreno_wait_ring(ring, 1);
270 OUT_RING(ring, CP_TYPE2_PKT);
271}
272
273static inline void
274OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
275{
276 adreno_wait_ring(ring, cnt+1);
277 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
278}
279
280static inline u32 PM4_PARITY(u32 val)
281{
282 return (0x9669 >> (0xF & (val ^
283 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
284 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
285 (val >> 28)))) & 1;
286}
287
288
289#define TYPE4_MAX_PAYLOAD 127
290
291#define PKT4(_reg, _cnt) \
292 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
293 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
294
295static inline void
296OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
297{
298 adreno_wait_ring(ring, cnt + 1);
299 OUT_RING(ring, PKT4(regindx, cnt));
300}
301
302static inline void
303OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
304{
305 adreno_wait_ring(ring, cnt + 1);
306 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
307 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
308}
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315static inline bool adreno_reg_check(struct adreno_gpu *gpu,
316 enum adreno_regs offset_name)
317{
318 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
319 !gpu->reg_offsets[offset_name]) {
320 BUG();
321 }
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328
329 if (gpu->reg_offsets[offset_name] == REG_SKIP)
330 return false;
331
332 return true;
333}
334
335static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
336 enum adreno_regs offset_name)
337{
338 u32 reg = gpu->reg_offsets[offset_name];
339 u32 val = 0;
340 if(adreno_reg_check(gpu,offset_name))
341 val = gpu_read(&gpu->base, reg - 1);
342 return val;
343}
344
345static inline void adreno_gpu_write(struct adreno_gpu *gpu,
346 enum adreno_regs offset_name, u32 data)
347{
348 u32 reg = gpu->reg_offsets[offset_name];
349 if(adreno_reg_check(gpu, offset_name))
350 gpu_write(&gpu->base, reg - 1, data);
351}
352
353struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
354struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
355struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
356struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
357struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
358
359static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
360 enum adreno_regs lo, enum adreno_regs hi, u64 data)
361{
362 adreno_gpu_write(gpu, lo, lower_32_bits(data));
363 adreno_gpu_write(gpu, hi, upper_32_bits(data));
364}
365
366static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
367{
368 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
369}
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382#define ADRENO_PROTECT_RW(_reg, _len) \
383 ((1 << 30) | (1 << 29) | \
384 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
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391#define ADRENO_PROTECT_RDONLY(_reg, _len) \
392 ((1 << 29) \
393 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
394
395
396#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
397 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
398 interval, timeout)
399
400#endif
401