1
2
3
4
5#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6#include "dpu_encoder_phys.h"
7#include "dpu_hw_interrupts.h"
8#include "dpu_core_irq.h"
9#include "dpu_formats.h"
10#include "dpu_trace.h"
11
12#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
17
18#define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
23
24#define to_dpu_encoder_phys_vid(x) \
25 container_of(x, struct dpu_encoder_phys_vid, base)
26
27static bool dpu_encoder_phys_vid_is_master(
28 struct dpu_encoder_phys *phys_enc)
29{
30 bool ret = false;
31
32 if (phys_enc->split_role != ENC_ROLE_SLAVE)
33 ret = true;
34
35 return ret;
36}
37
38static void drm_mode_to_intf_timing_params(
39 const struct dpu_encoder_phys *phys_enc,
40 const struct drm_display_mode *mode,
41 struct intf_timing_params *timing)
42{
43 memset(timing, 0, sizeof(*timing));
44
45 if ((mode->htotal < mode->hsync_end)
46 || (mode->hsync_start < mode->hdisplay)
47 || (mode->vtotal < mode->vsync_end)
48 || (mode->vsync_start < mode->vdisplay)
49 || (mode->hsync_end < mode->hsync_start)
50 || (mode->vsync_end < mode->vsync_start)) {
51 DPU_ERROR(
52 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
53 mode->hsync_start, mode->hsync_end,
54 mode->htotal, mode->hdisplay);
55 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
56 mode->vsync_start, mode->vsync_end,
57 mode->vtotal, mode->vdisplay);
58 return;
59 }
60
61
62
63
64
65
66
67
68
69
70 timing->width = mode->hdisplay;
71 timing->height = mode->vdisplay;
72 timing->xres = timing->width;
73 timing->yres = timing->height;
74 timing->h_back_porch = mode->htotal - mode->hsync_end;
75 timing->h_front_porch = mode->hsync_start - mode->hdisplay;
76 timing->v_back_porch = mode->vtotal - mode->vsync_end;
77 timing->v_front_porch = mode->vsync_start - mode->vdisplay;
78 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
79 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
80 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
81 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
82 timing->border_clr = 0;
83 timing->underflow_clr = 0xff;
84 timing->hsync_skew = mode->hskew;
85
86
87 if (phys_enc->hw_intf->cap->type == INTF_DSI) {
88 timing->hsync_polarity = 0;
89 timing->vsync_polarity = 0;
90 }
91
92
93
94
95
96
97
98
99
100
101
102
103}
104
105static u32 get_horizontal_total(const struct intf_timing_params *timing)
106{
107 u32 active = timing->xres;
108 u32 inactive =
109 timing->h_back_porch + timing->h_front_porch +
110 timing->hsync_pulse_width;
111 return active + inactive;
112}
113
114static u32 get_vertical_total(const struct intf_timing_params *timing)
115{
116 u32 active = timing->yres;
117 u32 inactive =
118 timing->v_back_porch + timing->v_front_porch +
119 timing->vsync_pulse_width;
120 return active + inactive;
121}
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137static u32 programmable_fetch_get_num_lines(
138 struct dpu_encoder_phys *phys_enc,
139 const struct intf_timing_params *timing)
140{
141 u32 worst_case_needed_lines =
142 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
143 u32 start_of_frame_lines =
144 timing->v_back_porch + timing->vsync_pulse_width;
145 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
146 u32 actual_vfp_lines = 0;
147
148
149 if (start_of_frame_lines >= worst_case_needed_lines) {
150 DPU_DEBUG_VIDENC(phys_enc,
151 "prog fetch is not needed, large vbp+vsw\n");
152 actual_vfp_lines = 0;
153 } else if (timing->v_front_porch < needed_vfp_lines) {
154
155 pr_warn_once
156 ("low vbp+vfp may lead to perf issues in some cases\n");
157 DPU_DEBUG_VIDENC(phys_enc,
158 "less vfp than fetch req, using entire vfp\n");
159 actual_vfp_lines = timing->v_front_porch;
160 } else {
161 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
162 actual_vfp_lines = needed_vfp_lines;
163 }
164
165 DPU_DEBUG_VIDENC(phys_enc,
166 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
167 timing->v_front_porch, timing->v_back_porch,
168 timing->vsync_pulse_width);
169 DPU_DEBUG_VIDENC(phys_enc,
170 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
171 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
172
173 return actual_vfp_lines;
174}
175
176
177
178
179
180
181
182
183
184
185
186static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
187 const struct intf_timing_params *timing)
188{
189 struct intf_prog_fetch f = { 0 };
190 u32 vfp_fetch_lines = 0;
191 u32 horiz_total = 0;
192 u32 vert_total = 0;
193 u32 vfp_fetch_start_vsync_counter = 0;
194 unsigned long lock_flags;
195
196 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
197 return;
198
199 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
200 if (vfp_fetch_lines) {
201 vert_total = get_vertical_total(timing);
202 horiz_total = get_horizontal_total(timing);
203 vfp_fetch_start_vsync_counter =
204 (vert_total - vfp_fetch_lines) * horiz_total + 1;
205 f.enable = 1;
206 f.fetch_start = vfp_fetch_start_vsync_counter;
207 }
208
209 DPU_DEBUG_VIDENC(phys_enc,
210 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
211 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
212
213 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
214 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
215 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
216}
217
218static bool dpu_encoder_phys_vid_mode_fixup(
219 struct dpu_encoder_phys *phys_enc,
220 const struct drm_display_mode *mode,
221 struct drm_display_mode *adj_mode)
222{
223 if (phys_enc)
224 DPU_DEBUG_VIDENC(phys_enc, "\n");
225
226
227
228
229 return true;
230}
231
232static void dpu_encoder_phys_vid_setup_timing_engine(
233 struct dpu_encoder_phys *phys_enc)
234{
235 struct drm_display_mode mode;
236 struct intf_timing_params timing_params = { 0 };
237 const struct dpu_format *fmt = NULL;
238 u32 fmt_fourcc = DRM_FORMAT_RGB888;
239 unsigned long lock_flags;
240 struct dpu_hw_intf_cfg intf_cfg = { 0 };
241
242 if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
243 DPU_ERROR("invalid encoder %d\n", phys_enc != 0);
244 return;
245 }
246
247 mode = phys_enc->cached_mode;
248 if (!phys_enc->hw_intf->ops.setup_timing_gen) {
249 DPU_ERROR("timing engine setup is not supported\n");
250 return;
251 }
252
253 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
254 drm_mode_debug_printmodeline(&mode);
255
256 if (phys_enc->split_role != ENC_ROLE_SOLO) {
257 mode.hdisplay >>= 1;
258 mode.htotal >>= 1;
259 mode.hsync_start >>= 1;
260 mode.hsync_end >>= 1;
261
262 DPU_DEBUG_VIDENC(phys_enc,
263 "split_role %d, halve horizontal %d %d %d %d\n",
264 phys_enc->split_role,
265 mode.hdisplay, mode.htotal,
266 mode.hsync_start, mode.hsync_end);
267 }
268
269 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
270
271 fmt = dpu_get_dpu_format(fmt_fourcc);
272 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
273
274 intf_cfg.intf = phys_enc->hw_intf->idx;
275 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
276 intf_cfg.stream_sel = 0;
277 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
278
279 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
280 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
281 &timing_params, fmt);
282 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
283 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
284
285 programmable_fetch_config(phys_enc, &timing_params);
286}
287
288static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
289{
290 struct dpu_encoder_phys *phys_enc = arg;
291 struct dpu_hw_ctl *hw_ctl;
292 unsigned long lock_flags;
293 u32 flush_register = 0;
294 int new_cnt = -1, old_cnt = -1;
295
296 if (!phys_enc)
297 return;
298
299 hw_ctl = phys_enc->hw_ctl;
300 if (!hw_ctl)
301 return;
302
303 DPU_ATRACE_BEGIN("vblank_irq");
304
305 if (phys_enc->parent_ops->handle_vblank_virt)
306 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
307 phys_enc);
308
309 old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
310
311
312
313
314
315
316 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
317 if (hw_ctl && hw_ctl->ops.get_flush_register)
318 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
319
320 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
321 new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
322 -1, 0);
323 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
324
325
326 wake_up_all(&phys_enc->pending_kickoff_wq);
327 DPU_ATRACE_END("vblank_irq");
328}
329
330static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
331{
332 struct dpu_encoder_phys *phys_enc = arg;
333
334 if (!phys_enc)
335 return;
336
337 if (phys_enc->parent_ops->handle_underrun_virt)
338 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
339 phys_enc);
340}
341
342static bool dpu_encoder_phys_vid_needs_single_flush(
343 struct dpu_encoder_phys *phys_enc)
344{
345 return phys_enc->split_role != ENC_ROLE_SOLO;
346}
347
348static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
349 struct dpu_encoder_phys *phys_enc)
350{
351 struct dpu_encoder_irq *irq;
352
353
354
355
356
357
358
359 irq = &phys_enc->irq[INTR_IDX_VSYNC];
360 if (irq->irq_idx < 0)
361 irq->hw_idx = phys_enc->intf_idx;
362
363 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
364 if (irq->irq_idx < 0)
365 irq->hw_idx = phys_enc->intf_idx;
366}
367
368static void dpu_encoder_phys_vid_mode_set(
369 struct dpu_encoder_phys *phys_enc,
370 struct drm_display_mode *mode,
371 struct drm_display_mode *adj_mode)
372{
373 if (!phys_enc || !phys_enc->dpu_kms) {
374 DPU_ERROR("invalid encoder/kms\n");
375 return;
376 }
377
378 if (adj_mode) {
379 phys_enc->cached_mode = *adj_mode;
380 drm_mode_debug_printmodeline(adj_mode);
381 DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
382 }
383
384 _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
385}
386
387static int dpu_encoder_phys_vid_control_vblank_irq(
388 struct dpu_encoder_phys *phys_enc,
389 bool enable)
390{
391 int ret = 0;
392 int refcount;
393
394 if (!phys_enc) {
395 DPU_ERROR("invalid encoder\n");
396 return -EINVAL;
397 }
398
399 refcount = atomic_read(&phys_enc->vblank_refcount);
400
401
402 if (!dpu_encoder_phys_vid_is_master(phys_enc))
403 goto end;
404
405
406 if (!enable && refcount == 0) {
407 ret = -EINVAL;
408 goto end;
409 }
410
411 DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
412 atomic_read(&phys_enc->vblank_refcount));
413
414 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
415 ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
416 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
417 ret = dpu_encoder_helper_unregister_irq(phys_enc,
418 INTR_IDX_VSYNC);
419
420end:
421 if (ret) {
422 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
423 DRMID(phys_enc->parent),
424 phys_enc->hw_intf->idx - INTF_0, ret, enable,
425 refcount);
426 }
427 return ret;
428}
429
430static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
431{
432 struct dpu_hw_ctl *ctl;
433 u32 flush_mask = 0;
434
435 ctl = phys_enc->hw_ctl;
436
437 DPU_DEBUG_VIDENC(phys_enc, "\n");
438
439 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
440 return;
441
442 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
443
444 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
445
446
447
448
449
450
451 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
452 !dpu_encoder_phys_vid_is_master(phys_enc))
453 goto skip_flush;
454
455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
456 ctl->ops.update_pending_flush(ctl, flush_mask);
457
458skip_flush:
459 DPU_DEBUG_VIDENC(phys_enc,
460 "update pending flush ctl %d flush_mask %x\n",
461 ctl->idx - CTL_0, flush_mask);
462
463
464 if (phys_enc->enable_state == DPU_ENC_DISABLED)
465 phys_enc->enable_state = DPU_ENC_ENABLING;
466}
467
468static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
469{
470 if (!phys_enc) {
471 DPU_ERROR("invalid encoder\n");
472 return;
473 }
474
475 DPU_DEBUG_VIDENC(phys_enc, "\n");
476 kfree(phys_enc);
477}
478
479static void dpu_encoder_phys_vid_get_hw_resources(
480 struct dpu_encoder_phys *phys_enc,
481 struct dpu_encoder_hw_resources *hw_res)
482{
483 hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
484}
485
486static int _dpu_encoder_phys_vid_wait_for_vblank(
487 struct dpu_encoder_phys *phys_enc, bool notify)
488{
489 struct dpu_encoder_wait_info wait_info;
490 int ret;
491
492 if (!phys_enc) {
493 pr_err("invalid encoder\n");
494 return -EINVAL;
495 }
496
497 wait_info.wq = &phys_enc->pending_kickoff_wq;
498 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
499 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
500
501 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
502 if (notify && phys_enc->parent_ops->handle_frame_done)
503 phys_enc->parent_ops->handle_frame_done(
504 phys_enc->parent, phys_enc,
505 DPU_ENCODER_FRAME_EVENT_DONE);
506 return 0;
507 }
508
509
510 ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
511 &wait_info);
512
513 if (ret == -ETIMEDOUT) {
514 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
515 } else if (!ret && notify && phys_enc->parent_ops->handle_frame_done)
516 phys_enc->parent_ops->handle_frame_done(
517 phys_enc->parent, phys_enc,
518 DPU_ENCODER_FRAME_EVENT_DONE);
519
520 return ret;
521}
522
523static int dpu_encoder_phys_vid_wait_for_vblank(
524 struct dpu_encoder_phys *phys_enc)
525{
526 return _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, true);
527}
528
529static void dpu_encoder_phys_vid_prepare_for_kickoff(
530 struct dpu_encoder_phys *phys_enc)
531{
532 struct dpu_hw_ctl *ctl;
533 int rc;
534
535 if (!phys_enc) {
536 DPU_ERROR("invalid encoder/parameters\n");
537 return;
538 }
539
540 ctl = phys_enc->hw_ctl;
541 if (!ctl || !ctl->ops.wait_reset_status)
542 return;
543
544
545
546
547
548 rc = ctl->ops.wait_reset_status(ctl);
549 if (rc) {
550 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
551 ctl->idx, rc);
552 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
553 }
554}
555
556static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
557{
558 struct msm_drm_private *priv;
559 unsigned long lock_flags;
560 int ret;
561
562 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
563 !phys_enc->parent->dev->dev_private) {
564 DPU_ERROR("invalid encoder/device\n");
565 return;
566 }
567 priv = phys_enc->parent->dev->dev_private;
568
569 if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
570 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
571 phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
572 return;
573 }
574
575 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
576 return;
577
578 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
579 DPU_ERROR("already disabled\n");
580 return;
581 }
582
583 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
584 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
585 if (dpu_encoder_phys_vid_is_master(phys_enc))
586 dpu_encoder_phys_inc_pending(phys_enc);
587 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
588
589
590
591
592
593
594
595
596
597 if (dpu_encoder_phys_vid_is_master(phys_enc)) {
598 ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
599 if (ret) {
600 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
601 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
602 DRMID(phys_enc->parent),
603 phys_enc->hw_intf->idx - INTF_0, ret);
604 }
605 }
606
607 phys_enc->enable_state = DPU_ENC_DISABLED;
608}
609
610static void dpu_encoder_phys_vid_handle_post_kickoff(
611 struct dpu_encoder_phys *phys_enc)
612{
613 unsigned long lock_flags;
614
615 if (!phys_enc) {
616 DPU_ERROR("invalid encoder\n");
617 return;
618 }
619
620
621
622
623
624 if (phys_enc->enable_state == DPU_ENC_ENABLING) {
625 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
626 phys_enc->hw_intf->idx - INTF_0);
627 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
628 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
629 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
630 phys_enc->enable_state = DPU_ENC_ENABLED;
631 }
632}
633
634static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
635 bool enable)
636{
637 int ret;
638
639 if (!phys_enc)
640 return;
641
642 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
643 phys_enc->hw_intf->idx - INTF_0,
644 enable,
645 atomic_read(&phys_enc->vblank_refcount));
646
647 if (enable) {
648 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
649 if (ret)
650 return;
651
652 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
653 } else {
654 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
655 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
656 }
657}
658
659static int dpu_encoder_phys_vid_get_line_count(
660 struct dpu_encoder_phys *phys_enc)
661{
662 if (!phys_enc)
663 return -EINVAL;
664
665 if (!dpu_encoder_phys_vid_is_master(phys_enc))
666 return -EINVAL;
667
668 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
669 return -EINVAL;
670
671 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
672}
673
674static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
675{
676 ops->is_master = dpu_encoder_phys_vid_is_master;
677 ops->mode_set = dpu_encoder_phys_vid_mode_set;
678 ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup;
679 ops->enable = dpu_encoder_phys_vid_enable;
680 ops->disable = dpu_encoder_phys_vid_disable;
681 ops->destroy = dpu_encoder_phys_vid_destroy;
682 ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;
683 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
684 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_vblank;
685 ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
686 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
687 ops->irq_control = dpu_encoder_phys_vid_irq_control;
688 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
689 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
690 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
691 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
692}
693
694struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
695 struct dpu_enc_phys_init_params *p)
696{
697 struct dpu_encoder_phys *phys_enc = NULL;
698 struct dpu_encoder_irq *irq;
699 int i, ret = 0;
700
701 if (!p) {
702 ret = -EINVAL;
703 goto fail;
704 }
705
706 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
707 if (!phys_enc) {
708 ret = -ENOMEM;
709 goto fail;
710 }
711
712 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
713 phys_enc->intf_idx = p->intf_idx;
714
715 DPU_DEBUG_VIDENC(phys_enc, "\n");
716
717 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
718 phys_enc->parent = p->parent;
719 phys_enc->parent_ops = p->parent_ops;
720 phys_enc->dpu_kms = p->dpu_kms;
721 phys_enc->split_role = p->split_role;
722 phys_enc->intf_mode = INTF_MODE_VIDEO;
723 phys_enc->enc_spinlock = p->enc_spinlock;
724 for (i = 0; i < INTR_IDX_MAX; i++) {
725 irq = &phys_enc->irq[i];
726 INIT_LIST_HEAD(&irq->cb.list);
727 irq->irq_idx = -EINVAL;
728 irq->hw_idx = -EINVAL;
729 irq->cb.arg = phys_enc;
730 }
731
732 irq = &phys_enc->irq[INTR_IDX_VSYNC];
733 irq->name = "vsync_irq";
734 irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
735 irq->intr_idx = INTR_IDX_VSYNC;
736 irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
737
738 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
739 irq->name = "underrun";
740 irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
741 irq->intr_idx = INTR_IDX_UNDERRUN;
742 irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
743
744 atomic_set(&phys_enc->vblank_refcount, 0);
745 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
746 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
747 phys_enc->enable_state = DPU_ENC_DISABLED;
748
749 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
750
751 return phys_enc;
752
753fail:
754 DPU_ERROR("failed to create encoder\n");
755 if (phys_enc)
756 dpu_encoder_phys_vid_destroy(phys_enc);
757
758 return ERR_PTR(ret);
759}
760