1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5#ifndef _DPU_HW_CATALOG_H 6#define _DPU_HW_CATALOG_H 7 8#include <linux/kernel.h> 9#include <linux/bug.h> 10#include <linux/bitmap.h> 11#include <linux/err.h> 12#include <drm/drmP.h> 13 14/** 15 * Max hardware block count: For ex: max 12 SSPP pipes or 16 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 17 * based on current design 18 */ 19#define MAX_BLOCKS 12 20 21#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 22 ((MINOR & 0xFFF) << 16) |\ 23 (STEP & 0xFFFF)) 24 25#define DPU_HW_MAJOR(rev) ((rev) >> 28) 26#define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 27#define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 28#define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 29 30#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 31 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 32 33#define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 34#define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 35#define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 36#define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 37#define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 38#define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 39#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 40#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 41#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */ 42 43 44#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 45#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 46#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 47#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 48#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 49 50 51#define DPU_HW_BLK_NAME_LEN 16 52 53#define MAX_IMG_WIDTH 0x3fff 54#define MAX_IMG_HEIGHT 0x3fff 55 56#define CRTC_DUAL_MIXERS 2 57 58#define MAX_XIN_COUNT 16 59 60/** 61 * Supported UBWC feature versions 62 */ 63enum { 64 DPU_HW_UBWC_VER_10 = 0x100, 65 DPU_HW_UBWC_VER_20 = 0x200, 66 DPU_HW_UBWC_VER_30 = 0x300, 67}; 68 69#define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20) 70 71/** 72 * MDP TOP BLOCK features 73 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 74 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 75 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 76 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 77 * compression initial revision 78 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 79 * @DPU_MDP_MAX Maximum value 80 81 */ 82enum { 83 DPU_MDP_PANIC_PER_PIPE = 0x1, 84 DPU_MDP_10BIT_SUPPORT, 85 DPU_MDP_BWC, 86 DPU_MDP_UBWC_1_0, 87 DPU_MDP_UBWC_1_5, 88 DPU_MDP_MAX 89}; 90 91/** 92 * SSPP sub-blocks/features 93 * @DPU_SSPP_SRC Src and fetch part of the pipes, 94 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 95 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 96 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 97 * @DPU_SSPP_CSC, Support of Color space converion 98 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 99 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 100 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 101 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 102 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 103 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 104 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 105 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 106 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 107 * @DPU_SSPP_CDP Supports client driven prefetch 108 * @DPU_SSPP_MAX maximum value 109 */ 110enum { 111 DPU_SSPP_SRC = 0x1, 112 DPU_SSPP_SCALER_QSEED2, 113 DPU_SSPP_SCALER_QSEED3, 114 DPU_SSPP_SCALER_RGB, 115 DPU_SSPP_CSC, 116 DPU_SSPP_CSC_10BIT, 117 DPU_SSPP_CURSOR, 118 DPU_SSPP_QOS, 119 DPU_SSPP_QOS_8LVL, 120 DPU_SSPP_EXCL_RECT, 121 DPU_SSPP_SMART_DMA_V1, 122 DPU_SSPP_SMART_DMA_V2, 123 DPU_SSPP_TS_PREFILL, 124 DPU_SSPP_TS_PREFILL_REC1, 125 DPU_SSPP_CDP, 126 DPU_SSPP_MAX 127}; 128 129/* 130 * MIXER sub-blocks/features 131 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 132 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 133 * @DPU_MIXER_GC Gamma correction block 134 * @DPU_DIM_LAYER Layer mixer supports dim layer 135 * @DPU_MIXER_MAX maximum value 136 */ 137enum { 138 DPU_MIXER_LAYER = 0x1, 139 DPU_MIXER_SOURCESPLIT, 140 DPU_MIXER_GC, 141 DPU_DIM_LAYER, 142 DPU_MIXER_MAX 143}; 144 145/** 146 * PINGPONG sub-blocks 147 * @DPU_PINGPONG_TE Tear check block 148 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 149 * @DPU_PINGPONG_SPLIT PP block supports split fifo 150 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 151 * @DPU_PINGPONG_DITHER, Dither blocks 152 * @DPU_PINGPONG_MAX 153 */ 154enum { 155 DPU_PINGPONG_TE = 0x1, 156 DPU_PINGPONG_TE2, 157 DPU_PINGPONG_SPLIT, 158 DPU_PINGPONG_SLAVE, 159 DPU_PINGPONG_DITHER, 160 DPU_PINGPONG_MAX 161}; 162 163/** 164 * CTL sub-blocks 165 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display 166 * @DPU_CTL_MAX 167 */ 168enum { 169 DPU_CTL_SPLIT_DISPLAY = 0x1, 170 DPU_CTL_MAX 171}; 172 173/** 174 * VBIF sub-blocks and features 175 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 176 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 177 * @DPU_VBIF_MAX maximum value 178 */ 179enum { 180 DPU_VBIF_QOS_OTLIM = 0x1, 181 DPU_VBIF_QOS_REMAP, 182 DPU_VBIF_MAX 183}; 184 185/** 186 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 187 * @name: string name for debug purposes 188 * @id: enum identifying this block 189 * @base: register base offset to mdss 190 * @len: length of hardware block 191 * @features bit mask identifying sub-blocks/features 192 */ 193#define DPU_HW_BLK_INFO \ 194 char name[DPU_HW_BLK_NAME_LEN]; \ 195 u32 id; \ 196 u32 base; \ 197 u32 len; \ 198 unsigned long features 199 200/** 201 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 202 * @name: string name for debug purposes 203 * @id: enum identifying this sub-block 204 * @base: offset of this sub-block relative to the block 205 * offset 206 * @len register block length of this sub-block 207 */ 208#define DPU_HW_SUBBLK_INFO \ 209 char name[DPU_HW_BLK_NAME_LEN]; \ 210 u32 id; \ 211 u32 base; \ 212 u32 len 213 214/** 215 * struct dpu_src_blk: SSPP part of the source pipes 216 * @info: HW register and features supported by this sub-blk 217 */ 218struct dpu_src_blk { 219 DPU_HW_SUBBLK_INFO; 220}; 221 222/** 223 * struct dpu_scaler_blk: Scaler information 224 * @info: HW register and features supported by this sub-blk 225 * @version: qseed block revision 226 */ 227struct dpu_scaler_blk { 228 DPU_HW_SUBBLK_INFO; 229 u32 version; 230}; 231 232struct dpu_csc_blk { 233 DPU_HW_SUBBLK_INFO; 234}; 235 236/** 237 * struct dpu_pp_blk : Pixel processing sub-blk information 238 * @info: HW register and features supported by this sub-blk 239 * @version: HW Algorithm version 240 */ 241struct dpu_pp_blk { 242 DPU_HW_SUBBLK_INFO; 243 u32 version; 244}; 245 246/** 247 * enum dpu_qos_lut_usage - define QoS LUT use cases 248 */ 249enum dpu_qos_lut_usage { 250 DPU_QOS_LUT_USAGE_LINEAR, 251 DPU_QOS_LUT_USAGE_MACROTILE, 252 DPU_QOS_LUT_USAGE_NRT, 253 DPU_QOS_LUT_USAGE_MAX, 254}; 255 256/** 257 * struct dpu_qos_lut_entry - define QoS LUT table entry 258 * @fl: fill level, or zero on last entry to indicate default lut 259 * @lut: lut to use if equal to or less than fill level 260 */ 261struct dpu_qos_lut_entry { 262 u32 fl; 263 u64 lut; 264}; 265 266/** 267 * struct dpu_qos_lut_tbl - define QoS LUT table 268 * @nentry: number of entry in this table 269 * @entries: Pointer to table entries 270 */ 271struct dpu_qos_lut_tbl { 272 u32 nentry; 273 struct dpu_qos_lut_entry *entries; 274}; 275 276/** 277 * struct dpu_caps - define DPU capabilities 278 * @max_mixer_width max layer mixer line width support. 279 * @max_mixer_blendstages max layer mixer blend stages or 280 * supported z order 281 * @qseed_type qseed2 or qseed3 support. 282 * @smart_dma_rev Supported version of SmartDMA feature. 283 * @ubwc_version UBWC feature version (0x0 for not supported) 284 * @has_src_split source split feature status 285 * @has_dim_layer dim layer feature status 286 * @has_idle_pc indicate if idle power collapse feature is supported 287 */ 288struct dpu_caps { 289 u32 max_mixer_width; 290 u32 max_mixer_blendstages; 291 u32 qseed_type; 292 u32 smart_dma_rev; 293 u32 ubwc_version; 294 bool has_src_split; 295 bool has_dim_layer; 296 bool has_idle_pc; 297}; 298 299/** 300 * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration 301 * @maxwidth: max pixelwidth supported by this pipe 302 * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes 303 * @maxhdeciexp: max horizontal decimation supported by this pipe 304 * (max is 2^value) 305 * @maxvdeciexp: max vertical decimation supported by this pipe 306 * (max is 2^value) 307 */ 308struct dpu_sspp_blks_common { 309 u32 maxlinewidth; 310 u32 pixel_ram_size; 311 u32 maxhdeciexp; 312 u32 maxvdeciexp; 313}; 314 315/** 316 * struct dpu_sspp_sub_blks : SSPP sub-blocks 317 * common: Pointer to common configurations shared by sub blocks 318 * @creq_vblank: creq priority during vertical blanking 319 * @danger_vblank: danger priority during vertical blanking 320 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 321 * @maxupscale: maxupscale ratio supported 322 * @smart_dma_priority: hw priority of rect1 of multirect pipe 323 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 324 * @src_blk: 325 * @scaler_blk: 326 * @csc_blk: 327 * @hsic: 328 * @memcolor: 329 * @pcc_blk: 330 * @igc_blk: 331 * @format_list: Pointer to list of supported formats 332 * @num_formats: Number of supported formats 333 * @virt_format_list: Pointer to list of supported formats for virtual planes 334 * @virt_num_formats: Number of supported formats for virtual planes 335 */ 336struct dpu_sspp_sub_blks { 337 const struct dpu_sspp_blks_common *common; 338 u32 creq_vblank; 339 u32 danger_vblank; 340 u32 maxdwnscale; 341 u32 maxupscale; 342 u32 smart_dma_priority; 343 u32 max_per_pipe_bw; 344 struct dpu_src_blk src_blk; 345 struct dpu_scaler_blk scaler_blk; 346 struct dpu_pp_blk csc_blk; 347 struct dpu_pp_blk hsic_blk; 348 struct dpu_pp_blk memcolor_blk; 349 struct dpu_pp_blk pcc_blk; 350 struct dpu_pp_blk igc_blk; 351 352 const u32 *format_list; 353 u32 num_formats; 354 const u32 *virt_format_list; 355 u32 virt_num_formats; 356}; 357 358/** 359 * struct dpu_lm_sub_blks: information of mixer block 360 * @maxwidth: Max pixel width supported by this mixer 361 * @maxblendstages: Max number of blend-stages supported 362 * @blendstage_base: Blend-stage register base offset 363 * @gc: gamma correction block 364 */ 365struct dpu_lm_sub_blks { 366 u32 maxwidth; 367 u32 maxblendstages; 368 u32 blendstage_base[MAX_BLOCKS]; 369 struct dpu_pp_blk gc; 370}; 371 372struct dpu_pingpong_sub_blks { 373 struct dpu_pp_blk te; 374 struct dpu_pp_blk te2; 375 struct dpu_pp_blk dither; 376}; 377 378/** 379 * dpu_clk_ctrl_type - Defines top level clock control signals 380 */ 381enum dpu_clk_ctrl_type { 382 DPU_CLK_CTRL_NONE, 383 DPU_CLK_CTRL_VIG0, 384 DPU_CLK_CTRL_VIG1, 385 DPU_CLK_CTRL_VIG2, 386 DPU_CLK_CTRL_VIG3, 387 DPU_CLK_CTRL_VIG4, 388 DPU_CLK_CTRL_RGB0, 389 DPU_CLK_CTRL_RGB1, 390 DPU_CLK_CTRL_RGB2, 391 DPU_CLK_CTRL_RGB3, 392 DPU_CLK_CTRL_DMA0, 393 DPU_CLK_CTRL_DMA1, 394 DPU_CLK_CTRL_CURSOR0, 395 DPU_CLK_CTRL_CURSOR1, 396 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 397 DPU_CLK_CTRL_MAX, 398}; 399 400/* struct dpu_clk_ctrl_reg : Clock control register 401 * @reg_off: register offset 402 * @bit_off: bit offset 403 */ 404struct dpu_clk_ctrl_reg { 405 u32 reg_off; 406 u32 bit_off; 407}; 408 409/* struct dpu_mdp_cfg : MDP TOP-BLK instance info 410 * @id: index identifying this block 411 * @base: register base offset to mdss 412 * @features bit mask identifying sub-blocks/features 413 * @highest_bank_bit: UBWC parameter 414 * @ubwc_static: ubwc static configuration 415 * @ubwc_swizzle: ubwc default swizzle setting 416 * @clk_ctrls clock control register definition 417 */ 418struct dpu_mdp_cfg { 419 DPU_HW_BLK_INFO; 420 u32 highest_bank_bit; 421 u32 ubwc_static; 422 u32 ubwc_swizzle; 423 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 424}; 425 426/* struct dpu_mdp_cfg : MDP TOP-BLK instance info 427 * @id: index identifying this block 428 * @base: register base offset to mdss 429 * @features bit mask identifying sub-blocks/features 430 */ 431struct dpu_ctl_cfg { 432 DPU_HW_BLK_INFO; 433}; 434 435/** 436 * struct dpu_sspp_cfg - information of source pipes 437 * @id: index identifying this block 438 * @base register offset of this block 439 * @features bit mask identifying sub-blocks/features 440 * @sblk: SSPP sub-blocks information 441 * @xin_id: bus client identifier 442 * @clk_ctrl clock control identifier 443 * @type sspp type identifier 444 */ 445struct dpu_sspp_cfg { 446 DPU_HW_BLK_INFO; 447 const struct dpu_sspp_sub_blks *sblk; 448 u32 xin_id; 449 enum dpu_clk_ctrl_type clk_ctrl; 450 u32 type; 451}; 452 453/** 454 * struct dpu_lm_cfg - information of layer mixer blocks 455 * @id: index identifying this block 456 * @base register offset of this block 457 * @features bit mask identifying sub-blocks/features 458 * @sblk: LM Sub-blocks information 459 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 460 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 461 */ 462struct dpu_lm_cfg { 463 DPU_HW_BLK_INFO; 464 const struct dpu_lm_sub_blks *sblk; 465 u32 pingpong; 466 unsigned long lm_pair_mask; 467}; 468 469/** 470 * struct dpu_pingpong_cfg - information of PING-PONG blocks 471 * @id enum identifying this block 472 * @base register offset of this block 473 * @features bit mask identifying sub-blocks/features 474 * @sblk sub-blocks information 475 */ 476struct dpu_pingpong_cfg { 477 DPU_HW_BLK_INFO; 478 const struct dpu_pingpong_sub_blks *sblk; 479}; 480 481/** 482 * struct dpu_intf_cfg - information of timing engine blocks 483 * @id enum identifying this block 484 * @base register offset of this block 485 * @features bit mask identifying sub-blocks/features 486 * @type: Interface type(DSI, DP, HDMI) 487 * @controller_id: Controller Instance ID in case of multiple of intf type 488 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 489 */ 490struct dpu_intf_cfg { 491 DPU_HW_BLK_INFO; 492 u32 type; /* interface type*/ 493 u32 controller_id; 494 u32 prog_fetch_lines_worst_case; 495}; 496 497/** 498 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 499 * @pps pixel per seconds 500 * @ot_limit OT limit to use up to specified pixel per second 501 */ 502struct dpu_vbif_dynamic_ot_cfg { 503 u64 pps; 504 u32 ot_limit; 505}; 506 507/** 508 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 509 * @count length of cfg 510 * @cfg pointer to array of configuration settings with 511 * ascending requirements 512 */ 513struct dpu_vbif_dynamic_ot_tbl { 514 u32 count; 515 struct dpu_vbif_dynamic_ot_cfg *cfg; 516}; 517 518/** 519 * struct dpu_vbif_qos_tbl - QoS priority table 520 * @npriority_lvl num of priority level 521 * @priority_lvl pointer to array of priority level in ascending order 522 */ 523struct dpu_vbif_qos_tbl { 524 u32 npriority_lvl; 525 u32 *priority_lvl; 526}; 527 528/** 529 * struct dpu_vbif_cfg - information of VBIF blocks 530 * @id enum identifying this block 531 * @base register offset of this block 532 * @features bit mask identifying sub-blocks/features 533 * @ot_rd_limit default OT read limit 534 * @ot_wr_limit default OT write limit 535 * @xin_halt_timeout maximum time (in usec) for xin to halt 536 * @dynamic_ot_rd_tbl dynamic OT read configuration table 537 * @dynamic_ot_wr_tbl dynamic OT write configuration table 538 * @qos_rt_tbl real-time QoS priority table 539 * @qos_nrt_tbl non-real-time QoS priority table 540 * @memtype_count number of defined memtypes 541 * @memtype array of xin memtype definitions 542 */ 543struct dpu_vbif_cfg { 544 DPU_HW_BLK_INFO; 545 u32 default_ot_rd_limit; 546 u32 default_ot_wr_limit; 547 u32 xin_halt_timeout; 548 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 549 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 550 struct dpu_vbif_qos_tbl qos_rt_tbl; 551 struct dpu_vbif_qos_tbl qos_nrt_tbl; 552 u32 memtype_count; 553 u32 memtype[MAX_XIN_COUNT]; 554}; 555/** 556 * struct dpu_reg_dma_cfg - information of lut dma blocks 557 * @id enum identifying this block 558 * @base register offset of this block 559 * @features bit mask identifying sub-blocks/features 560 * @version version of lutdma hw block 561 * @trigger_sel_off offset to trigger select registers of lutdma 562 */ 563struct dpu_reg_dma_cfg { 564 DPU_HW_BLK_INFO; 565 u32 version; 566 u32 trigger_sel_off; 567}; 568 569/** 570 * Define CDP use cases 571 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 572 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 573 */ 574enum { 575 DPU_PERF_CDP_USAGE_RT, 576 DPU_PERF_CDP_USAGE_NRT, 577 DPU_PERF_CDP_USAGE_MAX 578}; 579 580/** 581 * struct dpu_perf_cdp_cfg - define CDP use case configuration 582 * @rd_enable: true if read pipe CDP is enabled 583 * @wr_enable: true if write pipe CDP is enabled 584 */ 585struct dpu_perf_cdp_cfg { 586 bool rd_enable; 587 bool wr_enable; 588}; 589 590/** 591 * struct dpu_perf_cfg - performance control settings 592 * @max_bw_low low threshold of maximum bandwidth (kbps) 593 * @max_bw_high high threshold of maximum bandwidth (kbps) 594 * @min_core_ib minimum bandwidth for core (kbps) 595 * @min_core_ib minimum mnoc ib vote in kbps 596 * @min_llcc_ib minimum llcc ib vote in kbps 597 * @min_dram_ib minimum dram ib vote in kbps 598 * @core_ib_ff core instantaneous bandwidth fudge factor 599 * @core_clk_ff core clock fudge factor 600 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 601 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 602 * @undersized_prefill_lines undersized prefill in lines 603 * @xtra_prefill_lines extra prefill latency in lines 604 * @dest_scale_prefill_lines destination scaler latency in lines 605 * @macrotile_perfill_lines macrotile latency in lines 606 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 607 * @linear_prefill_lines linear latency in lines 608 * @downscaling_prefill_lines downscaling latency in lines 609 * @amortizable_theshold minimum y position for traffic shaping prefill 610 * @min_prefill_lines minimum pipeline latency in lines 611 * @safe_lut_tbl: LUT tables for safe signals 612 * @danger_lut_tbl: LUT tables for danger signals 613 * @qos_lut_tbl: LUT tables for QoS signals 614 * @cdp_cfg cdp use case configurations 615 */ 616struct dpu_perf_cfg { 617 u32 max_bw_low; 618 u32 max_bw_high; 619 u32 min_core_ib; 620 u32 min_llcc_ib; 621 u32 min_dram_ib; 622 const char *core_ib_ff; 623 const char *core_clk_ff; 624 const char *comp_ratio_rt; 625 const char *comp_ratio_nrt; 626 u32 undersized_prefill_lines; 627 u32 xtra_prefill_lines; 628 u32 dest_scale_prefill_lines; 629 u32 macrotile_prefill_lines; 630 u32 yuv_nv12_prefill_lines; 631 u32 linear_prefill_lines; 632 u32 downscaling_prefill_lines; 633 u32 amortizable_threshold; 634 u32 min_prefill_lines; 635 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 636 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 637 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 638 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 639}; 640 641/** 642 * struct dpu_mdss_cfg - information of MDSS HW 643 * This is the main catalog data structure representing 644 * this HW version. Contains number of instances, 645 * register offsets, capabilities of the all MDSS HW sub-blocks. 646 * 647 * @dma_formats Supported formats for dma pipe 648 * @cursor_formats Supported formats for cursor pipe 649 * @vig_formats Supported formats for vig pipe 650 */ 651struct dpu_mdss_cfg { 652 u32 hwversion; 653 654 const struct dpu_caps *caps; 655 656 u32 mdp_count; 657 struct dpu_mdp_cfg *mdp; 658 659 u32 ctl_count; 660 struct dpu_ctl_cfg *ctl; 661 662 u32 sspp_count; 663 struct dpu_sspp_cfg *sspp; 664 665 u32 mixer_count; 666 struct dpu_lm_cfg *mixer; 667 668 u32 pingpong_count; 669 struct dpu_pingpong_cfg *pingpong; 670 671 u32 intf_count; 672 struct dpu_intf_cfg *intf; 673 674 u32 vbif_count; 675 struct dpu_vbif_cfg *vbif; 676 677 u32 reg_dma_count; 678 struct dpu_reg_dma_cfg dma_cfg; 679 680 u32 ad_count; 681 682 /* Add additional block data structures here */ 683 684 struct dpu_perf_cfg perf; 685 struct dpu_format_extended *dma_formats; 686 struct dpu_format_extended *cursor_formats; 687 struct dpu_format_extended *vig_formats; 688}; 689 690struct dpu_mdss_hw_cfg_handler { 691 u32 hw_rev; 692 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); 693}; 694 695/* 696 * Access Macros 697 */ 698#define BLK_MDP(s) ((s)->mdp) 699#define BLK_CTL(s) ((s)->ctl) 700#define BLK_VIG(s) ((s)->vig) 701#define BLK_RGB(s) ((s)->rgb) 702#define BLK_DMA(s) ((s)->dma) 703#define BLK_CURSOR(s) ((s)->cursor) 704#define BLK_MIXER(s) ((s)->mixer) 705#define BLK_PINGPONG(s) ((s)->pingpong) 706#define BLK_INTF(s) ((s)->intf) 707#define BLK_AD(s) ((s)->ad) 708 709/** 710 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 711 * hardcoded target specific catalog information in config structure 712 * @hw_rev: caller needs provide the hardware revision. 713 * 714 * Return: dpu config structure 715 */ 716struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 717 718/** 719 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup 720 * @dpu_cfg: pointer returned from init function 721 */ 722void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); 723 724#endif /* _DPU_HW_CATALOG_H */ 725