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6#include "dpu_kms.h"
7#include <linux/interconnect.h>
8
9#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
10
11#define HW_INTR_STATUS 0x0010
12
13
14#define MAX_BW 6800000
15
16struct dpu_irq_controller {
17 unsigned long enabled_mask;
18 struct irq_domain *domain;
19};
20
21struct dpu_mdss {
22 struct msm_mdss base;
23 void __iomem *mmio;
24 unsigned long mmio_len;
25 u32 hwversion;
26 struct dss_module_power mp;
27 struct dpu_irq_controller irq_controller;
28 struct icc_path *path[2];
29 u32 num_paths;
30};
31
32static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
33 struct dpu_mdss *dpu_mdss)
34{
35 struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
36 struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
37
38 if (IS_ERR_OR_NULL(path0))
39 return PTR_ERR_OR_ZERO(path0);
40
41 dpu_mdss->path[0] = path0;
42 dpu_mdss->num_paths = 1;
43
44 if (!IS_ERR_OR_NULL(path1)) {
45 dpu_mdss->path[1] = path1;
46 dpu_mdss->num_paths++;
47 }
48
49 return 0;
50}
51
52static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss)
53{
54 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
55 int i;
56 u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
57
58 for (i = 0; i < dpu_mdss->num_paths; i++)
59 icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
60}
61
62static void dpu_mdss_irq(struct irq_desc *desc)
63{
64 struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
65 struct irq_chip *chip = irq_desc_get_chip(desc);
66 u32 interrupts;
67
68 chained_irq_enter(chip, desc);
69
70 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
71
72 while (interrupts) {
73 irq_hw_number_t hwirq = fls(interrupts) - 1;
74 unsigned int mapping;
75 int rc;
76
77 mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
78 hwirq);
79 if (mapping == 0) {
80 DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
81 break;
82 }
83
84 rc = generic_handle_irq(mapping);
85 if (rc < 0) {
86 DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
87 hwirq, mapping, rc);
88 break;
89 }
90
91 interrupts &= ~(1 << hwirq);
92 }
93
94 chained_irq_exit(chip, desc);
95}
96
97static void dpu_mdss_irq_mask(struct irq_data *irqd)
98{
99 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
100
101
102 smp_mb__before_atomic();
103 clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
104
105 smp_mb__after_atomic();
106}
107
108static void dpu_mdss_irq_unmask(struct irq_data *irqd)
109{
110 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
111
112
113 smp_mb__before_atomic();
114 set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
115
116 smp_mb__after_atomic();
117}
118
119static struct irq_chip dpu_mdss_irq_chip = {
120 .name = "dpu_mdss",
121 .irq_mask = dpu_mdss_irq_mask,
122 .irq_unmask = dpu_mdss_irq_unmask,
123};
124
125static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
126
127static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
128 unsigned int irq, irq_hw_number_t hwirq)
129{
130 struct dpu_mdss *dpu_mdss = domain->host_data;
131
132 irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
133 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
134 return irq_set_chip_data(irq, dpu_mdss);
135}
136
137static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
138 .map = dpu_mdss_irqdomain_map,
139 .xlate = irq_domain_xlate_onecell,
140};
141
142static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
143{
144 struct device *dev;
145 struct irq_domain *domain;
146
147 dev = dpu_mdss->base.dev->dev;
148
149 domain = irq_domain_add_linear(dev->of_node, 32,
150 &dpu_mdss_irqdomain_ops, dpu_mdss);
151 if (!domain) {
152 DPU_ERROR("failed to add irq_domain\n");
153 return -EINVAL;
154 }
155
156 dpu_mdss->irq_controller.enabled_mask = 0;
157 dpu_mdss->irq_controller.domain = domain;
158
159 return 0;
160}
161
162static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
163{
164 if (dpu_mdss->irq_controller.domain) {
165 irq_domain_remove(dpu_mdss->irq_controller.domain);
166 dpu_mdss->irq_controller.domain = NULL;
167 }
168}
169static int dpu_mdss_enable(struct msm_mdss *mdss)
170{
171 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
172 struct dss_module_power *mp = &dpu_mdss->mp;
173 int ret;
174
175 dpu_mdss_icc_request_bw(mdss);
176
177 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
178 if (ret)
179 DPU_ERROR("clock enable failed, ret:%d\n", ret);
180
181 return ret;
182}
183
184static int dpu_mdss_disable(struct msm_mdss *mdss)
185{
186 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
187 struct dss_module_power *mp = &dpu_mdss->mp;
188 int ret, i;
189
190 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
191 if (ret)
192 DPU_ERROR("clock disable failed, ret:%d\n", ret);
193
194 for (i = 0; i < dpu_mdss->num_paths; i++)
195 icc_set_bw(dpu_mdss->path[i], 0, 0);
196
197 return ret;
198}
199
200static void dpu_mdss_destroy(struct drm_device *dev)
201{
202 struct platform_device *pdev = to_platform_device(dev->dev);
203 struct msm_drm_private *priv = dev->dev_private;
204 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
205 struct dss_module_power *mp = &dpu_mdss->mp;
206 int irq;
207 int i;
208
209 pm_runtime_suspend(dev->dev);
210 pm_runtime_disable(dev->dev);
211 _dpu_mdss_irq_domain_fini(dpu_mdss);
212 irq = platform_get_irq(pdev, 0);
213 irq_set_chained_handler_and_data(irq, NULL, NULL);
214 msm_dss_put_clk(mp->clk_config, mp->num_clk);
215 devm_kfree(&pdev->dev, mp->clk_config);
216
217 for (i = 0; i < dpu_mdss->num_paths; i++)
218 icc_put(dpu_mdss->path[i]);
219
220 if (dpu_mdss->mmio)
221 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
222 dpu_mdss->mmio = NULL;
223 priv->mdss = NULL;
224}
225
226static const struct msm_mdss_funcs mdss_funcs = {
227 .enable = dpu_mdss_enable,
228 .disable = dpu_mdss_disable,
229 .destroy = dpu_mdss_destroy,
230};
231
232int dpu_mdss_init(struct drm_device *dev)
233{
234 struct platform_device *pdev = to_platform_device(dev->dev);
235 struct msm_drm_private *priv = dev->dev_private;
236 struct resource *res;
237 struct dpu_mdss *dpu_mdss;
238 struct dss_module_power *mp;
239 int ret = 0;
240 int irq;
241
242 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
243 if (!dpu_mdss)
244 return -ENOMEM;
245
246 dpu_mdss->mmio = msm_ioremap(pdev, "mdss", "mdss");
247 if (IS_ERR(dpu_mdss->mmio))
248 return PTR_ERR(dpu_mdss->mmio);
249
250 DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
251
252 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mdss");
253 if (!res) {
254 DRM_ERROR("failed to get memory resource for mdss\n");
255 return -ENOMEM;
256 }
257 dpu_mdss->mmio_len = resource_size(res);
258
259 ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
260 if (ret)
261 return ret;
262
263 mp = &dpu_mdss->mp;
264 ret = msm_dss_parse_clock(pdev, mp);
265 if (ret) {
266 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
267 goto clk_parse_err;
268 }
269
270 dpu_mdss->base.dev = dev;
271 dpu_mdss->base.funcs = &mdss_funcs;
272
273 ret = _dpu_mdss_irq_domain_add(dpu_mdss);
274 if (ret)
275 goto irq_domain_error;
276
277 irq = platform_get_irq(pdev, 0);
278 if (irq < 0)
279 goto irq_error;
280
281 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
282 dpu_mdss);
283
284 priv->mdss = &dpu_mdss->base;
285
286 pm_runtime_enable(dev->dev);
287
288 dpu_mdss_icc_request_bw(priv->mdss);
289
290 pm_runtime_get_sync(dev->dev);
291 dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
292 pm_runtime_put_sync(dev->dev);
293
294 return ret;
295
296irq_error:
297 _dpu_mdss_irq_domain_fini(dpu_mdss);
298irq_domain_error:
299 msm_dss_put_clk(mp->clk_config, mp->num_clk);
300clk_parse_err:
301 devm_kfree(&pdev->dev, mp->clk_config);
302 if (dpu_mdss->mmio)
303 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
304 dpu_mdss->mmio = NULL;
305 return ret;
306}
307
