1
2
3
4
5#if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
6#define _DPU_TRACE_H_
7
8#include <linux/stringify.h>
9#include <linux/types.h>
10#include <linux/tracepoint.h>
11
12#include <drm/drm_rect.h>
13#include "dpu_crtc.h"
14#include "dpu_encoder_phys.h"
15#include "dpu_hw_mdss.h"
16#include "dpu_hw_vbif.h"
17#include "dpu_plane.h"
18
19#undef TRACE_SYSTEM
20#define TRACE_SYSTEM dpu
21#undef TRACE_INCLUDE_FILE
22#define TRACE_INCLUDE_FILE dpu_trace
23
24TRACE_EVENT(dpu_perf_set_qos_luts,
25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
26 u32 lut, u32 lut_usage),
27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
28 TP_STRUCT__entry(
29 __field(u32, pnum)
30 __field(u32, fmt)
31 __field(bool, rt)
32 __field(u32, fl)
33 __field(u64, lut)
34 __field(u32, lut_usage)
35 ),
36 TP_fast_assign(
37 __entry->pnum = pnum;
38 __entry->fmt = fmt;
39 __entry->rt = rt;
40 __entry->fl = fl;
41 __entry->lut = lut;
42 __entry->lut_usage = lut_usage;
43 ),
44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
45 __entry->pnum, __entry->fmt,
46 __entry->rt, __entry->fl,
47 __entry->lut, __entry->lut_usage)
48);
49
50TRACE_EVENT(dpu_perf_set_danger_luts,
51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
52 u32 safe_lut),
53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
54 TP_STRUCT__entry(
55 __field(u32, pnum)
56 __field(u32, fmt)
57 __field(u32, mode)
58 __field(u32, danger_lut)
59 __field(u32, safe_lut)
60 ),
61 TP_fast_assign(
62 __entry->pnum = pnum;
63 __entry->fmt = fmt;
64 __entry->mode = mode;
65 __entry->danger_lut = danger_lut;
66 __entry->safe_lut = safe_lut;
67 ),
68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
69 __entry->pnum, __entry->fmt,
70 __entry->mode, __entry->danger_lut,
71 __entry->safe_lut)
72);
73
74TRACE_EVENT(dpu_perf_set_ot,
75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
77 TP_STRUCT__entry(
78 __field(u32, pnum)
79 __field(u32, xin_id)
80 __field(u32, rd_lim)
81 __field(u32, vbif_idx)
82 ),
83 TP_fast_assign(
84 __entry->pnum = pnum;
85 __entry->xin_id = xin_id;
86 __entry->rd_lim = rd_lim;
87 __entry->vbif_idx = vbif_idx;
88 ),
89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
90 __entry->pnum, __entry->xin_id, __entry->rd_lim,
91 __entry->vbif_idx)
92)
93
94TRACE_EVENT(dpu_cmd_release_bw,
95 TP_PROTO(u32 crtc_id),
96 TP_ARGS(crtc_id),
97 TP_STRUCT__entry(
98 __field(u32, crtc_id)
99 ),
100 TP_fast_assign(
101 __entry->crtc_id = crtc_id;
102 ),
103 TP_printk("crtc:%d", __entry->crtc_id)
104);
105
106TRACE_EVENT(tracing_mark_write,
107 TP_PROTO(int pid, const char *name, bool trace_begin),
108 TP_ARGS(pid, name, trace_begin),
109 TP_STRUCT__entry(
110 __field(int, pid)
111 __string(trace_name, name)
112 __field(bool, trace_begin)
113 ),
114 TP_fast_assign(
115 __entry->pid = pid;
116 __assign_str(trace_name, name);
117 __entry->trace_begin = trace_begin;
118 ),
119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
120 __entry->pid, __get_str(trace_name))
121)
122
123TRACE_EVENT(dpu_trace_counter,
124 TP_PROTO(int pid, char *name, int value),
125 TP_ARGS(pid, name, value),
126 TP_STRUCT__entry(
127 __field(int, pid)
128 __string(counter_name, name)
129 __field(int, value)
130 ),
131 TP_fast_assign(
132 __entry->pid = current->tgid;
133 __assign_str(counter_name, name);
134 __entry->value = value;
135 ),
136 TP_printk("%d|%s|%d", __entry->pid,
137 __get_str(counter_name), __entry->value)
138)
139
140TRACE_EVENT(dpu_perf_crtc_update,
141 TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate,
142 bool stop_req, bool update_bus, bool update_clk),
143 TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk),
144 TP_STRUCT__entry(
145 __field(u32, crtc)
146 __field(u64, bw_ctl)
147 __field(u32, core_clk_rate)
148 __field(bool, stop_req)
149 __field(u32, update_bus)
150 __field(u32, update_clk)
151 ),
152 TP_fast_assign(
153 __entry->crtc = crtc;
154 __entry->bw_ctl = bw_ctl;
155 __entry->core_clk_rate = core_clk_rate;
156 __entry->stop_req = stop_req;
157 __entry->update_bus = update_bus;
158 __entry->update_clk = update_clk;
159 ),
160 TP_printk(
161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
162 __entry->crtc,
163 __entry->bw_ctl,
164 __entry->core_clk_rate,
165 __entry->stop_req,
166 __entry->update_bus,
167 __entry->update_clk)
168);
169
170DECLARE_EVENT_CLASS(dpu_enc_irq_template,
171 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
172 int irq_idx),
173 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
174 TP_STRUCT__entry(
175 __field( uint32_t, drm_id )
176 __field( enum dpu_intr_idx, intr_idx )
177 __field( int, hw_idx )
178 __field( int, irq_idx )
179 ),
180 TP_fast_assign(
181 __entry->drm_id = drm_id;
182 __entry->intr_idx = intr_idx;
183 __entry->hw_idx = hw_idx;
184 __entry->irq_idx = irq_idx;
185 ),
186 TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
187 __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
188 __entry->irq_idx)
189);
190DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
191 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
192 int irq_idx),
193 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
194);
195DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
196 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
197 int irq_idx),
198 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
199);
200
201TRACE_EVENT(dpu_enc_irq_wait_success,
202 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
203 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
204 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
205 TP_STRUCT__entry(
206 __field( uint32_t, drm_id )
207 __field( enum dpu_intr_idx, intr_idx )
208 __field( int, hw_idx )
209 __field( int, irq_idx )
210 __field( enum dpu_pingpong, pp_idx )
211 __field( int, atomic_cnt )
212 ),
213 TP_fast_assign(
214 __entry->drm_id = drm_id;
215 __entry->intr_idx = intr_idx;
216 __entry->hw_idx = hw_idx;
217 __entry->irq_idx = irq_idx;
218 __entry->pp_idx = pp_idx;
219 __entry->atomic_cnt = atomic_cnt;
220 ),
221 TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
222 __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
223 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
224);
225
226DECLARE_EVENT_CLASS(dpu_drm_obj_template,
227 TP_PROTO(uint32_t drm_id),
228 TP_ARGS(drm_id),
229 TP_STRUCT__entry(
230 __field( uint32_t, drm_id )
231 ),
232 TP_fast_assign(
233 __entry->drm_id = drm_id;
234 ),
235 TP_printk("id=%u", __entry->drm_id)
236);
237DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
238 TP_PROTO(uint32_t drm_id),
239 TP_ARGS(drm_id)
240);
241DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
242 TP_PROTO(uint32_t drm_id),
243 TP_ARGS(drm_id)
244);
245DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
246 TP_PROTO(uint32_t drm_id),
247 TP_ARGS(drm_id)
248);
249DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
250 TP_PROTO(uint32_t drm_id),
251 TP_ARGS(drm_id)
252);
253DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
254 TP_PROTO(uint32_t drm_id),
255 TP_ARGS(drm_id)
256);
257DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
258 TP_PROTO(uint32_t drm_id),
259 TP_ARGS(drm_id)
260);
261DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
262 TP_PROTO(uint32_t drm_id),
263 TP_ARGS(drm_id)
264);
265DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
266 TP_PROTO(uint32_t drm_id),
267 TP_ARGS(drm_id)
268);
269DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
270 TP_PROTO(uint32_t drm_id),
271 TP_ARGS(drm_id)
272);
273DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
274 TP_PROTO(uint32_t drm_id),
275 TP_ARGS(drm_id)
276);
277DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
278 TP_PROTO(uint32_t drm_id),
279 TP_ARGS(drm_id)
280);
281DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
282 TP_PROTO(uint32_t drm_id),
283 TP_ARGS(drm_id)
284);
285DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
286 TP_PROTO(uint32_t drm_id),
287 TP_ARGS(drm_id)
288);
289
290TRACE_EVENT(dpu_enc_enable,
291 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
292 TP_ARGS(drm_id, hdisplay, vdisplay),
293 TP_STRUCT__entry(
294 __field( uint32_t, drm_id )
295 __field( int, hdisplay )
296 __field( int, vdisplay )
297 ),
298 TP_fast_assign(
299 __entry->drm_id = drm_id;
300 __entry->hdisplay = hdisplay;
301 __entry->vdisplay = vdisplay;
302 ),
303 TP_printk("id=%u, mode=%dx%d",
304 __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
305);
306
307DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
308 TP_PROTO(uint32_t drm_id, int val),
309 TP_ARGS(drm_id, val),
310 TP_STRUCT__entry(
311 __field( uint32_t, drm_id )
312 __field( int, val )
313 ),
314 TP_fast_assign(
315 __entry->drm_id = drm_id;
316 __entry->val = val;
317 ),
318 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
319);
320DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
321 TP_PROTO(uint32_t drm_id, int count),
322 TP_ARGS(drm_id, count)
323);
324DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
325 TP_PROTO(uint32_t drm_id, int ctl_idx),
326 TP_ARGS(drm_id, ctl_idx)
327);
328
329TRACE_EVENT(dpu_enc_atomic_check_flags,
330 TP_PROTO(uint32_t drm_id, unsigned int flags, int private_flags),
331 TP_ARGS(drm_id, flags, private_flags),
332 TP_STRUCT__entry(
333 __field( uint32_t, drm_id )
334 __field( unsigned int, flags )
335 __field( int, private_flags )
336 ),
337 TP_fast_assign(
338 __entry->drm_id = drm_id;
339 __entry->flags = flags;
340 __entry->private_flags = private_flags;
341 ),
342 TP_printk("id=%u, flags=%u, private_flags=%d",
343 __entry->drm_id, __entry->flags, __entry->private_flags)
344);
345
346DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
347 TP_PROTO(uint32_t drm_id, bool enable),
348 TP_ARGS(drm_id, enable),
349 TP_STRUCT__entry(
350 __field( uint32_t, drm_id )
351 __field( bool, enable )
352 ),
353 TP_fast_assign(
354 __entry->drm_id = drm_id;
355 __entry->enable = enable;
356 ),
357 TP_printk("id=%u, enable=%s",
358 __entry->drm_id, __entry->enable ? "true" : "false")
359);
360DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
361 TP_PROTO(uint32_t drm_id, bool enable),
362 TP_ARGS(drm_id, enable)
363);
364DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
365 TP_PROTO(uint32_t drm_id, bool enable),
366 TP_ARGS(drm_id, enable)
367);
368DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
369 TP_PROTO(uint32_t drm_id, bool enable),
370 TP_ARGS(drm_id, enable)
371);
372DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
373 TP_PROTO(uint32_t drm_id, bool enable),
374 TP_ARGS(drm_id, enable)
375);
376
377TRACE_EVENT(dpu_enc_rc,
378 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
379 int rc_state, const char *stage),
380 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
381 TP_STRUCT__entry(
382 __field( uint32_t, drm_id )
383 __field( u32, sw_event )
384 __field( bool, idle_pc_supported )
385 __field( int, rc_state )
386 __string( stage_str, stage )
387 ),
388 TP_fast_assign(
389 __entry->drm_id = drm_id;
390 __entry->sw_event = sw_event;
391 __entry->idle_pc_supported = idle_pc_supported;
392 __entry->rc_state = rc_state;
393 __assign_str(stage_str, stage);
394 ),
395 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d\n",
396 __get_str(stage_str), __entry->drm_id, __entry->sw_event,
397 __entry->idle_pc_supported ? "true" : "false",
398 __entry->rc_state)
399);
400
401TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
402 TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx),
403 TP_ARGS(drm_id, event, intf_idx),
404 TP_STRUCT__entry(
405 __field( uint32_t, drm_id )
406 __field( u32, event )
407 __field( enum dpu_intf, intf_idx )
408 ),
409 TP_fast_assign(
410 __entry->drm_id = drm_id;
411 __entry->event = event;
412 __entry->intf_idx = intf_idx;
413 ),
414 TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event,
415 __entry->intf_idx)
416);
417
418TRACE_EVENT(dpu_enc_frame_done_cb,
419 TP_PROTO(uint32_t drm_id, unsigned int idx,
420 unsigned long frame_busy_mask),
421 TP_ARGS(drm_id, idx, frame_busy_mask),
422 TP_STRUCT__entry(
423 __field( uint32_t, drm_id )
424 __field( unsigned int, idx )
425 __field( unsigned long, frame_busy_mask )
426 ),
427 TP_fast_assign(
428 __entry->drm_id = drm_id;
429 __entry->idx = idx;
430 __entry->frame_busy_mask = frame_busy_mask;
431 ),
432 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
433 __entry->idx, __entry->frame_busy_mask)
434);
435
436TRACE_EVENT(dpu_enc_trigger_flush,
437 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
438 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
439 u32 pending_flush_ret),
440 TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx,
441 extra_flush_bits, pending_flush_ret),
442 TP_STRUCT__entry(
443 __field( uint32_t, drm_id )
444 __field( enum dpu_intf, intf_idx )
445 __field( int, pending_kickoff_cnt )
446 __field( int, ctl_idx )
447 __field( u32, extra_flush_bits )
448 __field( u32, pending_flush_ret )
449 ),
450 TP_fast_assign(
451 __entry->drm_id = drm_id;
452 __entry->intf_idx = intf_idx;
453 __entry->pending_kickoff_cnt = pending_kickoff_cnt;
454 __entry->ctl_idx = ctl_idx;
455 __entry->extra_flush_bits = extra_flush_bits;
456 __entry->pending_flush_ret = pending_flush_ret;
457 ),
458 TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
459 "extra_flush_bits=0x%x pending_flush_ret=0x%x",
460 __entry->drm_id, __entry->intf_idx,
461 __entry->pending_kickoff_cnt, __entry->ctl_idx,
462 __entry->extra_flush_bits, __entry->pending_flush_ret)
463);
464
465DECLARE_EVENT_CLASS(dpu_enc_ktime_template,
466 TP_PROTO(uint32_t drm_id, ktime_t time),
467 TP_ARGS(drm_id, time),
468 TP_STRUCT__entry(
469 __field( uint32_t, drm_id )
470 __field( ktime_t, time )
471 ),
472 TP_fast_assign(
473 __entry->drm_id = drm_id;
474 __entry->time = time;
475 ),
476 TP_printk("id=%u, time=%lld", __entry->drm_id,
477 ktime_to_ms(__entry->time))
478);
479DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work,
480 TP_PROTO(uint32_t drm_id, ktime_t time),
481 TP_ARGS(drm_id, time)
482);
483DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff,
484 TP_PROTO(uint32_t drm_id, ktime_t time),
485 TP_ARGS(drm_id, time)
486);
487
488DECLARE_EVENT_CLASS(dpu_id_event_template,
489 TP_PROTO(uint32_t drm_id, u32 event),
490 TP_ARGS(drm_id, event),
491 TP_STRUCT__entry(
492 __field( uint32_t, drm_id )
493 __field( u32, event )
494 ),
495 TP_fast_assign(
496 __entry->drm_id = drm_id;
497 __entry->event = event;
498 ),
499 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
500);
501DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
502 TP_PROTO(uint32_t drm_id, u32 event),
503 TP_ARGS(drm_id, event)
504);
505DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
506 TP_PROTO(uint32_t drm_id, u32 event),
507 TP_ARGS(drm_id, event)
508);
509DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
510 TP_PROTO(uint32_t drm_id, u32 event),
511 TP_ARGS(drm_id, event)
512);
513DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
514 TP_PROTO(uint32_t drm_id, u32 event),
515 TP_ARGS(drm_id, event)
516);
517
518TRACE_EVENT(dpu_enc_wait_event_timeout,
519 TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
520 s64 expected_time, int atomic_cnt),
521 TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
522 TP_STRUCT__entry(
523 __field( uint32_t, drm_id )
524 __field( int32_t, hw_id )
525 __field( int, rc )
526 __field( s64, time )
527 __field( s64, expected_time )
528 __field( int, atomic_cnt )
529 ),
530 TP_fast_assign(
531 __entry->drm_id = drm_id;
532 __entry->hw_id = hw_id;
533 __entry->rc = rc;
534 __entry->time = time;
535 __entry->expected_time = expected_time;
536 __entry->atomic_cnt = atomic_cnt;
537 ),
538 TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
539 __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
540 __entry->expected_time, __entry->atomic_cnt)
541);
542
543TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
544 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
545 int refcnt),
546 TP_ARGS(drm_id, pp, enable, refcnt),
547 TP_STRUCT__entry(
548 __field( uint32_t, drm_id )
549 __field( enum dpu_pingpong, pp )
550 __field( bool, enable )
551 __field( int, refcnt )
552 ),
553 TP_fast_assign(
554 __entry->drm_id = drm_id;
555 __entry->pp = pp;
556 __entry->enable = enable;
557 __entry->refcnt = refcnt;
558 ),
559 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
560 __entry->pp, __entry->enable ? "true" : "false",
561 __entry->refcnt)
562);
563
564TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
565 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
566 u32 event),
567 TP_ARGS(drm_id, pp, new_count, event),
568 TP_STRUCT__entry(
569 __field( uint32_t, drm_id )
570 __field( enum dpu_pingpong, pp )
571 __field( int, new_count )
572 __field( u32, event )
573 ),
574 TP_fast_assign(
575 __entry->drm_id = drm_id;
576 __entry->pp = pp;
577 __entry->new_count = new_count;
578 __entry->event = event;
579 ),
580 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
581 __entry->pp, __entry->new_count, __entry->event)
582);
583
584TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
585 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
586 int kickoff_count, u32 event),
587 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
588 TP_STRUCT__entry(
589 __field( uint32_t, drm_id )
590 __field( enum dpu_pingpong, pp )
591 __field( int, timeout_count )
592 __field( int, kickoff_count )
593 __field( u32, event )
594 ),
595 TP_fast_assign(
596 __entry->drm_id = drm_id;
597 __entry->pp = pp;
598 __entry->timeout_count = timeout_count;
599 __entry->kickoff_count = kickoff_count;
600 __entry->event = event;
601 ),
602 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
603 __entry->drm_id, __entry->pp, __entry->timeout_count,
604 __entry->kickoff_count, __entry->event)
605);
606
607TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
608 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
609 TP_ARGS(drm_id, intf_idx),
610 TP_STRUCT__entry(
611 __field( uint32_t, drm_id )
612 __field( enum dpu_intf, intf_idx )
613 ),
614 TP_fast_assign(
615 __entry->drm_id = drm_id;
616 __entry->intf_idx = intf_idx;
617 ),
618 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
619);
620
621TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
622 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
623 int refcnt),
624 TP_ARGS(drm_id, intf_idx, enable, refcnt),
625 TP_STRUCT__entry(
626 __field( uint32_t, drm_id )
627 __field( enum dpu_intf, intf_idx )
628 __field( bool, enable )
629 __field( int, refcnt )
630 ),
631 TP_fast_assign(
632 __entry->drm_id = drm_id;
633 __entry->intf_idx = intf_idx;
634 __entry->enable = enable;
635 __entry->refcnt = refcnt;
636 ),
637 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
638 __entry->intf_idx, __entry->enable ? "true" : "false",
639 __entry->drm_id)
640);
641
642TRACE_EVENT(dpu_crtc_setup_mixer,
643 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
644 struct drm_plane_state *state, struct dpu_plane_state *pstate,
645 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
646 uint64_t modifier),
647 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
648 pixel_format, modifier),
649 TP_STRUCT__entry(
650 __field( uint32_t, crtc_id )
651 __field( uint32_t, plane_id )
652 __field( uint32_t, fb_id )
653 __field_struct( struct drm_rect, src_rect )
654 __field_struct( struct drm_rect, dst_rect )
655 __field( uint32_t, stage_idx )
656 __field( enum dpu_stage, stage )
657 __field( enum dpu_sspp, sspp )
658 __field( uint32_t, multirect_idx )
659 __field( uint32_t, multirect_mode )
660 __field( uint32_t, pixel_format )
661 __field( uint64_t, modifier )
662 ),
663 TP_fast_assign(
664 __entry->crtc_id = crtc_id;
665 __entry->plane_id = plane_id;
666 __entry->fb_id = state ? state->fb->base.id : 0;
667 __entry->src_rect = drm_plane_state_src(state);
668 __entry->dst_rect = drm_plane_state_dest(state);
669 __entry->stage_idx = stage_idx;
670 __entry->stage = pstate->stage;
671 __entry->sspp = sspp;
672 __entry->multirect_idx = pstate->multirect_index;
673 __entry->multirect_mode = pstate->multirect_mode;
674 __entry->pixel_format = pixel_format;
675 __entry->modifier = modifier;
676 ),
677 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
678 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
679 "multirect_index:%d multirect_mode:%u pix_format:%u "
680 "modifier:%llu",
681 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
682 DRM_RECT_FP_ARG(&__entry->src_rect),
683 DRM_RECT_ARG(&__entry->dst_rect),
684 __entry->stage_idx, __entry->stage, __entry->sspp,
685 __entry->multirect_idx, __entry->multirect_mode,
686 __entry->pixel_format, __entry->modifier)
687);
688
689TRACE_EVENT(dpu_crtc_setup_lm_bounds,
690 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
691 TP_ARGS(drm_id, mixer, bounds),
692 TP_STRUCT__entry(
693 __field( uint32_t, drm_id )
694 __field( int, mixer )
695 __field_struct( struct drm_rect, bounds )
696 ),
697 TP_fast_assign(
698 __entry->drm_id = drm_id;
699 __entry->mixer = mixer;
700 __entry->bounds = *bounds;
701 ),
702 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
703 __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
704);
705
706TRACE_EVENT(dpu_crtc_vblank_enable,
707 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
708 struct dpu_crtc *crtc),
709 TP_ARGS(drm_id, enc_id, enable, crtc),
710 TP_STRUCT__entry(
711 __field( uint32_t, drm_id )
712 __field( uint32_t, enc_id )
713 __field( bool, enable )
714 __field( bool, enabled )
715 ),
716 TP_fast_assign(
717 __entry->drm_id = drm_id;
718 __entry->enc_id = enc_id;
719 __entry->enable = enable;
720 __entry->enabled = crtc->enabled;
721 ),
722 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
723 __entry->drm_id, __entry->enc_id,
724 __entry->enable ? "true" : "false",
725 __entry->enabled ? "true" : "false")
726);
727
728DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
729 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
730 TP_ARGS(drm_id, enable, crtc),
731 TP_STRUCT__entry(
732 __field( uint32_t, drm_id )
733 __field( bool, enable )
734 __field( bool, enabled )
735 ),
736 TP_fast_assign(
737 __entry->drm_id = drm_id;
738 __entry->enable = enable;
739 __entry->enabled = crtc->enabled;
740 ),
741 TP_printk("id:%u enable:%s state{enabled:%s}",
742 __entry->drm_id, __entry->enable ? "true" : "false",
743 __entry->enabled ? "true" : "false")
744);
745DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
746 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
747 TP_ARGS(drm_id, enable, crtc)
748);
749DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
750 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
751 TP_ARGS(drm_id, enable, crtc)
752);
753DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
754 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
755 TP_ARGS(drm_id, enable, crtc)
756);
757
758TRACE_EVENT(dpu_crtc_disable_frame_pending,
759 TP_PROTO(uint32_t drm_id, int frame_pending),
760 TP_ARGS(drm_id, frame_pending),
761 TP_STRUCT__entry(
762 __field( uint32_t, drm_id )
763 __field( int, frame_pending )
764 ),
765 TP_fast_assign(
766 __entry->drm_id = drm_id;
767 __entry->frame_pending = frame_pending;
768 ),
769 TP_printk("id:%u frame_pending:%d", __entry->drm_id,
770 __entry->frame_pending)
771);
772
773TRACE_EVENT(dpu_plane_set_scanout,
774 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
775 enum dpu_sspp_multirect_index multirect_index),
776 TP_ARGS(index, layout, multirect_index),
777 TP_STRUCT__entry(
778 __field( enum dpu_sspp, index )
779 __field_struct( struct dpu_hw_fmt_layout, layout )
780 __field( enum dpu_sspp_multirect_index, multirect_index)
781 ),
782 TP_fast_assign(
783 __entry->index = index;
784 __entry->layout = *layout;
785 __entry->multirect_index = multirect_index;
786 ),
787 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
788 "multirect_index:%d", __entry->index, __entry->layout.width,
789 __entry->layout.height, __entry->layout.plane_addr[0],
790 __entry->layout.plane_size[0],
791 __entry->layout.plane_addr[1],
792 __entry->layout.plane_size[1],
793 __entry->layout.plane_addr[2],
794 __entry->layout.plane_size[2],
795 __entry->layout.plane_addr[3],
796 __entry->layout.plane_size[3], __entry->multirect_index)
797);
798
799TRACE_EVENT(dpu_plane_disable,
800 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
801 TP_ARGS(drm_id, is_virtual, multirect_mode),
802 TP_STRUCT__entry(
803 __field( uint32_t, drm_id )
804 __field( bool, is_virtual )
805 __field( uint32_t, multirect_mode )
806 ),
807 TP_fast_assign(
808 __entry->drm_id = drm_id;
809 __entry->is_virtual = is_virtual;
810 __entry->multirect_mode = multirect_mode;
811 ),
812 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
813 __entry->is_virtual ? "true" : "false",
814 __entry->multirect_mode)
815);
816
817DECLARE_EVENT_CLASS(dpu_rm_iter_template,
818 TP_PROTO(uint32_t id, uint32_t enc_id),
819 TP_ARGS(id, enc_id),
820 TP_STRUCT__entry(
821 __field( uint32_t, id )
822 __field( uint32_t, enc_id )
823 ),
824 TP_fast_assign(
825 __entry->id = id;
826 __entry->enc_id = enc_id;
827 ),
828 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
829);
830DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
831 TP_PROTO(uint32_t id, uint32_t enc_id),
832 TP_ARGS(id, enc_id)
833);
834DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
835 TP_PROTO(uint32_t id, uint32_t enc_id),
836 TP_ARGS(id, enc_id)
837);
838
839TRACE_EVENT(dpu_rm_reserve_lms,
840 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
841 TP_ARGS(id, enc_id, pp_id),
842 TP_STRUCT__entry(
843 __field( uint32_t, id )
844 __field( uint32_t, enc_id )
845 __field( uint32_t, pp_id )
846 ),
847 TP_fast_assign(
848 __entry->id = id;
849 __entry->enc_id = enc_id;
850 __entry->pp_id = pp_id;
851 ),
852 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
853 __entry->enc_id, __entry->pp_id)
854);
855
856TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
857 TP_PROTO(enum dpu_vbif index, u32 xin_id),
858 TP_ARGS(index, xin_id),
859 TP_STRUCT__entry(
860 __field( enum dpu_vbif, index )
861 __field( u32, xin_id )
862 ),
863 TP_fast_assign(
864 __entry->index = index;
865 __entry->xin_id = xin_id;
866 ),
867 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
868);
869
870TRACE_EVENT(dpu_pp_connect_ext_te,
871 TP_PROTO(enum dpu_pingpong pp, u32 cfg),
872 TP_ARGS(pp, cfg),
873 TP_STRUCT__entry(
874 __field( enum dpu_pingpong, pp )
875 __field( u32, cfg )
876 ),
877 TP_fast_assign(
878 __entry->pp = pp;
879 __entry->cfg = cfg;
880 ),
881 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
882);
883
884DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
885 TP_PROTO(int irq_idx, int enable_count),
886 TP_ARGS(irq_idx, enable_count),
887 TP_STRUCT__entry(
888 __field( int, irq_idx )
889 __field( int, enable_count )
890 ),
891 TP_fast_assign(
892 __entry->irq_idx = irq_idx;
893 __entry->enable_count = enable_count;
894 ),
895 TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
896 __entry->enable_count)
897);
898DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
899 TP_PROTO(int irq_idx, int enable_count),
900 TP_ARGS(irq_idx, enable_count)
901);
902DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
903 TP_PROTO(int irq_idx, int enable_count),
904 TP_ARGS(irq_idx, enable_count)
905);
906
907DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
908 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
909 TP_ARGS(irq_idx, callback),
910 TP_STRUCT__entry(
911 __field( int, irq_idx )
912 __field( struct dpu_irq_callback *, callback)
913 ),
914 TP_fast_assign(
915 __entry->irq_idx = irq_idx;
916 __entry->callback = callback;
917 ),
918 TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx,
919 __entry->callback)
920);
921DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback,
922 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
923 TP_ARGS(irq_idx, callback)
924);
925DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback,
926 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
927 TP_ARGS(irq_idx, callback)
928);
929
930TRACE_EVENT(dpu_core_perf_update_clk,
931 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
932 TP_ARGS(dev, stop_req, clk_rate),
933 TP_STRUCT__entry(
934 __string( dev_name, dev->unique )
935 __field( bool, stop_req )
936 __field( u64, clk_rate )
937 ),
938 TP_fast_assign(
939 __assign_str(dev_name, dev->unique);
940 __entry->stop_req = stop_req;
941 __entry->clk_rate = clk_rate;
942 ),
943 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
944 __entry->stop_req ? "true" : "false", __entry->clk_rate)
945);
946
947TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
948 TP_PROTO(u32 new_bits, u32 pending_mask),
949 TP_ARGS(new_bits, pending_mask),
950 TP_STRUCT__entry(
951 __field( u32, new_bits )
952 __field( u32, pending_mask )
953 ),
954 TP_fast_assign(
955 __entry->new_bits = new_bits;
956 __entry->pending_mask = pending_mask;
957 ),
958 TP_printk("new=%x existing=%x", __entry->new_bits,
959 __entry->pending_mask)
960);
961
962DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
963 TP_PROTO(u32 pending_mask, u32 ctl_flush),
964 TP_ARGS(pending_mask, ctl_flush),
965 TP_STRUCT__entry(
966 __field( u32, pending_mask )
967 __field( u32, ctl_flush )
968 ),
969 TP_fast_assign(
970 __entry->pending_mask = pending_mask;
971 __entry->ctl_flush = ctl_flush;
972 ),
973 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
974 __entry->ctl_flush)
975);
976DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
977 TP_PROTO(u32 pending_mask, u32 ctl_flush),
978 TP_ARGS(pending_mask, ctl_flush)
979);
980DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
981 dpu_hw_ctl_trigger_pending_flush,
982 TP_PROTO(u32 pending_mask, u32 ctl_flush),
983 TP_ARGS(pending_mask, ctl_flush)
984);
985DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
986 TP_PROTO(u32 pending_mask, u32 ctl_flush),
987 TP_ARGS(pending_mask, ctl_flush)
988);
989DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
990 TP_PROTO(u32 pending_mask, u32 ctl_flush),
991 TP_ARGS(pending_mask, ctl_flush)
992);
993
994#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
995#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
996#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
997
998#define DPU_ATRACE_INT(name, value) \
999 trace_dpu_trace_counter(current->tgid, name, value)
1000
1001#endif
1002
1003
1004#undef TRACE_INCLUDE_PATH
1005#define TRACE_INCLUDE_PATH .
1006#include <trace/define_trace.h>
1007
