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7#ifndef __MDP5_KMS_H__
8#define __MDP5_KMS_H__
9
10#include "msm_drv.h"
11#include "msm_kms.h"
12#include "disp/mdp_kms.h"
13#include "mdp5_cfg.h"
14#include "mdp5.xml.h"
15#include "mdp5_pipe.h"
16#include "mdp5_mixer.h"
17#include "mdp5_ctl.h"
18#include "mdp5_smp.h"
19
20struct mdp5_kms {
21 struct mdp_kms base;
22
23 struct drm_device *dev;
24
25 struct platform_device *pdev;
26
27 unsigned num_hwpipes;
28 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
29
30 unsigned num_hwmixers;
31 struct mdp5_hw_mixer *hwmixers[8];
32
33 unsigned num_intfs;
34 struct mdp5_interface *intfs[5];
35
36 struct mdp5_cfg_handler *cfg;
37 uint32_t caps;
38
39
40
41
42
43 struct drm_modeset_lock glob_state_lock;
44 struct drm_private_obj glob_state;
45
46 struct mdp5_smp *smp;
47 struct mdp5_ctl_manager *ctlm;
48
49
50 void __iomem *mmio;
51
52 struct clk *axi_clk;
53 struct clk *ahb_clk;
54 struct clk *core_clk;
55 struct clk *lut_clk;
56 struct clk *vsync_clk;
57
58
59
60
61
62 spinlock_t resource_lock;
63
64 bool rpm_enabled;
65
66 struct mdp_irq error_handler;
67
68 int enable_count;
69};
70#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
71
72
73
74
75#define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)
76struct mdp5_global_state {
77 struct drm_private_state base;
78
79 struct drm_atomic_state *state;
80 struct mdp5_kms *mdp5_kms;
81
82 struct mdp5_hw_pipe_state hwpipe;
83 struct mdp5_hw_mixer_state hwmixer;
84 struct mdp5_smp_state smp;
85};
86
87struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
88struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s);
89
90
91
92
93struct mdp5_plane_state {
94 struct drm_plane_state base;
95
96 struct mdp5_hw_pipe *hwpipe;
97 struct mdp5_hw_pipe *r_hwpipe;
98
99
100 uint8_t premultiplied;
101 uint8_t zpos;
102 uint8_t alpha;
103
104
105 enum mdp_mixer_stage_id stage;
106};
107#define to_mdp5_plane_state(x) \
108 container_of(x, struct mdp5_plane_state, base)
109
110struct mdp5_pipeline {
111 struct mdp5_interface *intf;
112 struct mdp5_hw_mixer *mixer;
113 struct mdp5_hw_mixer *r_mixer;
114};
115
116struct mdp5_crtc_state {
117 struct drm_crtc_state base;
118
119 struct mdp5_ctl *ctl;
120 struct mdp5_pipeline pipeline;
121
122
123 u32 vblank_irqmask;
124 u32 err_irqmask;
125 u32 pp_done_irqmask;
126
127 bool cmd_mode;
128
129
130
131
132
133
134
135 bool defer_start;
136};
137#define to_mdp5_crtc_state(x) \
138 container_of(x, struct mdp5_crtc_state, base)
139
140enum mdp5_intf_mode {
141 MDP5_INTF_MODE_NONE = 0,
142
143
144 MDP5_INTF_DSI_MODE_VIDEO,
145 MDP5_INTF_DSI_MODE_COMMAND,
146
147
148 MDP5_INTF_WB_MODE_BLOCK,
149 MDP5_INTF_WB_MODE_LINE,
150};
151
152struct mdp5_interface {
153 int idx;
154 int num;
155 enum mdp5_intf_type type;
156 enum mdp5_intf_mode mode;
157};
158
159struct mdp5_encoder {
160 struct drm_encoder base;
161 spinlock_t intf_lock;
162 bool enabled;
163 uint32_t bsc;
164
165 struct mdp5_interface *intf;
166 struct mdp5_ctl *ctl;
167};
168#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
169
170static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
171{
172 WARN_ON(mdp5_kms->enable_count <= 0);
173 msm_writel(data, mdp5_kms->mmio + reg);
174}
175
176static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
177{
178 WARN_ON(mdp5_kms->enable_count <= 0);
179 return msm_readl(mdp5_kms->mmio + reg);
180}
181
182static inline const char *stage2name(enum mdp_mixer_stage_id stage)
183{
184 static const char *names[] = {
185#define NAME(n) [n] = #n
186 NAME(STAGE_UNUSED), NAME(STAGE_BASE),
187 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
188 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
189#undef NAME
190 };
191 return names[stage];
192}
193
194static inline const char *pipe2name(enum mdp5_pipe pipe)
195{
196 static const char *names[] = {
197#define NAME(n) [SSPP_ ## n] = #n
198 NAME(VIG0), NAME(VIG1), NAME(VIG2),
199 NAME(RGB0), NAME(RGB1), NAME(RGB2),
200 NAME(DMA0), NAME(DMA1),
201 NAME(VIG3), NAME(RGB3),
202 NAME(CURSOR0), NAME(CURSOR1),
203#undef NAME
204 };
205 return names[pipe];
206}
207
208static inline int pipe2nclients(enum mdp5_pipe pipe)
209{
210 switch (pipe) {
211 case SSPP_RGB0:
212 case SSPP_RGB1:
213 case SSPP_RGB2:
214 case SSPP_RGB3:
215 return 1;
216 default:
217 return 3;
218 }
219}
220
221static inline uint32_t intf2err(int intf_num)
222{
223 switch (intf_num) {
224 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
225 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
226 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
227 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
228 default: return 0;
229 }
230}
231
232static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,
233 struct mdp5_interface *intf)
234{
235
236
237
238
239
240
241 if ((intf->type == INTF_DSI) &&
242 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
243 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;
244
245 if (intf->type == INTF_WB)
246 return MDP5_IRQ_WB_2_DONE;
247
248 switch (intf->num) {
249 case 0: return MDP5_IRQ_INTF0_VSYNC;
250 case 1: return MDP5_IRQ_INTF1_VSYNC;
251 case 2: return MDP5_IRQ_INTF2_VSYNC;
252 case 3: return MDP5_IRQ_INTF3_VSYNC;
253 default: return 0;
254 }
255}
256
257static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)
258{
259 return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;
260}
261
262void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
263 uint32_t old_irqmask);
264void mdp5_irq_preinstall(struct msm_kms *kms);
265int mdp5_irq_postinstall(struct msm_kms *kms);
266void mdp5_irq_uninstall(struct msm_kms *kms);
267irqreturn_t mdp5_irq(struct msm_kms *kms);
268int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
269void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
270int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
271void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
272
273uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
274enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
275enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
276struct drm_plane *mdp5_plane_init(struct drm_device *dev,
277 enum drm_plane_type type);
278
279struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
280uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
281
282struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
283struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
284void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
285void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
286struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
287 struct drm_plane *plane,
288 struct drm_plane *cursor_plane, int id);
289
290struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
291 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
292int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
293 struct drm_encoder *slave_encoder);
294void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
295int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
296u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
297
298#ifdef CONFIG_DRM_MSM_DSI
299void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
300 struct drm_display_mode *mode,
301 struct drm_display_mode *adjusted_mode);
302void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
303void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
304int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
305 struct drm_encoder *slave_encoder);
306#else
307static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
308 struct drm_display_mode *mode,
309 struct drm_display_mode *adjusted_mode)
310{
311}
312static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
313{
314}
315static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
316{
317}
318static inline int mdp5_cmd_encoder_set_split_display(
319 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
320{
321 return -EINVAL;
322}
323#endif
324
325#endif
326