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5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/gpio.h>
10#include <linux/gpio/consumer.h>
11#include <linux/interrupt.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/of_irq.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/of_graph.h>
17#include <linux/regulator/consumer.h>
18#include <linux/spinlock.h>
19#include <linux/mfd/syscon.h>
20#include <linux/regmap.h>
21#include <video/mipi_display.h>
22
23#include "dsi.h"
24#include "dsi.xml.h"
25#include "sfpb.xml.h"
26#include "dsi_cfg.h"
27#include "msm_kms.h"
28
29static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
30{
31 u32 ver;
32
33 if (!major || !minor)
34 return -EINVAL;
35
36
37
38
39
40
41
42
43
44
45
46
47 ver = msm_readl(base + REG_DSI_VERSION);
48 if (ver) {
49
50 ver = FIELD(ver, DSI_VERSION_MAJOR);
51 if (ver <= MSM_DSI_VER_MAJOR_V2) {
52
53 *major = ver;
54 *minor = 0;
55 return 0;
56 } else {
57 return -EINVAL;
58 }
59 } else {
60
61
62
63
64
65 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
66 ver = FIELD(ver, DSI_VERSION_MAJOR);
67 if (ver == MSM_DSI_VER_MAJOR_6G) {
68
69 *major = ver;
70 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
71 return 0;
72 } else {
73 return -EINVAL;
74 }
75 }
76}
77
78#define DSI_ERR_STATE_ACK 0x0000
79#define DSI_ERR_STATE_TIMEOUT 0x0001
80#define DSI_ERR_STATE_DLN0_PHY 0x0002
81#define DSI_ERR_STATE_FIFO 0x0004
82#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
83#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
84#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
85
86#define DSI_CLK_CTRL_ENABLE_CLKS \
87 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
88 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
89 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
90 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
91
92struct msm_dsi_host {
93 struct mipi_dsi_host base;
94
95 struct platform_device *pdev;
96 struct drm_device *dev;
97
98 int id;
99
100 void __iomem *ctrl_base;
101 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
102
103 struct clk *bus_clks[DSI_BUS_CLK_MAX];
104
105 struct clk *byte_clk;
106 struct clk *esc_clk;
107 struct clk *pixel_clk;
108 struct clk *byte_clk_src;
109 struct clk *pixel_clk_src;
110 struct clk *byte_intf_clk;
111
112 u32 byte_clk_rate;
113 u32 pixel_clk_rate;
114 u32 esc_clk_rate;
115
116
117 struct clk *src_clk;
118 struct clk *esc_clk_src;
119 struct clk *dsi_clk_src;
120
121 u32 src_clk_rate;
122
123 struct gpio_desc *disp_en_gpio;
124 struct gpio_desc *te_gpio;
125
126 const struct msm_dsi_cfg_handler *cfg_hnd;
127
128 struct completion dma_comp;
129 struct completion video_comp;
130 struct mutex dev_mutex;
131 struct mutex cmd_mutex;
132 spinlock_t intr_lock;
133
134 u32 err_work_state;
135 struct work_struct err_work;
136 struct work_struct hpd_work;
137 struct workqueue_struct *workqueue;
138
139
140 struct drm_gem_object *tx_gem_obj;
141
142
143 void *tx_buf;
144 dma_addr_t tx_buf_paddr;
145
146 int tx_size;
147
148 u8 *rx_buf;
149
150 struct regmap *sfpb;
151
152 struct drm_display_mode *mode;
153
154
155 struct device_node *device_node;
156 unsigned int channel;
157 unsigned int lanes;
158 enum mipi_dsi_pixel_format format;
159 unsigned long mode_flags;
160
161
162 int dlane_swap;
163 int num_data_lanes;
164
165 u32 dma_cmd_ctrl_restore;
166
167 bool registered;
168 bool power_on;
169 bool enabled;
170 int irq;
171};
172
173static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
174{
175 switch (fmt) {
176 case MIPI_DSI_FMT_RGB565: return 16;
177 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
178 case MIPI_DSI_FMT_RGB666:
179 case MIPI_DSI_FMT_RGB888:
180 default: return 24;
181 }
182}
183
184static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
185{
186 return msm_readl(msm_host->ctrl_base + reg);
187}
188static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
189{
190 msm_writel(data, msm_host->ctrl_base + reg);
191}
192
193static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
194static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
195
196static const struct msm_dsi_cfg_handler *dsi_get_config(
197 struct msm_dsi_host *msm_host)
198{
199 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
200 struct device *dev = &msm_host->pdev->dev;
201 struct regulator *gdsc_reg;
202 struct clk *ahb_clk;
203 int ret;
204 u32 major = 0, minor = 0;
205
206 gdsc_reg = regulator_get(dev, "gdsc");
207 if (IS_ERR(gdsc_reg)) {
208 pr_err("%s: cannot get gdsc\n", __func__);
209 goto exit;
210 }
211
212 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
213 if (IS_ERR(ahb_clk)) {
214 pr_err("%s: cannot get interface clock\n", __func__);
215 goto put_gdsc;
216 }
217
218 pm_runtime_get_sync(dev);
219
220 ret = regulator_enable(gdsc_reg);
221 if (ret) {
222 pr_err("%s: unable to enable gdsc\n", __func__);
223 goto put_gdsc;
224 }
225
226 ret = clk_prepare_enable(ahb_clk);
227 if (ret) {
228 pr_err("%s: unable to enable ahb_clk\n", __func__);
229 goto disable_gdsc;
230 }
231
232 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
233 if (ret) {
234 pr_err("%s: Invalid version\n", __func__);
235 goto disable_clks;
236 }
237
238 cfg_hnd = msm_dsi_cfg_get(major, minor);
239
240 DBG("%s: Version %x:%x\n", __func__, major, minor);
241
242disable_clks:
243 clk_disable_unprepare(ahb_clk);
244disable_gdsc:
245 regulator_disable(gdsc_reg);
246 pm_runtime_put_sync(dev);
247put_gdsc:
248 regulator_put(gdsc_reg);
249exit:
250 return cfg_hnd;
251}
252
253static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
254{
255 return container_of(host, struct msm_dsi_host, base);
256}
257
258static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
259{
260 struct regulator_bulk_data *s = msm_host->supplies;
261 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
262 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
263 int i;
264
265 DBG("");
266 for (i = num - 1; i >= 0; i--)
267 if (regs[i].disable_load >= 0)
268 regulator_set_load(s[i].consumer,
269 regs[i].disable_load);
270
271 regulator_bulk_disable(num, s);
272}
273
274static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
275{
276 struct regulator_bulk_data *s = msm_host->supplies;
277 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
278 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
279 int ret, i;
280
281 DBG("");
282 for (i = 0; i < num; i++) {
283 if (regs[i].enable_load >= 0) {
284 ret = regulator_set_load(s[i].consumer,
285 regs[i].enable_load);
286 if (ret < 0) {
287 pr_err("regulator %d set op mode failed, %d\n",
288 i, ret);
289 goto fail;
290 }
291 }
292 }
293
294 ret = regulator_bulk_enable(num, s);
295 if (ret < 0) {
296 pr_err("regulator enable failed, %d\n", ret);
297 goto fail;
298 }
299
300 return 0;
301
302fail:
303 for (i--; i >= 0; i--)
304 regulator_set_load(s[i].consumer, regs[i].disable_load);
305 return ret;
306}
307
308static int dsi_regulator_init(struct msm_dsi_host *msm_host)
309{
310 struct regulator_bulk_data *s = msm_host->supplies;
311 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
312 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
313 int i, ret;
314
315 for (i = 0; i < num; i++)
316 s[i].supply = regs[i].name;
317
318 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
319 if (ret < 0) {
320 pr_err("%s: failed to init regulator, ret=%d\n",
321 __func__, ret);
322 return ret;
323 }
324
325 return 0;
326}
327
328int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
329{
330 struct platform_device *pdev = msm_host->pdev;
331 int ret = 0;
332
333 msm_host->src_clk = msm_clk_get(pdev, "src");
334
335 if (IS_ERR(msm_host->src_clk)) {
336 ret = PTR_ERR(msm_host->src_clk);
337 pr_err("%s: can't find src clock. ret=%d\n",
338 __func__, ret);
339 msm_host->src_clk = NULL;
340 return ret;
341 }
342
343 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
344 if (!msm_host->esc_clk_src) {
345 ret = -ENODEV;
346 pr_err("%s: can't get esc clock parent. ret=%d\n",
347 __func__, ret);
348 return ret;
349 }
350
351 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
352 if (!msm_host->dsi_clk_src) {
353 ret = -ENODEV;
354 pr_err("%s: can't get src clock parent. ret=%d\n",
355 __func__, ret);
356 }
357
358 return ret;
359}
360
361int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
362{
363 struct platform_device *pdev = msm_host->pdev;
364 int ret = 0;
365
366 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
367 if (IS_ERR(msm_host->byte_intf_clk)) {
368 ret = PTR_ERR(msm_host->byte_intf_clk);
369 pr_err("%s: can't find byte_intf clock. ret=%d\n",
370 __func__, ret);
371 }
372
373 return ret;
374}
375
376static int dsi_clk_init(struct msm_dsi_host *msm_host)
377{
378 struct platform_device *pdev = msm_host->pdev;
379 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
380 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
381 int i, ret = 0;
382
383
384 for (i = 0; i < cfg->num_bus_clks; i++) {
385 msm_host->bus_clks[i] = msm_clk_get(pdev,
386 cfg->bus_clk_names[i]);
387 if (IS_ERR(msm_host->bus_clks[i])) {
388 ret = PTR_ERR(msm_host->bus_clks[i]);
389 pr_err("%s: Unable to get %s clock, ret = %d\n",
390 __func__, cfg->bus_clk_names[i], ret);
391 goto exit;
392 }
393 }
394
395
396 msm_host->byte_clk = msm_clk_get(pdev, "byte");
397 if (IS_ERR(msm_host->byte_clk)) {
398 ret = PTR_ERR(msm_host->byte_clk);
399 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
400 __func__, ret);
401 msm_host->byte_clk = NULL;
402 goto exit;
403 }
404
405 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
406 if (IS_ERR(msm_host->pixel_clk)) {
407 ret = PTR_ERR(msm_host->pixel_clk);
408 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
409 __func__, ret);
410 msm_host->pixel_clk = NULL;
411 goto exit;
412 }
413
414 msm_host->esc_clk = msm_clk_get(pdev, "core");
415 if (IS_ERR(msm_host->esc_clk)) {
416 ret = PTR_ERR(msm_host->esc_clk);
417 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
418 __func__, ret);
419 msm_host->esc_clk = NULL;
420 goto exit;
421 }
422
423 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
424 if (!msm_host->byte_clk_src) {
425 ret = -ENODEV;
426 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
427 goto exit;
428 }
429
430 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
431 if (!msm_host->pixel_clk_src) {
432 ret = -ENODEV;
433 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
434 goto exit;
435 }
436
437 if (cfg_hnd->ops->clk_init_ver)
438 ret = cfg_hnd->ops->clk_init_ver(msm_host);
439exit:
440 return ret;
441}
442
443static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
444{
445 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
446 int i, ret;
447
448 DBG("id=%d", msm_host->id);
449
450 for (i = 0; i < cfg->num_bus_clks; i++) {
451 ret = clk_prepare_enable(msm_host->bus_clks[i]);
452 if (ret) {
453 pr_err("%s: failed to enable bus clock %d ret %d\n",
454 __func__, i, ret);
455 goto err;
456 }
457 }
458
459 return 0;
460err:
461 for (; i > 0; i--)
462 clk_disable_unprepare(msm_host->bus_clks[i]);
463
464 return ret;
465}
466
467static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
468{
469 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
470 int i;
471
472 DBG("");
473
474 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
475 clk_disable_unprepare(msm_host->bus_clks[i]);
476}
477
478int msm_dsi_runtime_suspend(struct device *dev)
479{
480 struct platform_device *pdev = to_platform_device(dev);
481 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
482 struct mipi_dsi_host *host = msm_dsi->host;
483 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
484
485 if (!msm_host->cfg_hnd)
486 return 0;
487
488 dsi_bus_clk_disable(msm_host);
489
490 return 0;
491}
492
493int msm_dsi_runtime_resume(struct device *dev)
494{
495 struct platform_device *pdev = to_platform_device(dev);
496 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
497 struct mipi_dsi_host *host = msm_dsi->host;
498 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
499
500 if (!msm_host->cfg_hnd)
501 return 0;
502
503 return dsi_bus_clk_enable(msm_host);
504}
505
506int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
507{
508 int ret;
509
510 DBG("Set clk rates: pclk=%d, byteclk=%d",
511 msm_host->mode->clock, msm_host->byte_clk_rate);
512
513 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
514 if (ret) {
515 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
516 goto error;
517 }
518
519 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
520 if (ret) {
521 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
522 goto error;
523 }
524
525 if (msm_host->byte_intf_clk) {
526 ret = clk_set_rate(msm_host->byte_intf_clk,
527 msm_host->byte_clk_rate / 2);
528 if (ret) {
529 pr_err("%s: Failed to set rate byte intf clk, %d\n",
530 __func__, ret);
531 goto error;
532 }
533 }
534
535 ret = clk_prepare_enable(msm_host->esc_clk);
536 if (ret) {
537 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
538 goto error;
539 }
540
541 ret = clk_prepare_enable(msm_host->byte_clk);
542 if (ret) {
543 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
544 goto byte_clk_err;
545 }
546
547 ret = clk_prepare_enable(msm_host->pixel_clk);
548 if (ret) {
549 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
550 goto pixel_clk_err;
551 }
552
553 if (msm_host->byte_intf_clk) {
554 ret = clk_prepare_enable(msm_host->byte_intf_clk);
555 if (ret) {
556 pr_err("%s: Failed to enable byte intf clk\n",
557 __func__);
558 goto byte_intf_clk_err;
559 }
560 }
561
562 return 0;
563
564byte_intf_clk_err:
565 clk_disable_unprepare(msm_host->pixel_clk);
566pixel_clk_err:
567 clk_disable_unprepare(msm_host->byte_clk);
568byte_clk_err:
569 clk_disable_unprepare(msm_host->esc_clk);
570error:
571 return ret;
572}
573
574int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
575{
576 int ret;
577
578 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
579 msm_host->mode->clock, msm_host->byte_clk_rate,
580 msm_host->esc_clk_rate, msm_host->src_clk_rate);
581
582 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
583 if (ret) {
584 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
585 goto error;
586 }
587
588 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
589 if (ret) {
590 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
591 goto error;
592 }
593
594 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
595 if (ret) {
596 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
597 goto error;
598 }
599
600 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
601 if (ret) {
602 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
603 goto error;
604 }
605
606 ret = clk_prepare_enable(msm_host->byte_clk);
607 if (ret) {
608 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
609 goto error;
610 }
611
612 ret = clk_prepare_enable(msm_host->esc_clk);
613 if (ret) {
614 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
615 goto esc_clk_err;
616 }
617
618 ret = clk_prepare_enable(msm_host->src_clk);
619 if (ret) {
620 pr_err("%s: Failed to enable dsi src clk\n", __func__);
621 goto src_clk_err;
622 }
623
624 ret = clk_prepare_enable(msm_host->pixel_clk);
625 if (ret) {
626 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
627 goto pixel_clk_err;
628 }
629
630 return 0;
631
632pixel_clk_err:
633 clk_disable_unprepare(msm_host->src_clk);
634src_clk_err:
635 clk_disable_unprepare(msm_host->esc_clk);
636esc_clk_err:
637 clk_disable_unprepare(msm_host->byte_clk);
638error:
639 return ret;
640}
641
642void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
643{
644 clk_disable_unprepare(msm_host->esc_clk);
645 clk_disable_unprepare(msm_host->pixel_clk);
646 if (msm_host->byte_intf_clk)
647 clk_disable_unprepare(msm_host->byte_intf_clk);
648 clk_disable_unprepare(msm_host->byte_clk);
649}
650
651void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
652{
653 clk_disable_unprepare(msm_host->pixel_clk);
654 clk_disable_unprepare(msm_host->src_clk);
655 clk_disable_unprepare(msm_host->esc_clk);
656 clk_disable_unprepare(msm_host->byte_clk);
657}
658
659static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
660{
661 struct drm_display_mode *mode = msm_host->mode;
662 u32 pclk_rate;
663
664 pclk_rate = mode->clock * 1000;
665
666
667
668
669
670
671
672 if (is_dual_dsi)
673 pclk_rate /= 2;
674
675 return pclk_rate;
676}
677
678static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi)
679{
680 u8 lanes = msm_host->lanes;
681 u32 bpp = dsi_get_bpp(msm_host->format);
682 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi);
683 u64 pclk_bpp = (u64)pclk_rate * bpp;
684
685 if (lanes == 0) {
686 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
687 lanes = 1;
688 }
689
690 do_div(pclk_bpp, (8 * lanes));
691
692 msm_host->pixel_clk_rate = pclk_rate;
693 msm_host->byte_clk_rate = pclk_bpp;
694
695 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
696 msm_host->byte_clk_rate);
697
698}
699
700int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
701{
702 if (!msm_host->mode) {
703 pr_err("%s: mode not set\n", __func__);
704 return -EINVAL;
705 }
706
707 dsi_calc_pclk(msm_host, is_dual_dsi);
708 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
709 return 0;
710}
711
712int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
713{
714 u32 bpp = dsi_get_bpp(msm_host->format);
715 u64 pclk_bpp;
716 unsigned int esc_mhz, esc_div;
717 unsigned long byte_mhz;
718
719 dsi_calc_pclk(msm_host, is_dual_dsi);
720
721 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp;
722 do_div(pclk_bpp, 8);
723 msm_host->src_clk_rate = pclk_bpp;
724
725
726
727
728
729
730
731
732
733
734 byte_mhz = msm_host->byte_clk_rate / 1000000;
735
736 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
737 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
738
739
740
741
742
743
744
745 if (esc_div >= 1 && esc_div <= 16)
746 break;
747 }
748
749 if (esc_mhz < 5)
750 return -EINVAL;
751
752 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
753
754 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
755 msm_host->src_clk_rate);
756
757 return 0;
758}
759
760static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
761{
762 u32 intr;
763 unsigned long flags;
764
765 spin_lock_irqsave(&msm_host->intr_lock, flags);
766 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
767
768 if (enable)
769 intr |= mask;
770 else
771 intr &= ~mask;
772
773 DBG("intr=%x enable=%d", intr, enable);
774
775 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
776 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
777}
778
779static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
780{
781 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
782 return BURST_MODE;
783 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
784 return NON_BURST_SYNCH_PULSE;
785
786 return NON_BURST_SYNCH_EVENT;
787}
788
789static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
790 const enum mipi_dsi_pixel_format mipi_fmt)
791{
792 switch (mipi_fmt) {
793 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
794 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
795 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
796 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
797 default: return VID_DST_FORMAT_RGB888;
798 }
799}
800
801static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
802 const enum mipi_dsi_pixel_format mipi_fmt)
803{
804 switch (mipi_fmt) {
805 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
806 case MIPI_DSI_FMT_RGB666_PACKED:
807 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
808 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
809 default: return CMD_DST_FORMAT_RGB888;
810 }
811}
812
813static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
814 struct msm_dsi_phy_shared_timings *phy_shared_timings)
815{
816 u32 flags = msm_host->mode_flags;
817 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
818 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
819 u32 data = 0;
820
821 if (!enable) {
822 dsi_write(msm_host, REG_DSI_CTRL, 0);
823 return;
824 }
825
826 if (flags & MIPI_DSI_MODE_VIDEO) {
827 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
828 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
829 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
830 data |= DSI_VID_CFG0_HFP_POWER_STOP;
831 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
832 data |= DSI_VID_CFG0_HBP_POWER_STOP;
833 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
834 data |= DSI_VID_CFG0_HSA_POWER_STOP;
835
836
837
838 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
839 DSI_VID_CFG0_BLLP_POWER_STOP;
840 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
841 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
842 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
843 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
844
845
846 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
847 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
848 } else {
849
850 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
851 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
852 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
853
854 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
855 DSI_CMD_CFG1_WR_MEM_CONTINUE(
856 MIPI_DCS_WRITE_MEMORY_CONTINUE);
857
858 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
859 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
860 }
861
862 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
863 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
864 DSI_CMD_DMA_CTRL_LOW_POWER);
865
866 data = 0;
867
868 data |= DSI_TRIG_CTRL_TE;
869 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
870 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
871 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
872 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
873 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
874 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
875 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
876
877 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
878 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
879 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
880
881 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
882 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
883 phy_shared_timings->clk_pre_inc_by_2)
884 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
885 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
886
887 data = 0;
888 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
889 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
890 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
891
892
893 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
894
895 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
896
897 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
898
899 data = DSI_CTRL_CLK_EN;
900
901 DBG("lane number=%d", msm_host->lanes);
902 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
903
904 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
905 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
906
907 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
908 dsi_write(msm_host, REG_DSI_LANE_CTRL,
909 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
910
911 data |= DSI_CTRL_ENABLE;
912
913 dsi_write(msm_host, REG_DSI_CTRL, data);
914}
915
916static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
917{
918 struct drm_display_mode *mode = msm_host->mode;
919 u32 hs_start = 0, vs_start = 0;
920 u32 h_total = mode->htotal;
921 u32 v_total = mode->vtotal;
922 u32 hs_end = mode->hsync_end - mode->hsync_start;
923 u32 vs_end = mode->vsync_end - mode->vsync_start;
924 u32 ha_start = h_total - mode->hsync_start;
925 u32 ha_end = ha_start + mode->hdisplay;
926 u32 va_start = v_total - mode->vsync_start;
927 u32 va_end = va_start + mode->vdisplay;
928 u32 hdisplay = mode->hdisplay;
929 u32 wc;
930
931 DBG("");
932
933
934
935
936
937
938
939
940 if (is_dual_dsi) {
941 h_total /= 2;
942 hs_end /= 2;
943 ha_start /= 2;
944 ha_end /= 2;
945 hdisplay /= 2;
946 }
947
948 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
949 dsi_write(msm_host, REG_DSI_ACTIVE_H,
950 DSI_ACTIVE_H_START(ha_start) |
951 DSI_ACTIVE_H_END(ha_end));
952 dsi_write(msm_host, REG_DSI_ACTIVE_V,
953 DSI_ACTIVE_V_START(va_start) |
954 DSI_ACTIVE_V_END(va_end));
955 dsi_write(msm_host, REG_DSI_TOTAL,
956 DSI_TOTAL_H_TOTAL(h_total - 1) |
957 DSI_TOTAL_V_TOTAL(v_total - 1));
958
959 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
960 DSI_ACTIVE_HSYNC_START(hs_start) |
961 DSI_ACTIVE_HSYNC_END(hs_end));
962 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
963 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
964 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
965 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
966 } else {
967
968 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
969
970 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
971 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
972 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
973 msm_host->channel) |
974 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
975 MIPI_DSI_DCS_LONG_WRITE));
976
977 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
978 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
979 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
980 }
981}
982
983static void dsi_sw_reset(struct msm_dsi_host *msm_host)
984{
985 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
986 wmb();
987
988 dsi_write(msm_host, REG_DSI_RESET, 1);
989 wmb();
990 dsi_write(msm_host, REG_DSI_RESET, 0);
991}
992
993static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
994 bool video_mode, bool enable)
995{
996 u32 dsi_ctrl;
997
998 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
999
1000 if (!enable) {
1001 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1002 DSI_CTRL_CMD_MODE_EN);
1003 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1004 DSI_IRQ_MASK_VIDEO_DONE, 0);
1005 } else {
1006 if (video_mode) {
1007 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1008 } else {
1009 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1010 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1011 }
1012 dsi_ctrl |= DSI_CTRL_ENABLE;
1013 }
1014
1015 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1016}
1017
1018static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1019{
1020 u32 data;
1021
1022 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1023
1024 if (mode == 0)
1025 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1026 else
1027 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1028
1029 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1030}
1031
1032static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1033{
1034 u32 ret = 0;
1035 struct device *dev = &msm_host->pdev->dev;
1036
1037 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1038
1039 reinit_completion(&msm_host->video_comp);
1040
1041 ret = wait_for_completion_timeout(&msm_host->video_comp,
1042 msecs_to_jiffies(70));
1043
1044 if (ret == 0)
1045 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1046
1047 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1048}
1049
1050static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1051{
1052 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1053 return;
1054
1055 if (msm_host->power_on && msm_host->enabled) {
1056 dsi_wait4video_done(msm_host);
1057
1058 usleep_range(2000, 4000);
1059 }
1060}
1061
1062int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1063{
1064 struct drm_device *dev = msm_host->dev;
1065 struct msm_drm_private *priv = dev->dev_private;
1066 uint64_t iova;
1067 u8 *data;
1068
1069 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
1070 priv->kms->aspace,
1071 &msm_host->tx_gem_obj, &iova);
1072
1073 if (IS_ERR(data)) {
1074 msm_host->tx_gem_obj = NULL;
1075 return PTR_ERR(data);
1076 }
1077
1078 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1079
1080 msm_host->tx_size = msm_host->tx_gem_obj->size;
1081
1082 return 0;
1083}
1084
1085int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1086{
1087 struct drm_device *dev = msm_host->dev;
1088
1089 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1090 &msm_host->tx_buf_paddr, GFP_KERNEL);
1091 if (!msm_host->tx_buf)
1092 return -ENOMEM;
1093
1094 msm_host->tx_size = size;
1095
1096 return 0;
1097}
1098
1099static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1100{
1101 struct drm_device *dev = msm_host->dev;
1102 struct msm_drm_private *priv;
1103
1104
1105
1106
1107
1108
1109
1110 if (!dev)
1111 return;
1112
1113 priv = dev->dev_private;
1114 if (msm_host->tx_gem_obj) {
1115 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1116 drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
1117 msm_host->tx_gem_obj = NULL;
1118 }
1119
1120 if (msm_host->tx_buf)
1121 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1122 msm_host->tx_buf_paddr);
1123}
1124
1125void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1126{
1127 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1128}
1129
1130void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1131{
1132 return msm_host->tx_buf;
1133}
1134
1135void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1136{
1137 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1138}
1139
1140
1141
1142
1143static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1144 const struct mipi_dsi_msg *msg)
1145{
1146 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1147 struct mipi_dsi_packet packet;
1148 int len;
1149 int ret;
1150 u8 *data;
1151
1152 ret = mipi_dsi_create_packet(&packet, msg);
1153 if (ret) {
1154 pr_err("%s: create packet failed, %d\n", __func__, ret);
1155 return ret;
1156 }
1157 len = (packet.size + 3) & (~0x3);
1158
1159 if (len > msm_host->tx_size) {
1160 pr_err("%s: packet size is too big\n", __func__);
1161 return -EINVAL;
1162 }
1163
1164 data = cfg_hnd->ops->tx_buf_get(msm_host);
1165 if (IS_ERR(data)) {
1166 ret = PTR_ERR(data);
1167 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1168 return ret;
1169 }
1170
1171
1172 data[0] = packet.header[1];
1173 data[1] = packet.header[2];
1174 data[2] = packet.header[0];
1175 data[3] = BIT(7);
1176 if (mipi_dsi_packet_format_is_long(msg->type))
1177 data[3] |= BIT(6);
1178 if (msg->rx_buf && msg->rx_len)
1179 data[3] |= BIT(5);
1180
1181
1182 if (packet.payload && packet.payload_length)
1183 memcpy(data + 4, packet.payload, packet.payload_length);
1184
1185
1186 if (packet.size < len)
1187 memset(data + packet.size, 0xff, len - packet.size);
1188
1189 if (cfg_hnd->ops->tx_buf_put)
1190 cfg_hnd->ops->tx_buf_put(msm_host);
1191
1192 return len;
1193}
1194
1195
1196
1197
1198static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1199{
1200 u8 *data = msg->rx_buf;
1201 if (data && (msg->rx_len >= 1)) {
1202 *data = buf[1];
1203 return 1;
1204 } else {
1205 pr_err("%s: read data does not match with rx_buf len %zu\n",
1206 __func__, msg->rx_len);
1207 return -EINVAL;
1208 }
1209}
1210
1211
1212
1213
1214static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1215{
1216 u8 *data = msg->rx_buf;
1217 if (data && (msg->rx_len >= 2)) {
1218 data[0] = buf[1];
1219 data[1] = buf[2];
1220 return 2;
1221 } else {
1222 pr_err("%s: read data does not match with rx_buf len %zu\n",
1223 __func__, msg->rx_len);
1224 return -EINVAL;
1225 }
1226}
1227
1228static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1229{
1230
1231 if (msg->rx_buf && msg->rx_len)
1232 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1233
1234 return msg->rx_len;
1235}
1236
1237int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1238{
1239 struct drm_device *dev = msm_host->dev;
1240 struct msm_drm_private *priv = dev->dev_private;
1241
1242 if (!dma_base)
1243 return -EINVAL;
1244
1245 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1246 priv->kms->aspace, dma_base);
1247}
1248
1249int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1250{
1251 if (!dma_base)
1252 return -EINVAL;
1253
1254 *dma_base = msm_host->tx_buf_paddr;
1255 return 0;
1256}
1257
1258static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1259{
1260 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1261 int ret;
1262 uint64_t dma_base;
1263 bool triggered;
1264
1265 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1266 if (ret) {
1267 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1268 return ret;
1269 }
1270
1271 reinit_completion(&msm_host->dma_comp);
1272
1273 dsi_wait4video_eng_busy(msm_host);
1274
1275 triggered = msm_dsi_manager_cmd_xfer_trigger(
1276 msm_host->id, dma_base, len);
1277 if (triggered) {
1278 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1279 msecs_to_jiffies(200));
1280 DBG("ret=%d", ret);
1281 if (ret == 0)
1282 ret = -ETIMEDOUT;
1283 else
1284 ret = len;
1285 } else
1286 ret = len;
1287
1288 return ret;
1289}
1290
1291static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1292 u8 *buf, int rx_byte, int pkt_size)
1293{
1294 u32 *lp, *temp, data;
1295 int i, j = 0, cnt;
1296 u32 read_cnt;
1297 u8 reg[16];
1298 int repeated_bytes = 0;
1299 int buf_offset = buf - msm_host->rx_buf;
1300
1301 lp = (u32 *)buf;
1302 temp = (u32 *)reg;
1303 cnt = (rx_byte + 3) >> 2;
1304 if (cnt > 4)
1305 cnt = 4;
1306
1307 if (rx_byte == 4)
1308 read_cnt = 4;
1309 else
1310 read_cnt = pkt_size + 6;
1311
1312
1313
1314
1315
1316
1317
1318
1319 if (read_cnt > 16) {
1320 int bytes_shifted;
1321
1322
1323
1324
1325 bytes_shifted = read_cnt - 16;
1326 repeated_bytes = buf_offset - bytes_shifted;
1327 }
1328
1329 for (i = cnt - 1; i >= 0; i--) {
1330 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1331 *temp++ = ntohl(data);
1332 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1333 }
1334
1335 for (i = repeated_bytes; i < 16; i++)
1336 buf[j++] = reg[i];
1337
1338 return j;
1339}
1340
1341static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1342 const struct mipi_dsi_msg *msg)
1343{
1344 int len, ret;
1345 int bllp_len = msm_host->mode->hdisplay *
1346 dsi_get_bpp(msm_host->format) / 8;
1347
1348 len = dsi_cmd_dma_add(msm_host, msg);
1349 if (!len) {
1350 pr_err("%s: failed to add cmd type = 0x%x\n",
1351 __func__, msg->type);
1352 return -EINVAL;
1353 }
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1365 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1366 __func__, len);
1367 return -EINVAL;
1368 }
1369
1370 ret = dsi_cmd_dma_tx(msm_host, len);
1371 if (ret < len) {
1372 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1373 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1374 return -ECOMM;
1375 }
1376
1377 return len;
1378}
1379
1380static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1381{
1382 u32 data0, data1;
1383
1384 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1385 data1 = data0;
1386 data1 &= ~DSI_CTRL_ENABLE;
1387 dsi_write(msm_host, REG_DSI_CTRL, data1);
1388
1389
1390
1391
1392 wmb();
1393
1394 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1395 wmb();
1396
1397
1398 dsi_write(msm_host, REG_DSI_RESET, 1);
1399 wmb();
1400 dsi_write(msm_host, REG_DSI_RESET, 0);
1401 wmb();
1402 dsi_write(msm_host, REG_DSI_CTRL, data0);
1403 wmb();
1404}
1405
1406static void dsi_hpd_worker(struct work_struct *work)
1407{
1408 struct msm_dsi_host *msm_host =
1409 container_of(work, struct msm_dsi_host, hpd_work);
1410
1411 drm_helper_hpd_irq_event(msm_host->dev);
1412}
1413
1414static void dsi_err_worker(struct work_struct *work)
1415{
1416 struct msm_dsi_host *msm_host =
1417 container_of(work, struct msm_dsi_host, err_work);
1418 u32 status = msm_host->err_work_state;
1419
1420 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1421 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1422 dsi_sw_reset_restore(msm_host);
1423
1424
1425 msm_host->err_work_state = 0;
1426
1427
1428 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1429}
1430
1431static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1432{
1433 u32 status;
1434
1435 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1436
1437 if (status) {
1438 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1439
1440 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1441 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1442 }
1443}
1444
1445static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1446{
1447 u32 status;
1448
1449 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1450
1451 if (status) {
1452 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1453 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1454 }
1455}
1456
1457static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1458{
1459 u32 status;
1460
1461 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1462
1463 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1464 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1465 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1466 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1467 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1468 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1469 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1470 }
1471}
1472
1473static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1474{
1475 u32 status;
1476
1477 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1478
1479
1480 if (status) {
1481 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1482 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1483 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1484 msm_host->err_work_state |=
1485 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1486 }
1487}
1488
1489static void dsi_status(struct msm_dsi_host *msm_host)
1490{
1491 u32 status;
1492
1493 status = dsi_read(msm_host, REG_DSI_STATUS0);
1494
1495 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1496 dsi_write(msm_host, REG_DSI_STATUS0, status);
1497 msm_host->err_work_state |=
1498 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1499 }
1500}
1501
1502static void dsi_clk_status(struct msm_dsi_host *msm_host)
1503{
1504 u32 status;
1505
1506 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1507
1508 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1509 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1510 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1511 }
1512}
1513
1514static void dsi_error(struct msm_dsi_host *msm_host)
1515{
1516
1517 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1518
1519 dsi_clk_status(msm_host);
1520 dsi_fifo_status(msm_host);
1521 dsi_ack_err_status(msm_host);
1522 dsi_timeout_status(msm_host);
1523 dsi_status(msm_host);
1524 dsi_dln0_phy_err(msm_host);
1525
1526 queue_work(msm_host->workqueue, &msm_host->err_work);
1527}
1528
1529static irqreturn_t dsi_host_irq(int irq, void *ptr)
1530{
1531 struct msm_dsi_host *msm_host = ptr;
1532 u32 isr;
1533 unsigned long flags;
1534
1535 if (!msm_host->ctrl_base)
1536 return IRQ_HANDLED;
1537
1538 spin_lock_irqsave(&msm_host->intr_lock, flags);
1539 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1540 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1541 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1542
1543 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1544
1545 if (isr & DSI_IRQ_ERROR)
1546 dsi_error(msm_host);
1547
1548 if (isr & DSI_IRQ_VIDEO_DONE)
1549 complete(&msm_host->video_comp);
1550
1551 if (isr & DSI_IRQ_CMD_DMA_DONE)
1552 complete(&msm_host->dma_comp);
1553
1554 return IRQ_HANDLED;
1555}
1556
1557static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1558 struct device *panel_device)
1559{
1560 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1561 "disp-enable",
1562 GPIOD_OUT_LOW);
1563 if (IS_ERR(msm_host->disp_en_gpio)) {
1564 DBG("cannot get disp-enable-gpios %ld",
1565 PTR_ERR(msm_host->disp_en_gpio));
1566 return PTR_ERR(msm_host->disp_en_gpio);
1567 }
1568
1569 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1570 GPIOD_IN);
1571 if (IS_ERR(msm_host->te_gpio)) {
1572 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1573 return PTR_ERR(msm_host->te_gpio);
1574 }
1575
1576 return 0;
1577}
1578
1579static int dsi_host_attach(struct mipi_dsi_host *host,
1580 struct mipi_dsi_device *dsi)
1581{
1582 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1583 int ret;
1584
1585 if (dsi->lanes > msm_host->num_data_lanes)
1586 return -EINVAL;
1587
1588 msm_host->channel = dsi->channel;
1589 msm_host->lanes = dsi->lanes;
1590 msm_host->format = dsi->format;
1591 msm_host->mode_flags = dsi->mode_flags;
1592
1593
1594 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1595 if (ret)
1596 return ret;
1597
1598 DBG("id=%d", msm_host->id);
1599 if (msm_host->dev)
1600 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1601
1602 return 0;
1603}
1604
1605static int dsi_host_detach(struct mipi_dsi_host *host,
1606 struct mipi_dsi_device *dsi)
1607{
1608 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1609
1610 msm_host->device_node = NULL;
1611
1612 DBG("id=%d", msm_host->id);
1613 if (msm_host->dev)
1614 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1615
1616 return 0;
1617}
1618
1619static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1620 const struct mipi_dsi_msg *msg)
1621{
1622 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1623 int ret;
1624
1625 if (!msg || !msm_host->power_on)
1626 return -EINVAL;
1627
1628 mutex_lock(&msm_host->cmd_mutex);
1629 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1630 mutex_unlock(&msm_host->cmd_mutex);
1631
1632 return ret;
1633}
1634
1635static struct mipi_dsi_host_ops dsi_host_ops = {
1636 .attach = dsi_host_attach,
1637 .detach = dsi_host_detach,
1638 .transfer = dsi_host_transfer,
1639};
1640
1641
1642
1643
1644
1645
1646
1647static const int supported_data_lane_swaps[][4] = {
1648 { 0, 1, 2, 3 },
1649 { 3, 0, 1, 2 },
1650 { 2, 3, 0, 1 },
1651 { 1, 2, 3, 0 },
1652 { 0, 3, 2, 1 },
1653 { 1, 0, 3, 2 },
1654 { 2, 1, 0, 3 },
1655 { 3, 2, 1, 0 },
1656};
1657
1658static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1659 struct device_node *ep)
1660{
1661 struct device *dev = &msm_host->pdev->dev;
1662 struct property *prop;
1663 u32 lane_map[4];
1664 int ret, i, len, num_lanes;
1665
1666 prop = of_find_property(ep, "data-lanes", &len);
1667 if (!prop) {
1668 DRM_DEV_DEBUG(dev,
1669 "failed to find data lane mapping, using default\n");
1670 return 0;
1671 }
1672
1673 num_lanes = len / sizeof(u32);
1674
1675 if (num_lanes < 1 || num_lanes > 4) {
1676 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1677 return -EINVAL;
1678 }
1679
1680 msm_host->num_data_lanes = num_lanes;
1681
1682 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1683 num_lanes);
1684 if (ret) {
1685 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1686 return ret;
1687 }
1688
1689
1690
1691
1692
1693 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1694 const int *swap = supported_data_lane_swaps[i];
1695 int j;
1696
1697
1698
1699
1700
1701
1702
1703
1704 for (j = 0; j < num_lanes; j++) {
1705 if (lane_map[j] < 0 || lane_map[j] > 3)
1706 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1707 lane_map[j]);
1708
1709 if (swap[lane_map[j]] != j)
1710 break;
1711 }
1712
1713 if (j == num_lanes) {
1714 msm_host->dlane_swap = i;
1715 return 0;
1716 }
1717 }
1718
1719 return -EINVAL;
1720}
1721
1722static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1723{
1724 struct device *dev = &msm_host->pdev->dev;
1725 struct device_node *np = dev->of_node;
1726 struct device_node *endpoint, *device_node;
1727 int ret = 0;
1728
1729
1730
1731
1732
1733
1734
1735 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1736 if (!endpoint) {
1737 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1738 return 0;
1739 }
1740
1741 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1742 if (ret) {
1743 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1744 __func__, ret);
1745 ret = -EINVAL;
1746 goto err;
1747 }
1748
1749
1750 device_node = of_graph_get_remote_node(np, 1, 0);
1751 if (!device_node) {
1752 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__);
1753 ret = -ENODEV;
1754 goto err;
1755 }
1756
1757 msm_host->device_node = device_node;
1758
1759 if (of_property_read_bool(np, "syscon-sfpb")) {
1760 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1761 "syscon-sfpb");
1762 if (IS_ERR(msm_host->sfpb)) {
1763 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1764 __func__);
1765 ret = PTR_ERR(msm_host->sfpb);
1766 }
1767 }
1768
1769 of_node_put(device_node);
1770
1771err:
1772 of_node_put(endpoint);
1773
1774 return ret;
1775}
1776
1777static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1778{
1779 struct platform_device *pdev = msm_host->pdev;
1780 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1781 struct resource *res;
1782 int i;
1783
1784 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1785 if (!res)
1786 return -EINVAL;
1787
1788 for (i = 0; i < cfg->num_dsi; i++) {
1789 if (cfg->io_start[i] == res->start)
1790 return i;
1791 }
1792
1793 return -EINVAL;
1794}
1795
1796int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1797{
1798 struct msm_dsi_host *msm_host = NULL;
1799 struct platform_device *pdev = msm_dsi->pdev;
1800 int ret;
1801
1802 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1803 if (!msm_host) {
1804 pr_err("%s: FAILED: cannot alloc dsi host\n",
1805 __func__);
1806 ret = -ENOMEM;
1807 goto fail;
1808 }
1809
1810 msm_host->pdev = pdev;
1811 msm_dsi->host = &msm_host->base;
1812
1813 ret = dsi_host_parse_dt(msm_host);
1814 if (ret) {
1815 pr_err("%s: failed to parse dt\n", __func__);
1816 goto fail;
1817 }
1818
1819 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1820 if (IS_ERR(msm_host->ctrl_base)) {
1821 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1822 ret = PTR_ERR(msm_host->ctrl_base);
1823 goto fail;
1824 }
1825
1826 pm_runtime_enable(&pdev->dev);
1827
1828 msm_host->cfg_hnd = dsi_get_config(msm_host);
1829 if (!msm_host->cfg_hnd) {
1830 ret = -EINVAL;
1831 pr_err("%s: get config failed\n", __func__);
1832 goto fail;
1833 }
1834
1835 msm_host->id = dsi_host_get_id(msm_host);
1836 if (msm_host->id < 0) {
1837 ret = msm_host->id;
1838 pr_err("%s: unable to identify DSI host index\n", __func__);
1839 goto fail;
1840 }
1841
1842
1843 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1844
1845 ret = dsi_regulator_init(msm_host);
1846 if (ret) {
1847 pr_err("%s: regulator init failed\n", __func__);
1848 goto fail;
1849 }
1850
1851 ret = dsi_clk_init(msm_host);
1852 if (ret) {
1853 pr_err("%s: unable to initialize dsi clks\n", __func__);
1854 goto fail;
1855 }
1856
1857 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1858 if (!msm_host->rx_buf) {
1859 ret = -ENOMEM;
1860 pr_err("%s: alloc rx temp buf failed\n", __func__);
1861 goto fail;
1862 }
1863
1864 init_completion(&msm_host->dma_comp);
1865 init_completion(&msm_host->video_comp);
1866 mutex_init(&msm_host->dev_mutex);
1867 mutex_init(&msm_host->cmd_mutex);
1868 spin_lock_init(&msm_host->intr_lock);
1869
1870
1871 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1872 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1873 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1874
1875 msm_dsi->id = msm_host->id;
1876
1877 DBG("Dsi Host %d initialized", msm_host->id);
1878 return 0;
1879
1880fail:
1881 return ret;
1882}
1883
1884void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1885{
1886 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1887
1888 DBG("");
1889 dsi_tx_buf_free(msm_host);
1890 if (msm_host->workqueue) {
1891 flush_workqueue(msm_host->workqueue);
1892 destroy_workqueue(msm_host->workqueue);
1893 msm_host->workqueue = NULL;
1894 }
1895
1896 mutex_destroy(&msm_host->cmd_mutex);
1897 mutex_destroy(&msm_host->dev_mutex);
1898
1899 pm_runtime_disable(&msm_host->pdev->dev);
1900}
1901
1902int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1903 struct drm_device *dev)
1904{
1905 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1906 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1907 struct platform_device *pdev = msm_host->pdev;
1908 int ret;
1909
1910 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1911 if (msm_host->irq < 0) {
1912 ret = msm_host->irq;
1913 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
1914 return ret;
1915 }
1916
1917 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1918 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1919 "dsi_isr", msm_host);
1920 if (ret < 0) {
1921 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n",
1922 msm_host->irq, ret);
1923 return ret;
1924 }
1925
1926 msm_host->dev = dev;
1927 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1928 if (ret) {
1929 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1930 return ret;
1931 }
1932
1933 return 0;
1934}
1935
1936int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1937{
1938 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1939 int ret;
1940
1941
1942 if (!msm_host->registered) {
1943 host->dev = &msm_host->pdev->dev;
1944 host->ops = &dsi_host_ops;
1945 ret = mipi_dsi_host_register(host);
1946 if (ret)
1947 return ret;
1948
1949 msm_host->registered = true;
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959 if (check_defer && msm_host->device_node) {
1960 if (IS_ERR(of_drm_find_panel(msm_host->device_node)))
1961 if (!of_drm_find_bridge(msm_host->device_node))
1962 return -EPROBE_DEFER;
1963 }
1964 }
1965
1966 return 0;
1967}
1968
1969void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1970{
1971 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1972
1973 if (msm_host->registered) {
1974 mipi_dsi_host_unregister(host);
1975 host->dev = NULL;
1976 host->ops = NULL;
1977 msm_host->registered = false;
1978 }
1979}
1980
1981int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1982 const struct mipi_dsi_msg *msg)
1983{
1984 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1985 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997 pm_runtime_get_sync(&msm_host->pdev->dev);
1998 cfg_hnd->ops->link_clk_enable(msm_host);
1999
2000
2001
2002 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2003 dsi_set_tx_power_mode(0, msm_host);
2004
2005 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2006 dsi_write(msm_host, REG_DSI_CTRL,
2007 msm_host->dma_cmd_ctrl_restore |
2008 DSI_CTRL_CMD_MODE_EN |
2009 DSI_CTRL_ENABLE);
2010 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2011
2012 return 0;
2013}
2014
2015void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2016 const struct mipi_dsi_msg *msg)
2017{
2018 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2019 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2020
2021 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2022 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2023
2024 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2025 dsi_set_tx_power_mode(1, msm_host);
2026
2027
2028
2029 cfg_hnd->ops->link_clk_disable(msm_host);
2030 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2031}
2032
2033int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2034 const struct mipi_dsi_msg *msg)
2035{
2036 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2037
2038 return dsi_cmds2buf_tx(msm_host, msg);
2039}
2040
2041int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2042 const struct mipi_dsi_msg *msg)
2043{
2044 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2045 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2046 int data_byte, rx_byte, dlen, end;
2047 int short_response, diff, pkt_size, ret = 0;
2048 char cmd;
2049 int rlen = msg->rx_len;
2050 u8 *buf;
2051
2052 if (rlen <= 2) {
2053 short_response = 1;
2054 pkt_size = rlen;
2055 rx_byte = 4;
2056 } else {
2057 short_response = 0;
2058 data_byte = 10;
2059 if (rlen < data_byte)
2060 pkt_size = rlen;
2061 else
2062 pkt_size = data_byte;
2063 rx_byte = data_byte + 6;
2064 }
2065
2066 buf = msm_host->rx_buf;
2067 end = 0;
2068 while (!end) {
2069 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2070 struct mipi_dsi_msg max_pkt_size_msg = {
2071 .channel = msg->channel,
2072 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2073 .tx_len = 2,
2074 .tx_buf = tx,
2075 };
2076
2077 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2078 rlen, pkt_size, rx_byte);
2079
2080 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2081 if (ret < 2) {
2082 pr_err("%s: Set max pkt size failed, %d\n",
2083 __func__, ret);
2084 return -EINVAL;
2085 }
2086
2087 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2088 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2089
2090 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2091 DSI_RDBK_DATA_CTRL_CLR);
2092 wmb();
2093 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2094 wmb();
2095 }
2096
2097 ret = dsi_cmds2buf_tx(msm_host, msg);
2098 if (ret < msg->tx_len) {
2099 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2100 return ret;
2101 }
2102
2103
2104
2105
2106
2107
2108
2109
2110 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2111
2112 if (dlen <= 0)
2113 return 0;
2114
2115 if (short_response)
2116 break;
2117
2118 if (rlen <= data_byte) {
2119 diff = data_byte - rlen;
2120 end = 1;
2121 } else {
2122 diff = 0;
2123 rlen -= data_byte;
2124 }
2125
2126 if (!end) {
2127 dlen -= 2;
2128 dlen -= diff;
2129 buf += dlen;
2130 data_byte = 14;
2131 if (rlen < data_byte)
2132 pkt_size += rlen;
2133 else
2134 pkt_size += data_byte;
2135 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2136 }
2137 }
2138
2139
2140
2141
2142
2143
2144
2145 if (pkt_size < 10 && !short_response)
2146 buf = msm_host->rx_buf + (10 - rlen);
2147 else
2148 buf = msm_host->rx_buf;
2149
2150 cmd = buf[0];
2151 switch (cmd) {
2152 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2153 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2154 ret = 0;
2155 break;
2156 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2157 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2158 ret = dsi_short_read1_resp(buf, msg);
2159 break;
2160 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2161 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2162 ret = dsi_short_read2_resp(buf, msg);
2163 break;
2164 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2165 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2166 ret = dsi_long_read_resp(buf, msg);
2167 break;
2168 default:
2169 pr_warn("%s:Invalid response cmd\n", __func__);
2170 ret = 0;
2171 }
2172
2173 return ret;
2174}
2175
2176void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2177 u32 len)
2178{
2179 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2180
2181 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2182 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2183 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2184
2185
2186 wmb();
2187}
2188
2189int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2190 struct msm_dsi_pll *src_pll)
2191{
2192 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2193 struct clk *byte_clk_provider, *pixel_clk_provider;
2194 int ret;
2195
2196 ret = msm_dsi_pll_get_clk_provider(src_pll,
2197 &byte_clk_provider, &pixel_clk_provider);
2198 if (ret) {
2199 pr_info("%s: can't get provider from pll, don't set parent\n",
2200 __func__);
2201 return 0;
2202 }
2203
2204 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2205 if (ret) {
2206 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2207 __func__, ret);
2208 goto exit;
2209 }
2210
2211 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2212 if (ret) {
2213 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2214 __func__, ret);
2215 goto exit;
2216 }
2217
2218 if (msm_host->dsi_clk_src) {
2219 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2220 if (ret) {
2221 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2222 __func__, ret);
2223 goto exit;
2224 }
2225 }
2226
2227 if (msm_host->esc_clk_src) {
2228 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2229 if (ret) {
2230 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2231 __func__, ret);
2232 goto exit;
2233 }
2234 }
2235
2236exit:
2237 return ret;
2238}
2239
2240void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2241{
2242 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2243
2244 DBG("");
2245 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2246
2247 wmb();
2248 udelay(1000);
2249 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2250 udelay(100);
2251}
2252
2253void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2254 struct msm_dsi_phy_clk_request *clk_req,
2255 bool is_dual_dsi)
2256{
2257 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2258 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2259 int ret;
2260
2261 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi);
2262 if (ret) {
2263 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2264 return;
2265 }
2266
2267 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2268 clk_req->escclk_rate = msm_host->esc_clk_rate;
2269}
2270
2271int msm_dsi_host_enable(struct mipi_dsi_host *host)
2272{
2273 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2274
2275 dsi_op_mode_config(msm_host,
2276 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287 msm_host->enabled = true;
2288 return 0;
2289}
2290
2291int msm_dsi_host_disable(struct mipi_dsi_host *host)
2292{
2293 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2294
2295 msm_host->enabled = false;
2296 dsi_op_mode_config(msm_host,
2297 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2298
2299
2300
2301
2302
2303 dsi_sw_reset(msm_host);
2304
2305 return 0;
2306}
2307
2308static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2309{
2310 enum sfpb_ahb_arb_master_port_en en;
2311
2312 if (!msm_host->sfpb)
2313 return;
2314
2315 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2316
2317 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2318 SFPB_GPREG_MASTER_PORT_EN__MASK,
2319 SFPB_GPREG_MASTER_PORT_EN(en));
2320}
2321
2322int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2323 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2324 bool is_dual_dsi)
2325{
2326 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2327 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2328 int ret = 0;
2329
2330 mutex_lock(&msm_host->dev_mutex);
2331 if (msm_host->power_on) {
2332 DBG("dsi host already on");
2333 goto unlock_ret;
2334 }
2335
2336 msm_dsi_sfpb_config(msm_host, true);
2337
2338 ret = dsi_host_regulator_enable(msm_host);
2339 if (ret) {
2340 pr_err("%s:Failed to enable vregs.ret=%d\n",
2341 __func__, ret);
2342 goto unlock_ret;
2343 }
2344
2345 pm_runtime_get_sync(&msm_host->pdev->dev);
2346 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2347 if (ret) {
2348 pr_err("%s: failed to enable link clocks. ret=%d\n",
2349 __func__, ret);
2350 goto fail_disable_reg;
2351 }
2352
2353 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2354 if (ret) {
2355 pr_err("%s: failed to set pinctrl default state, %d\n",
2356 __func__, ret);
2357 goto fail_disable_clk;
2358 }
2359
2360 dsi_timing_setup(msm_host, is_dual_dsi);
2361 dsi_sw_reset(msm_host);
2362 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2363
2364 if (msm_host->disp_en_gpio)
2365 gpiod_set_value(msm_host->disp_en_gpio, 1);
2366
2367 msm_host->power_on = true;
2368 mutex_unlock(&msm_host->dev_mutex);
2369
2370 return 0;
2371
2372fail_disable_clk:
2373 cfg_hnd->ops->link_clk_disable(msm_host);
2374 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2375fail_disable_reg:
2376 dsi_host_regulator_disable(msm_host);
2377unlock_ret:
2378 mutex_unlock(&msm_host->dev_mutex);
2379 return ret;
2380}
2381
2382int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2383{
2384 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2386
2387 mutex_lock(&msm_host->dev_mutex);
2388 if (!msm_host->power_on) {
2389 DBG("dsi host already off");
2390 goto unlock_ret;
2391 }
2392
2393 dsi_ctrl_config(msm_host, false, NULL);
2394
2395 if (msm_host->disp_en_gpio)
2396 gpiod_set_value(msm_host->disp_en_gpio, 0);
2397
2398 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2399
2400 cfg_hnd->ops->link_clk_disable(msm_host);
2401 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2402
2403 dsi_host_regulator_disable(msm_host);
2404
2405 msm_dsi_sfpb_config(msm_host, false);
2406
2407 DBG("-");
2408
2409 msm_host->power_on = false;
2410
2411unlock_ret:
2412 mutex_unlock(&msm_host->dev_mutex);
2413 return 0;
2414}
2415
2416int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2417 const struct drm_display_mode *mode)
2418{
2419 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2420
2421 if (msm_host->mode) {
2422 drm_mode_destroy(msm_host->dev, msm_host->mode);
2423 msm_host->mode = NULL;
2424 }
2425
2426 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2427 if (!msm_host->mode) {
2428 pr_err("%s: cannot duplicate mode\n", __func__);
2429 return -ENOMEM;
2430 }
2431
2432 return 0;
2433}
2434
2435struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
2436{
2437 return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
2438}
2439
2440unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2441{
2442 return to_msm_dsi_host(host)->mode_flags;
2443}
2444
2445struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2446{
2447 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2448
2449 return of_drm_find_bridge(msm_host->device_node);
2450}
2451