1#ifndef __NV50_KMS_ATOM_H__
2#define __NV50_KMS_ATOM_H__
3#define nv50_atom(p) container_of((p), struct nv50_atom, state)
4#include <drm/drm_atomic.h>
5
6struct nv50_atom {
7 struct drm_atomic_state state;
8
9 struct list_head outp;
10 bool lock_core;
11 bool flush_disable;
12};
13
14#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
15
16struct nv50_head_atom {
17 struct drm_crtc_state state;
18
19 struct {
20 u32 mask;
21 u32 olut;
22 } wndw;
23
24 struct {
25 u16 iW;
26 u16 iH;
27 u16 oW;
28 u16 oH;
29 } view;
30
31 struct nv50_head_mode {
32 bool interlace;
33 u32 clock;
34 struct {
35 u16 active;
36 u16 synce;
37 u16 blanke;
38 u16 blanks;
39 } h;
40 struct {
41 u32 active;
42 u16 synce;
43 u16 blanke;
44 u16 blanks;
45 u16 blank2s;
46 u16 blank2e;
47 u16 blankus;
48 } v;
49 } mode;
50
51 struct {
52 bool visible;
53 u32 handle;
54 u64 offset:40;
55 u8 buffer:1;
56 u8 mode:4;
57 u16 size:11;
58 u8 range:2;
59 u8 output_mode:2;
60 void (*load)(struct drm_color_lut *, int size, void __iomem *);
61 } olut;
62
63 struct {
64 bool visible;
65 u32 handle;
66 u64 offset:40;
67 u8 format;
68 u8 kind:7;
69 u8 layout:1;
70 u8 blockh:4;
71 u16 blocks:12;
72 u32 pitch:20;
73 u16 x;
74 u16 y;
75 u16 w;
76 u16 h;
77 } core;
78
79 struct {
80 bool visible;
81 u32 handle;
82 u64 offset:40;
83 u8 layout:2;
84 u8 format:8;
85 } curs;
86
87 struct {
88 u8 depth;
89 u8 cpp;
90 u16 x;
91 u16 y;
92 u16 w;
93 u16 h;
94 } base;
95
96 struct {
97 u8 cpp;
98 } ovly;
99
100 struct {
101 bool enable:1;
102 u8 bits:2;
103 u8 mode:4;
104 } dither;
105
106 struct {
107 struct {
108 u16 cos:12;
109 u16 sin:12;
110 } sat;
111 } procamp;
112
113 struct {
114 u8 nhsync:1;
115 u8 nvsync:1;
116 u8 depth:4;
117 } or;
118
119
120 struct {
121 int pbn;
122 u8 tu:6;
123 } dp;
124
125 union nv50_head_atom_mask {
126 struct {
127 bool olut:1;
128 bool core:1;
129 bool curs:1;
130 bool view:1;
131 bool mode:1;
132 bool base:1;
133 bool ovly:1;
134 bool dither:1;
135 bool procamp:1;
136 bool or:1;
137 };
138 u16 mask;
139 } set, clr;
140};
141
142static inline struct nv50_head_atom *
143nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
144{
145 struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
146 if (IS_ERR(statec))
147 return (void *)statec;
148 return nv50_head_atom(statec);
149}
150
151#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
152
153struct nv50_wndw_atom {
154 struct drm_plane_state state;
155
156 struct drm_property_blob *ilut;
157 bool visible;
158
159 struct {
160 u32 handle;
161 u16 offset:12;
162 bool awaken:1;
163 } ntfy;
164
165 struct {
166 u32 handle;
167 u16 offset:12;
168 u32 acquire;
169 u32 release;
170 } sema;
171
172 struct {
173 u32 handle;
174 struct {
175 u64 offset:40;
176 u8 buffer:1;
177 u8 enable:2;
178 u8 mode:4;
179 u16 size:11;
180 u8 range:2;
181 u8 output_mode:2;
182 void (*load)(struct drm_color_lut *, int size,
183 void __iomem *);
184 } i;
185 } xlut;
186
187 struct {
188 u8 mode:2;
189 u8 interval:4;
190
191 u8 colorspace:2;
192 u8 format;
193 u8 kind:7;
194 u8 layout:1;
195 u8 blockh:4;
196 u16 blocks[3];
197 u32 pitch[3];
198 u16 w;
199 u16 h;
200
201 u32 handle[6];
202 u64 offset[6];
203 } image;
204
205 struct {
206 u16 sx;
207 u16 sy;
208 u16 sw;
209 u16 sh;
210 u16 dw;
211 u16 dh;
212 } scale;
213
214 struct {
215 u16 x;
216 u16 y;
217 } point;
218
219 union nv50_wndw_atom_mask {
220 struct {
221 bool ntfy:1;
222 bool sema:1;
223 bool xlut:1;
224 bool image:1;
225 bool scale:1;
226 bool point:1;
227 };
228 u8 mask;
229 } set, clr;
230};
231#endif
232
