LXR linux/drivers/gpu/drm/nouveau/nvc0

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include "nouveau_drv.h"
  26#include "nouveau_dma.h"
  27#include "nouveau_fence.h"
  28
  29#include "nv50_display.h"
  30
  31static int
  32nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  33{
  34        int ret = RING_SPACE(chan, 6);
  35        if (ret == 0) {
  36                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
  37                OUT_RING  (chan, upper_32_bits(virtual));
  38                OUT_RING  (chan, lower_32_bits(virtual));
  39                OUT_RING  (chan, sequence);
  40                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  41                OUT_RING  (chan, 0x00000000);
  42                FIRE_RING (chan);
  43        }
  44        return ret;
  45}
  46
  47static int
  48nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  49{
  50        int ret = RING_SPACE(chan, 5);
  51        if (ret == 0) {
  52                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  53                OUT_RING  (chan, upper_32_bits(virtual));
  54                OUT_RING  (chan, lower_32_bits(virtual));
  55                OUT_RING  (chan, sequence);
  56                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
  57                                 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
  58                FIRE_RING (chan);
  59        }
  60        return ret;
  61}
  62
  63static int
  64nvc0_fence_context_new(struct nouveau_channel *chan)
  65{
  66        int ret = nv84_fence_context_new(chan);
  67        if (ret == 0) {
  68                struct nv84_fence_chan *fctx = chan->fence;
  69                fctx->base.emit32 = nvc0_fence_emit32;
  70                fctx->base.sync32 = nvc0_fence_sync32;
  71        }
  72        return ret;
  73}
  74
  75int
  76nvc0_fence_create(struct nouveau_drm *drm)
  77{
  78        int ret = nv84_fence_create(drm);
  79        if (ret == 0) {
  80                struct nv84_fence_priv *priv = drm->fence;
  81                priv->base.context_new = nvc0_fence_context_new;
  82        }
  83        return ret;
  84}
  85