LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "channv04.h"
  25#include "regsnv04.h"
  26
  27#include <core/client.h>
  28#include <core/ramht.h>
  29#include <subdev/instmem.h>
  30
  31#include <nvif/class.h>
  32#include <nvif/cl006b.h>
  33#include <nvif/unpack.h>
  34
  35static bool
  36nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
  37{
  38        switch (engine->subdev.index) {
  39        case NVKM_ENGINE_DMAOBJ:
  40        case NVKM_ENGINE_SW:
  41                return false;
  42        case NVKM_ENGINE_GR:
  43                *reg = 0x0032e0;
  44                *ctx = 0x38;
  45                return true;
  46        case NVKM_ENGINE_MPEG:
  47                if (engine->subdev.device->chipset < 0x44)
  48                        return false;
  49                *reg = 0x00330c;
  50                *ctx = 0x54;
  51                return true;
  52        default:
  53                WARN_ON(1);
  54                return false;
  55        }
  56}
  57
  58static int
  59nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base,
  60                          struct nvkm_engine *engine, bool suspend)
  61{
  62        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  63        struct nv04_fifo *fifo = chan->fifo;
  64        struct nvkm_device *device = fifo->base.engine.subdev.device;
  65        struct nvkm_instmem *imem = device->imem;
  66        unsigned long flags;
  67        u32 reg, ctx;
  68        int chid;
  69
  70        if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
  71                return 0;
  72
  73        spin_lock_irqsave(&fifo->base.lock, flags);
  74        nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
  75
  76        chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1);
  77        if (chid == chan->base.chid)
  78                nvkm_wr32(device, reg, 0x00000000);
  79        nvkm_kmap(imem->ramfc);
  80        nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000);
  81        nvkm_done(imem->ramfc);
  82
  83        nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
  84        spin_unlock_irqrestore(&fifo->base.lock, flags);
  85        return 0;
  86}
  87
  88static int
  89nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base,
  90                          struct nvkm_engine *engine)
  91{
  92        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  93        struct nv04_fifo *fifo = chan->fifo;
  94        struct nvkm_device *device = fifo->base.engine.subdev.device;
  95        struct nvkm_instmem *imem = device->imem;
  96        unsigned long flags;
  97        u32 inst, reg, ctx;
  98        int chid;
  99
 100        if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
 101                return 0;
 102        inst = chan->engn[engine->subdev.index]->addr >> 4;
 103
 104        spin_lock_irqsave(&fifo->base.lock, flags);
 105        nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
 106
 107        chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1);
 108        if (chid == chan->base.chid)
 109                nvkm_wr32(device, reg, inst);
 110        nvkm_kmap(imem->ramfc);
 111        nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst);
 112        nvkm_done(imem->ramfc);
 113
 114        nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
 115        spin_unlock_irqrestore(&fifo->base.lock, flags);
 116        return 0;
 117}
 118
 119static void
 120nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base,
 121                          struct nvkm_engine *engine)
 122{
 123        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 124        nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);
 125}
 126
 127static int
 128nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base,
 129                          struct nvkm_engine *engine,
 130                          struct nvkm_object *object)
 131{
 132        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 133        const int engn = engine->subdev.index;
 134        u32 reg, ctx;
 135
 136        if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
 137                return 0;
 138
 139        return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);
 140}
 141
 142static int
 143nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
 144                          struct nvkm_object *object)
 145{
 146        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 147        struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
 148        u32 context = chan->base.chid << 23;
 149        u32 handle  = object->handle;
 150        int hash;
 151
 152        switch (object->engine->subdev.index) {
 153        case NVKM_ENGINE_DMAOBJ:
 154        case NVKM_ENGINE_SW    : context |= 0x00000000; break;
 155        case NVKM_ENGINE_GR    : context |= 0x00100000; break;
 156        case NVKM_ENGINE_MPEG  : context |= 0x00200000; break;
 157        default:
 158                WARN_ON(1);
 159                return -EINVAL;
 160        }
 161
 162        mutex_lock(&chan->fifo->base.engine.subdev.mutex);
 163        hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,
 164                                 handle, context);
 165        mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
 166        return hash;
 167}
 168
 169static const struct nvkm_fifo_chan_func
 170nv40_fifo_dma_func = {
 171        .dtor = nv04_fifo_dma_dtor,
 172        .init = nv04_fifo_dma_init,
 173        .fini = nv04_fifo_dma_fini,
 174        .engine_ctor = nv40_fifo_dma_engine_ctor,
 175        .engine_dtor = nv40_fifo_dma_engine_dtor,
 176        .engine_init = nv40_fifo_dma_engine_init,
 177        .engine_fini = nv40_fifo_dma_engine_fini,
 178        .object_ctor = nv40_fifo_dma_object_ctor,
 179        .object_dtor = nv04_fifo_dma_object_dtor,
 180};
 181
 182static int
 183nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 184                  void *data, u32 size, struct nvkm_object **pobject)
 185{
 186        struct nvkm_object *parent = oclass->parent;
 187        union {
 188                struct nv03_channel_dma_v0 v0;
 189        } *args = data;
 190        struct nv04_fifo *fifo = nv04_fifo(base);
 191        struct nv04_fifo_chan *chan = NULL;
 192        struct nvkm_device *device = fifo->base.engine.subdev.device;
 193        struct nvkm_instmem *imem = device->imem;
 194        int ret = -ENOSYS;
 195
 196        nvif_ioctl(parent, "create channel dma size %d\n", size);
 197        if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 198                nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 199                                   "offset %08x\n", args->v0.version,
 200                           args->v0.pushbuf, args->v0.offset);
 201                if (!args->v0.pushbuf)
 202                        return -EINVAL;
 203        } else
 204                return ret;
 205
 206        if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 207                return -ENOMEM;
 208        *pobject = &chan->base.object;
 209
 210        ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base,
 211                                  0x1000, 0x1000, false, 0, args->v0.pushbuf,
 212                                  (1ULL << NVKM_ENGINE_DMAOBJ) |
 213                                  (1ULL << NVKM_ENGINE_GR) |
 214                                  (1ULL << NVKM_ENGINE_MPEG) |
 215                                  (1ULL << NVKM_ENGINE_SW),
 216                                  0, 0xc00000, 0x1000, oclass, &chan->base);
 217        chan->fifo = fifo;
 218        if (ret)
 219                return ret;
 220
 221        args->v0.chid = chan->base.chid;
 222        chan->ramfc = chan->base.chid * 128;
 223
 224        nvkm_kmap(imem->ramfc);
 225        nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
 226        nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
 227        nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
 228        nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 |
 229                               NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 230                               NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 231#ifdef __BIG_ENDIAN
 232                               NV_PFIFO_CACHE1_BIG_ENDIAN |
 233#endif
 234                               NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 235        nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
 236        nvkm_done(imem->ramfc);
 237        return 0;
 238}
 239
 240const struct nvkm_fifo_chan_oclass
 241nv40_fifo_dma_oclass = {
 242        .base.oclass = NV40_CHANNEL_DMA,
 243        .base.minver = 0,
 244        .base.maxver = 0,
 245        .ctor = nv40_fifo_dma_new,
 246};
 247