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16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/spi/spi.h>
19
20#include "../dss/omapdss.h"
21
22struct panel_drv_data {
23 struct omap_dss_device dssdev;
24
25 struct videomode vm;
26
27 struct backlight_device *backlight;
28
29 struct spi_device *spi_dev;
30};
31
32static const struct videomode td028ttec1_panel_vm = {
33 .hactive = 480,
34 .vactive = 640,
35 .pixelclock = 22153000,
36 .hfront_porch = 24,
37 .hsync_len = 8,
38 .hback_porch = 8,
39 .vfront_porch = 4,
40 .vsync_len = 2,
41 .vback_porch = 2,
42
43 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
44};
45
46#define JBT_COMMAND 0x000
47#define JBT_DATA 0x100
48
49static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
50{
51 int rc;
52 u16 tx_buf = JBT_COMMAND | reg;
53
54 rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
55 1*sizeof(u16));
56 if (rc != 0)
57 dev_err(&ddata->spi_dev->dev,
58 "jbt_ret_write_0 spi_write ret %d\n", rc);
59
60 return rc;
61}
62
63static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
64{
65 int rc;
66 u16 tx_buf[2];
67
68 tx_buf[0] = JBT_COMMAND | reg;
69 tx_buf[1] = JBT_DATA | data;
70 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
71 2*sizeof(u16));
72 if (rc != 0)
73 dev_err(&ddata->spi_dev->dev,
74 "jbt_reg_write_1 spi_write ret %d\n", rc);
75
76 return rc;
77}
78
79static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
80{
81 int rc;
82 u16 tx_buf[3];
83
84 tx_buf[0] = JBT_COMMAND | reg;
85 tx_buf[1] = JBT_DATA | (data >> 8);
86 tx_buf[2] = JBT_DATA | (data & 0xff);
87
88 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
89 3*sizeof(u16));
90
91 if (rc != 0)
92 dev_err(&ddata->spi_dev->dev,
93 "jbt_reg_write_2 spi_write ret %d\n", rc);
94
95 return rc;
96}
97
98enum jbt_register {
99 JBT_REG_SLEEP_IN = 0x10,
100 JBT_REG_SLEEP_OUT = 0x11,
101
102 JBT_REG_DISPLAY_OFF = 0x28,
103 JBT_REG_DISPLAY_ON = 0x29,
104
105 JBT_REG_RGB_FORMAT = 0x3a,
106 JBT_REG_QUAD_RATE = 0x3b,
107
108 JBT_REG_POWER_ON_OFF = 0xb0,
109 JBT_REG_BOOSTER_OP = 0xb1,
110 JBT_REG_BOOSTER_MODE = 0xb2,
111 JBT_REG_BOOSTER_FREQ = 0xb3,
112 JBT_REG_OPAMP_SYSCLK = 0xb4,
113 JBT_REG_VSC_VOLTAGE = 0xb5,
114 JBT_REG_VCOM_VOLTAGE = 0xb6,
115 JBT_REG_EXT_DISPL = 0xb7,
116 JBT_REG_OUTPUT_CONTROL = 0xb8,
117 JBT_REG_DCCLK_DCEV = 0xb9,
118 JBT_REG_DISPLAY_MODE1 = 0xba,
119 JBT_REG_DISPLAY_MODE2 = 0xbb,
120 JBT_REG_DISPLAY_MODE = 0xbc,
121 JBT_REG_ASW_SLEW = 0xbd,
122 JBT_REG_DUMMY_DISPLAY = 0xbe,
123 JBT_REG_DRIVE_SYSTEM = 0xbf,
124
125 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
126 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
127 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
128 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
129 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
130 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
131 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
132
133 JBT_REG_GAMMA1_FINE_1 = 0xc7,
134 JBT_REG_GAMMA1_FINE_2 = 0xc8,
135 JBT_REG_GAMMA1_INCLINATION = 0xc9,
136 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
137
138 JBT_REG_BLANK_CONTROL = 0xcf,
139 JBT_REG_BLANK_TH_TV = 0xd0,
140 JBT_REG_CKV_ON_OFF = 0xd1,
141 JBT_REG_CKV_1_2 = 0xd2,
142 JBT_REG_OEV_TIMING = 0xd3,
143 JBT_REG_ASW_TIMING_1 = 0xd4,
144 JBT_REG_ASW_TIMING_2 = 0xd5,
145
146 JBT_REG_HCLOCK_VGA = 0xec,
147 JBT_REG_HCLOCK_QVGA = 0xed,
148};
149
150#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
151
152static int td028ttec1_panel_connect(struct omap_dss_device *src,
153 struct omap_dss_device *dst)
154{
155 return 0;
156}
157
158static void td028ttec1_panel_disconnect(struct omap_dss_device *src,
159 struct omap_dss_device *dst)
160{
161}
162
163static void td028ttec1_panel_enable(struct omap_dss_device *dssdev)
164{
165 struct panel_drv_data *ddata = to_panel_data(dssdev);
166 int r = 0;
167
168 dev_dbg(dssdev->dev, "%s: state %d\n", __func__, dssdev->state);
169
170
171 r |= jbt_ret_write_0(ddata, 0x00);
172 usleep_range(1000, 2000);
173 r |= jbt_ret_write_0(ddata, 0x00);
174 usleep_range(1000, 2000);
175 r |= jbt_ret_write_0(ddata, 0x00);
176 usleep_range(1000, 2000);
177
178 if (r) {
179 dev_warn(dssdev->dev, "%s: transfer error\n", __func__);
180 return;
181 }
182
183
184 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
185
186
187 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
188
189
190 r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
191
192
193 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
194
195
196 r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
197
198
199 r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
200
201
202
203
204 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
205 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
206 r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
207 r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
208 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
209 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
210 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
211 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
212 r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
213 r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
214 r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
215 r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
216 r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
217
218
219
220
221 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
222 r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
223
224 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
225 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
226 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
227 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
228 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
229 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
230 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
231
232 r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
233 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
234 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
235 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
236
237 r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
238 r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
239 r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
240
241 r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
242 r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
243
244 r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
245 r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
246 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
247
248 r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
249
250 if (r)
251 dev_err(dssdev->dev, "%s: write error\n", __func__);
252
253 backlight_enable(ddata->backlight);
254}
255
256static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
257{
258 struct panel_drv_data *ddata = to_panel_data(dssdev);
259
260 backlight_disable(ddata->backlight);
261
262 dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
263
264 jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
265 jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
266 jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
267 jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
268}
269
270static int td028ttec1_panel_get_modes(struct omap_dss_device *dssdev,
271 struct drm_connector *connector)
272{
273 struct panel_drv_data *ddata = to_panel_data(dssdev);
274
275 return omapdss_display_get_modes(connector, &ddata->vm);
276}
277
278static const struct omap_dss_device_ops td028ttec1_ops = {
279 .connect = td028ttec1_panel_connect,
280 .disconnect = td028ttec1_panel_disconnect,
281
282 .enable = td028ttec1_panel_enable,
283 .disable = td028ttec1_panel_disable,
284
285 .get_modes = td028ttec1_panel_get_modes,
286};
287
288static int td028ttec1_panel_probe(struct spi_device *spi)
289{
290 struct panel_drv_data *ddata;
291 struct omap_dss_device *dssdev;
292 int r;
293
294 dev_dbg(&spi->dev, "%s\n", __func__);
295
296 spi->bits_per_word = 9;
297 spi->mode = SPI_MODE_3;
298
299 r = spi_setup(spi);
300 if (r < 0) {
301 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
302 return r;
303 }
304
305 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
306 if (ddata == NULL)
307 return -ENOMEM;
308
309 ddata->backlight = devm_of_find_backlight(&spi->dev);
310 if (IS_ERR(ddata->backlight))
311 return PTR_ERR(ddata->backlight);
312
313 dev_set_drvdata(&spi->dev, ddata);
314
315 ddata->spi_dev = spi;
316
317 ddata->vm = td028ttec1_panel_vm;
318
319 dssdev = &ddata->dssdev;
320 dssdev->dev = &spi->dev;
321 dssdev->ops = &td028ttec1_ops;
322 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
323 dssdev->display = true;
324 dssdev->owner = THIS_MODULE;
325 dssdev->of_ports = BIT(0);
326 dssdev->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
327
328
329
330
331
332 dssdev->bus_flags = DRM_BUS_FLAG_DE_HIGH
333 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
334 | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
335
336 omapdss_display_init(dssdev);
337 omapdss_device_register(dssdev);
338
339 return 0;
340}
341
342static int td028ttec1_panel_remove(struct spi_device *spi)
343{
344 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
345 struct omap_dss_device *dssdev = &ddata->dssdev;
346
347 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
348
349 omapdss_device_unregister(dssdev);
350
351 td028ttec1_panel_disable(dssdev);
352
353 return 0;
354}
355
356static const struct of_device_id td028ttec1_of_match[] = {
357 { .compatible = "omapdss,tpo,td028ttec1", },
358
359 { .compatible = "omapdss,toppoly,td028ttec1", },
360 {},
361};
362
363MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
364
365static const struct spi_device_id td028ttec1_ids[] = {
366 { "toppoly,td028ttec1", 0 },
367 { "tpo,td028ttec1", 0},
368 { }
369};
370
371MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
372
373
374static struct spi_driver td028ttec1_spi_driver = {
375 .probe = td028ttec1_panel_probe,
376 .remove = td028ttec1_panel_remove,
377 .id_table = td028ttec1_ids,
378
379 .driver = {
380 .name = "panel-tpo-td028ttec1",
381 .of_match_table = td028ttec1_of_match,
382 .suppress_bind_attrs = true,
383 },
384};
385
386module_spi_driver(td028ttec1_spi_driver);
387
388MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
389MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
390MODULE_LICENSE("GPL");
391
