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7#include "omap_drv.h"
8
9struct omap_irq_wait {
10 struct list_head node;
11 wait_queue_head_t wq;
12 u32 irqmask;
13 int count;
14};
15
16
17static void omap_irq_update(struct drm_device *dev)
18{
19 struct omap_drm_private *priv = dev->dev_private;
20 struct omap_irq_wait *wait;
21 u32 irqmask = priv->irq_mask;
22
23 assert_spin_locked(&priv->wait_lock);
24
25 list_for_each_entry(wait, &priv->wait_list, node)
26 irqmask |= wait->irqmask;
27
28 DBG("irqmask=%08x", irqmask);
29
30 priv->dispc_ops->write_irqenable(priv->dispc, irqmask);
31}
32
33static void omap_irq_wait_handler(struct omap_irq_wait *wait)
34{
35 wait->count--;
36 wake_up(&wait->wq);
37}
38
39struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
40 u32 irqmask, int count)
41{
42 struct omap_drm_private *priv = dev->dev_private;
43 struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
44 unsigned long flags;
45
46 init_waitqueue_head(&wait->wq);
47 wait->irqmask = irqmask;
48 wait->count = count;
49
50 spin_lock_irqsave(&priv->wait_lock, flags);
51 list_add(&wait->node, &priv->wait_list);
52 omap_irq_update(dev);
53 spin_unlock_irqrestore(&priv->wait_lock, flags);
54
55 return wait;
56}
57
58int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
59 unsigned long timeout)
60{
61 struct omap_drm_private *priv = dev->dev_private;
62 unsigned long flags;
63 int ret;
64
65 ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
66
67 spin_lock_irqsave(&priv->wait_lock, flags);
68 list_del(&wait->node);
69 omap_irq_update(dev);
70 spin_unlock_irqrestore(&priv->wait_lock, flags);
71
72 kfree(wait);
73
74 return ret == 0 ? -1 : 0;
75}
76
77int omap_irq_enable_framedone(struct drm_crtc *crtc, bool enable)
78{
79 struct drm_device *dev = crtc->dev;
80 struct omap_drm_private *priv = dev->dev_private;
81 unsigned long flags;
82 enum omap_channel channel = omap_crtc_channel(crtc);
83 int framedone_irq =
84 priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel);
85
86 DBG("dev=%p, crtc=%u, enable=%d", dev, channel, enable);
87
88 spin_lock_irqsave(&priv->wait_lock, flags);
89 if (enable)
90 priv->irq_mask |= framedone_irq;
91 else
92 priv->irq_mask &= ~framedone_irq;
93 omap_irq_update(dev);
94 spin_unlock_irqrestore(&priv->wait_lock, flags);
95
96 return 0;
97}
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111
112int omap_irq_enable_vblank(struct drm_crtc *crtc)
113{
114 struct drm_device *dev = crtc->dev;
115 struct omap_drm_private *priv = dev->dev_private;
116 unsigned long flags;
117 enum omap_channel channel = omap_crtc_channel(crtc);
118
119 DBG("dev=%p, crtc=%u", dev, channel);
120
121 spin_lock_irqsave(&priv->wait_lock, flags);
122 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
123 channel);
124 omap_irq_update(dev);
125 spin_unlock_irqrestore(&priv->wait_lock, flags);
126
127 return 0;
128}
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138
139void omap_irq_disable_vblank(struct drm_crtc *crtc)
140{
141 struct drm_device *dev = crtc->dev;
142 struct omap_drm_private *priv = dev->dev_private;
143 unsigned long flags;
144 enum omap_channel channel = omap_crtc_channel(crtc);
145
146 DBG("dev=%p, crtc=%u", dev, channel);
147
148 spin_lock_irqsave(&priv->wait_lock, flags);
149 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
150 channel);
151 omap_irq_update(dev);
152 spin_unlock_irqrestore(&priv->wait_lock, flags);
153}
154
155static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
156 u32 irqstatus)
157{
158 static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
159 DEFAULT_RATELIMIT_BURST);
160 static const struct {
161 const char *name;
162 u32 mask;
163 } sources[] = {
164 { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
165 { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
166 { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
167 { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
168 };
169
170 const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
171 | DISPC_IRQ_VID1_FIFO_UNDERFLOW
172 | DISPC_IRQ_VID2_FIFO_UNDERFLOW
173 | DISPC_IRQ_VID3_FIFO_UNDERFLOW;
174 unsigned int i;
175
176 spin_lock(&priv->wait_lock);
177 irqstatus &= priv->irq_mask & mask;
178 spin_unlock(&priv->wait_lock);
179
180 if (!irqstatus)
181 return;
182
183 if (!__ratelimit(&_rs))
184 return;
185
186 DRM_ERROR("FIFO underflow on ");
187
188 for (i = 0; i < ARRAY_SIZE(sources); ++i) {
189 if (sources[i].mask & irqstatus)
190 pr_cont("%s ", sources[i].name);
191 }
192
193 pr_cont("(0x%08x)\n", irqstatus);
194}
195
196static void omap_irq_ocp_error_handler(struct drm_device *dev,
197 u32 irqstatus)
198{
199 if (!(irqstatus & DISPC_IRQ_OCP_ERR))
200 return;
201
202 dev_err_ratelimited(dev->dev, "OCP error\n");
203}
204
205static irqreturn_t omap_irq_handler(int irq, void *arg)
206{
207 struct drm_device *dev = (struct drm_device *) arg;
208 struct omap_drm_private *priv = dev->dev_private;
209 struct omap_irq_wait *wait, *n;
210 unsigned long flags;
211 unsigned int id;
212 u32 irqstatus;
213
214 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc);
215 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus);
216 priv->dispc_ops->read_irqstatus(priv->dispc);
217
218 VERB("irqs: %08x", irqstatus);
219
220 for (id = 0; id < priv->num_pipes; id++) {
221 struct drm_crtc *crtc = priv->pipes[id].crtc;
222 enum omap_channel channel = omap_crtc_channel(crtc);
223
224 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) {
225 drm_handle_vblank(dev, id);
226 omap_crtc_vblank_irq(crtc);
227 }
228
229 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
230 omap_crtc_error_irq(crtc, irqstatus);
231
232 if (irqstatus & priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel))
233 omap_crtc_framedone_irq(crtc, irqstatus);
234 }
235
236 omap_irq_ocp_error_handler(dev, irqstatus);
237 omap_irq_fifo_underflow(priv, irqstatus);
238
239 spin_lock_irqsave(&priv->wait_lock, flags);
240 list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
241 if (wait->irqmask & irqstatus)
242 omap_irq_wait_handler(wait);
243 }
244 spin_unlock_irqrestore(&priv->wait_lock, flags);
245
246 return IRQ_HANDLED;
247}
248
249static const u32 omap_underflow_irqs[] = {
250 [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
251 [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
252 [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
253 [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
254};
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263int omap_drm_irq_install(struct drm_device *dev)
264{
265 struct omap_drm_private *priv = dev->dev_private;
266 unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
267 unsigned int max_planes;
268 unsigned int i;
269 int ret;
270
271 spin_lock_init(&priv->wait_lock);
272 INIT_LIST_HEAD(&priv->wait_list);
273
274 priv->irq_mask = DISPC_IRQ_OCP_ERR;
275
276 max_planes = min(ARRAY_SIZE(priv->planes),
277 ARRAY_SIZE(omap_underflow_irqs));
278 for (i = 0; i < max_planes; ++i) {
279 if (priv->planes[i])
280 priv->irq_mask |= omap_underflow_irqs[i];
281 }
282
283 for (i = 0; i < num_mgrs; ++i)
284 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i);
285
286 priv->dispc_ops->runtime_get(priv->dispc);
287 priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff);
288 priv->dispc_ops->runtime_put(priv->dispc);
289
290 ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev);
291 if (ret < 0)
292 return ret;
293
294 dev->irq_enabled = true;
295
296 return 0;
297}
298
299void omap_drm_irq_uninstall(struct drm_device *dev)
300{
301 struct omap_drm_private *priv = dev->dev_private;
302
303 if (!dev->irq_enabled)
304 return;
305
306 dev->irq_enabled = false;
307
308 priv->dispc_ops->free_irq(priv->dispc, dev);
309}
310