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24#include <linux/backlight.h>
25#include <linux/delay.h>
26#include <linux/gpio/consumer.h>
27#include <linux/module.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
32#include <video/display_timing.h>
33#include <video/videomode.h>
34
35#include <drm/drm_crtc.h>
36#include <drm/drm_device.h>
37#include <drm/drm_mipi_dsi.h>
38#include <drm/drm_panel.h>
39
40struct panel_desc {
41 const struct drm_display_mode *modes;
42 unsigned int num_modes;
43 const struct display_timing *timings;
44 unsigned int num_timings;
45
46 unsigned int bpc;
47
48
49
50
51
52 struct {
53 unsigned int width;
54 unsigned int height;
55 } size;
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70 struct {
71 unsigned int prepare;
72 unsigned int hpd_absent_delay;
73 unsigned int enable;
74 unsigned int disable;
75 unsigned int unprepare;
76 } delay;
77
78 u32 bus_format;
79 u32 bus_flags;
80};
81
82struct panel_simple {
83 struct drm_panel base;
84 bool prepared;
85 bool enabled;
86 bool no_hpd;
87
88 const struct panel_desc *desc;
89
90 struct backlight_device *backlight;
91 struct regulator *supply;
92 struct i2c_adapter *ddc;
93
94 struct gpio_desc *enable_gpio;
95};
96
97static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
98{
99 return container_of(panel, struct panel_simple, base);
100}
101
102static int panel_simple_get_fixed_modes(struct panel_simple *panel)
103{
104 struct drm_connector *connector = panel->base.connector;
105 struct drm_device *drm = panel->base.drm;
106 struct drm_display_mode *mode;
107 unsigned int i, num = 0;
108
109 if (!panel->desc)
110 return 0;
111
112 for (i = 0; i < panel->desc->num_timings; i++) {
113 const struct display_timing *dt = &panel->desc->timings[i];
114 struct videomode vm;
115
116 videomode_from_timing(dt, &vm);
117 mode = drm_mode_create(drm);
118 if (!mode) {
119 dev_err(drm->dev, "failed to add mode %ux%u\n",
120 dt->hactive.typ, dt->vactive.typ);
121 continue;
122 }
123
124 drm_display_mode_from_videomode(&vm, mode);
125
126 mode->type |= DRM_MODE_TYPE_DRIVER;
127
128 if (panel->desc->num_timings == 1)
129 mode->type |= DRM_MODE_TYPE_PREFERRED;
130
131 drm_mode_probed_add(connector, mode);
132 num++;
133 }
134
135 for (i = 0; i < panel->desc->num_modes; i++) {
136 const struct drm_display_mode *m = &panel->desc->modes[i];
137
138 mode = drm_mode_duplicate(drm, m);
139 if (!mode) {
140 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
141 m->hdisplay, m->vdisplay, m->vrefresh);
142 continue;
143 }
144
145 mode->type |= DRM_MODE_TYPE_DRIVER;
146
147 if (panel->desc->num_modes == 1)
148 mode->type |= DRM_MODE_TYPE_PREFERRED;
149
150 drm_mode_set_name(mode);
151
152 drm_mode_probed_add(connector, mode);
153 num++;
154 }
155
156 connector->display_info.bpc = panel->desc->bpc;
157 connector->display_info.width_mm = panel->desc->size.width;
158 connector->display_info.height_mm = panel->desc->size.height;
159 if (panel->desc->bus_format)
160 drm_display_info_set_bus_formats(&connector->display_info,
161 &panel->desc->bus_format, 1);
162 connector->display_info.bus_flags = panel->desc->bus_flags;
163
164 return num;
165}
166
167static int panel_simple_disable(struct drm_panel *panel)
168{
169 struct panel_simple *p = to_panel_simple(panel);
170
171 if (!p->enabled)
172 return 0;
173
174 if (p->backlight) {
175 p->backlight->props.power = FB_BLANK_POWERDOWN;
176 p->backlight->props.state |= BL_CORE_FBBLANK;
177 backlight_update_status(p->backlight);
178 }
179
180 if (p->desc->delay.disable)
181 msleep(p->desc->delay.disable);
182
183 p->enabled = false;
184
185 return 0;
186}
187
188static int panel_simple_unprepare(struct drm_panel *panel)
189{
190 struct panel_simple *p = to_panel_simple(panel);
191
192 if (!p->prepared)
193 return 0;
194
195 gpiod_set_value_cansleep(p->enable_gpio, 0);
196
197 regulator_disable(p->supply);
198
199 if (p->desc->delay.unprepare)
200 msleep(p->desc->delay.unprepare);
201
202 p->prepared = false;
203
204 return 0;
205}
206
207static int panel_simple_prepare(struct drm_panel *panel)
208{
209 struct panel_simple *p = to_panel_simple(panel);
210 unsigned int delay;
211 int err;
212
213 if (p->prepared)
214 return 0;
215
216 err = regulator_enable(p->supply);
217 if (err < 0) {
218 dev_err(panel->dev, "failed to enable supply: %d\n", err);
219 return err;
220 }
221
222 gpiod_set_value_cansleep(p->enable_gpio, 1);
223
224 delay = p->desc->delay.prepare;
225 if (p->no_hpd)
226 delay += p->desc->delay.hpd_absent_delay;
227 if (delay)
228 msleep(delay);
229
230 p->prepared = true;
231
232 return 0;
233}
234
235static int panel_simple_enable(struct drm_panel *panel)
236{
237 struct panel_simple *p = to_panel_simple(panel);
238
239 if (p->enabled)
240 return 0;
241
242 if (p->desc->delay.enable)
243 msleep(p->desc->delay.enable);
244
245 if (p->backlight) {
246 p->backlight->props.state &= ~BL_CORE_FBBLANK;
247 p->backlight->props.power = FB_BLANK_UNBLANK;
248 backlight_update_status(p->backlight);
249 }
250
251 p->enabled = true;
252
253 return 0;
254}
255
256static int panel_simple_get_modes(struct drm_panel *panel)
257{
258 struct panel_simple *p = to_panel_simple(panel);
259 int num = 0;
260
261
262 if (p->ddc) {
263 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
264 drm_connector_update_edid_property(panel->connector, edid);
265 if (edid) {
266 num += drm_add_edid_modes(panel->connector, edid);
267 kfree(edid);
268 }
269 }
270
271
272 num += panel_simple_get_fixed_modes(p);
273
274 return num;
275}
276
277static int panel_simple_get_timings(struct drm_panel *panel,
278 unsigned int num_timings,
279 struct display_timing *timings)
280{
281 struct panel_simple *p = to_panel_simple(panel);
282 unsigned int i;
283
284 if (p->desc->num_timings < num_timings)
285 num_timings = p->desc->num_timings;
286
287 if (timings)
288 for (i = 0; i < num_timings; i++)
289 timings[i] = p->desc->timings[i];
290
291 return p->desc->num_timings;
292}
293
294static const struct drm_panel_funcs panel_simple_funcs = {
295 .disable = panel_simple_disable,
296 .unprepare = panel_simple_unprepare,
297 .prepare = panel_simple_prepare,
298 .enable = panel_simple_enable,
299 .get_modes = panel_simple_get_modes,
300 .get_timings = panel_simple_get_timings,
301};
302
303static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
304{
305 struct device_node *backlight, *ddc;
306 struct panel_simple *panel;
307 int err;
308
309 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
310 if (!panel)
311 return -ENOMEM;
312
313 panel->enabled = false;
314 panel->prepared = false;
315 panel->desc = desc;
316
317 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
318
319 panel->supply = devm_regulator_get(dev, "power");
320 if (IS_ERR(panel->supply))
321 return PTR_ERR(panel->supply);
322
323 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
324 GPIOD_OUT_LOW);
325 if (IS_ERR(panel->enable_gpio)) {
326 err = PTR_ERR(panel->enable_gpio);
327 if (err != -EPROBE_DEFER)
328 dev_err(dev, "failed to request GPIO: %d\n", err);
329 return err;
330 }
331
332 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
333 if (backlight) {
334 panel->backlight = of_find_backlight_by_node(backlight);
335 of_node_put(backlight);
336
337 if (!panel->backlight)
338 return -EPROBE_DEFER;
339 }
340
341 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
342 if (ddc) {
343 panel->ddc = of_find_i2c_adapter_by_node(ddc);
344 of_node_put(ddc);
345
346 if (!panel->ddc) {
347 err = -EPROBE_DEFER;
348 goto free_backlight;
349 }
350 }
351
352 drm_panel_init(&panel->base);
353 panel->base.dev = dev;
354 panel->base.funcs = &panel_simple_funcs;
355
356 err = drm_panel_add(&panel->base);
357 if (err < 0)
358 goto free_ddc;
359
360 dev_set_drvdata(dev, panel);
361
362 return 0;
363
364free_ddc:
365 if (panel->ddc)
366 put_device(&panel->ddc->dev);
367free_backlight:
368 if (panel->backlight)
369 put_device(&panel->backlight->dev);
370
371 return err;
372}
373
374static int panel_simple_remove(struct device *dev)
375{
376 struct panel_simple *panel = dev_get_drvdata(dev);
377
378 drm_panel_remove(&panel->base);
379
380 panel_simple_disable(&panel->base);
381 panel_simple_unprepare(&panel->base);
382
383 if (panel->ddc)
384 put_device(&panel->ddc->dev);
385
386 if (panel->backlight)
387 put_device(&panel->backlight->dev);
388
389 return 0;
390}
391
392static void panel_simple_shutdown(struct device *dev)
393{
394 struct panel_simple *panel = dev_get_drvdata(dev);
395
396 panel_simple_disable(&panel->base);
397 panel_simple_unprepare(&panel->base);
398}
399
400static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
401 .clock = 9000,
402 .hdisplay = 480,
403 .hsync_start = 480 + 2,
404 .hsync_end = 480 + 2 + 41,
405 .htotal = 480 + 2 + 41 + 2,
406 .vdisplay = 272,
407 .vsync_start = 272 + 2,
408 .vsync_end = 272 + 2 + 10,
409 .vtotal = 272 + 2 + 10 + 2,
410 .vrefresh = 60,
411 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
412};
413
414static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
415 .modes = &ire_am_480272h3tmqw_t01h_mode,
416 .num_modes = 1,
417 .bpc = 8,
418 .size = {
419 .width = 105,
420 .height = 67,
421 },
422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
423};
424
425static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
426 .clock = 33333,
427 .hdisplay = 800,
428 .hsync_start = 800 + 0,
429 .hsync_end = 800 + 0 + 255,
430 .htotal = 800 + 0 + 255 + 0,
431 .vdisplay = 480,
432 .vsync_start = 480 + 2,
433 .vsync_end = 480 + 2 + 45,
434 .vtotal = 480 + 2 + 45 + 0,
435 .vrefresh = 60,
436 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
437};
438
439static const struct panel_desc ampire_am800480r3tmqwa1h = {
440 .modes = &ire_am800480r3tmqwa1h_mode,
441 .num_modes = 1,
442 .bpc = 6,
443 .size = {
444 .width = 152,
445 .height = 91,
446 },
447 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
448};
449
450static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
451 .pixelclock = { 26400000, 33300000, 46800000 },
452 .hactive = { 800, 800, 800 },
453 .hfront_porch = { 16, 210, 354 },
454 .hback_porch = { 45, 36, 6 },
455 .hsync_len = { 1, 10, 40 },
456 .vactive = { 480, 480, 480 },
457 .vfront_porch = { 7, 22, 147 },
458 .vback_porch = { 22, 13, 3 },
459 .vsync_len = { 1, 10, 20 },
460 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
461 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
462};
463
464static const struct panel_desc armadeus_st0700_adapt = {
465 .timings = &santek_st0700i5y_rbslw_f_timing,
466 .num_timings = 1,
467 .bpc = 6,
468 .size = {
469 .width = 154,
470 .height = 86,
471 },
472 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
473 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
474};
475
476static const struct drm_display_mode auo_b101aw03_mode = {
477 .clock = 51450,
478 .hdisplay = 1024,
479 .hsync_start = 1024 + 156,
480 .hsync_end = 1024 + 156 + 8,
481 .htotal = 1024 + 156 + 8 + 156,
482 .vdisplay = 600,
483 .vsync_start = 600 + 16,
484 .vsync_end = 600 + 16 + 6,
485 .vtotal = 600 + 16 + 6 + 16,
486 .vrefresh = 60,
487};
488
489static const struct panel_desc auo_b101aw03 = {
490 .modes = &auo_b101aw03_mode,
491 .num_modes = 1,
492 .bpc = 6,
493 .size = {
494 .width = 223,
495 .height = 125,
496 },
497};
498
499static const struct drm_display_mode auo_b101ean01_mode = {
500 .clock = 72500,
501 .hdisplay = 1280,
502 .hsync_start = 1280 + 119,
503 .hsync_end = 1280 + 119 + 32,
504 .htotal = 1280 + 119 + 32 + 21,
505 .vdisplay = 800,
506 .vsync_start = 800 + 4,
507 .vsync_end = 800 + 4 + 20,
508 .vtotal = 800 + 4 + 20 + 8,
509 .vrefresh = 60,
510};
511
512static const struct panel_desc auo_b101ean01 = {
513 .modes = &auo_b101ean01_mode,
514 .num_modes = 1,
515 .bpc = 6,
516 .size = {
517 .width = 217,
518 .height = 136,
519 },
520};
521
522static const struct drm_display_mode auo_b101xtn01_mode = {
523 .clock = 72000,
524 .hdisplay = 1366,
525 .hsync_start = 1366 + 20,
526 .hsync_end = 1366 + 20 + 70,
527 .htotal = 1366 + 20 + 70,
528 .vdisplay = 768,
529 .vsync_start = 768 + 14,
530 .vsync_end = 768 + 14 + 42,
531 .vtotal = 768 + 14 + 42,
532 .vrefresh = 60,
533 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
534};
535
536static const struct panel_desc auo_b101xtn01 = {
537 .modes = &auo_b101xtn01_mode,
538 .num_modes = 1,
539 .bpc = 6,
540 .size = {
541 .width = 223,
542 .height = 125,
543 },
544};
545
546static const struct drm_display_mode auo_b116xw03_mode = {
547 .clock = 70589,
548 .hdisplay = 1366,
549 .hsync_start = 1366 + 40,
550 .hsync_end = 1366 + 40 + 40,
551 .htotal = 1366 + 40 + 40 + 32,
552 .vdisplay = 768,
553 .vsync_start = 768 + 10,
554 .vsync_end = 768 + 10 + 12,
555 .vtotal = 768 + 10 + 12 + 6,
556 .vrefresh = 60,
557};
558
559static const struct panel_desc auo_b116xw03 = {
560 .modes = &auo_b116xw03_mode,
561 .num_modes = 1,
562 .bpc = 6,
563 .size = {
564 .width = 256,
565 .height = 144,
566 },
567};
568
569static const struct drm_display_mode auo_b133xtn01_mode = {
570 .clock = 69500,
571 .hdisplay = 1366,
572 .hsync_start = 1366 + 48,
573 .hsync_end = 1366 + 48 + 32,
574 .htotal = 1366 + 48 + 32 + 20,
575 .vdisplay = 768,
576 .vsync_start = 768 + 3,
577 .vsync_end = 768 + 3 + 6,
578 .vtotal = 768 + 3 + 6 + 13,
579 .vrefresh = 60,
580};
581
582static const struct panel_desc auo_b133xtn01 = {
583 .modes = &auo_b133xtn01_mode,
584 .num_modes = 1,
585 .bpc = 6,
586 .size = {
587 .width = 293,
588 .height = 165,
589 },
590};
591
592static const struct drm_display_mode auo_b133htn01_mode = {
593 .clock = 150660,
594 .hdisplay = 1920,
595 .hsync_start = 1920 + 172,
596 .hsync_end = 1920 + 172 + 80,
597 .htotal = 1920 + 172 + 80 + 60,
598 .vdisplay = 1080,
599 .vsync_start = 1080 + 25,
600 .vsync_end = 1080 + 25 + 10,
601 .vtotal = 1080 + 25 + 10 + 10,
602 .vrefresh = 60,
603};
604
605static const struct panel_desc auo_b133htn01 = {
606 .modes = &auo_b133htn01_mode,
607 .num_modes = 1,
608 .bpc = 6,
609 .size = {
610 .width = 293,
611 .height = 165,
612 },
613 .delay = {
614 .prepare = 105,
615 .enable = 20,
616 .unprepare = 50,
617 },
618};
619
620static const struct display_timing auo_g070vvn01_timings = {
621 .pixelclock = { 33300000, 34209000, 45000000 },
622 .hactive = { 800, 800, 800 },
623 .hfront_porch = { 20, 40, 200 },
624 .hback_porch = { 87, 40, 1 },
625 .hsync_len = { 1, 48, 87 },
626 .vactive = { 480, 480, 480 },
627 .vfront_porch = { 5, 13, 200 },
628 .vback_porch = { 31, 31, 29 },
629 .vsync_len = { 1, 1, 3 },
630};
631
632static const struct panel_desc auo_g070vvn01 = {
633 .timings = &auo_g070vvn01_timings,
634 .num_timings = 1,
635 .bpc = 8,
636 .size = {
637 .width = 152,
638 .height = 91,
639 },
640 .delay = {
641 .prepare = 200,
642 .enable = 50,
643 .disable = 50,
644 .unprepare = 1000,
645 },
646};
647
648static const struct drm_display_mode auo_g101evn010_mode = {
649 .clock = 68930,
650 .hdisplay = 1280,
651 .hsync_start = 1280 + 82,
652 .hsync_end = 1280 + 82 + 2,
653 .htotal = 1280 + 82 + 2 + 84,
654 .vdisplay = 800,
655 .vsync_start = 800 + 8,
656 .vsync_end = 800 + 8 + 2,
657 .vtotal = 800 + 8 + 2 + 6,
658 .vrefresh = 60,
659};
660
661static const struct panel_desc auo_g101evn010 = {
662 .modes = &auo_g101evn010_mode,
663 .num_modes = 1,
664 .bpc = 6,
665 .size = {
666 .width = 216,
667 .height = 135,
668 },
669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
670};
671
672static const struct drm_display_mode auo_g104sn02_mode = {
673 .clock = 40000,
674 .hdisplay = 800,
675 .hsync_start = 800 + 40,
676 .hsync_end = 800 + 40 + 216,
677 .htotal = 800 + 40 + 216 + 128,
678 .vdisplay = 600,
679 .vsync_start = 600 + 10,
680 .vsync_end = 600 + 10 + 35,
681 .vtotal = 600 + 10 + 35 + 2,
682 .vrefresh = 60,
683};
684
685static const struct panel_desc auo_g104sn02 = {
686 .modes = &auo_g104sn02_mode,
687 .num_modes = 1,
688 .bpc = 8,
689 .size = {
690 .width = 211,
691 .height = 158,
692 },
693};
694
695static const struct display_timing auo_g133han01_timings = {
696 .pixelclock = { 134000000, 141200000, 149000000 },
697 .hactive = { 1920, 1920, 1920 },
698 .hfront_porch = { 39, 58, 77 },
699 .hback_porch = { 59, 88, 117 },
700 .hsync_len = { 28, 42, 56 },
701 .vactive = { 1080, 1080, 1080 },
702 .vfront_porch = { 3, 8, 11 },
703 .vback_porch = { 5, 14, 19 },
704 .vsync_len = { 4, 14, 19 },
705};
706
707static const struct panel_desc auo_g133han01 = {
708 .timings = &auo_g133han01_timings,
709 .num_timings = 1,
710 .bpc = 8,
711 .size = {
712 .width = 293,
713 .height = 165,
714 },
715 .delay = {
716 .prepare = 200,
717 .enable = 50,
718 .disable = 50,
719 .unprepare = 1000,
720 },
721 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
722};
723
724static const struct display_timing auo_g185han01_timings = {
725 .pixelclock = { 120000000, 144000000, 175000000 },
726 .hactive = { 1920, 1920, 1920 },
727 .hfront_porch = { 18, 60, 74 },
728 .hback_porch = { 12, 44, 54 },
729 .hsync_len = { 10, 24, 32 },
730 .vactive = { 1080, 1080, 1080 },
731 .vfront_porch = { 6, 10, 40 },
732 .vback_porch = { 2, 5, 20 },
733 .vsync_len = { 2, 5, 20 },
734};
735
736static const struct panel_desc auo_g185han01 = {
737 .timings = &auo_g185han01_timings,
738 .num_timings = 1,
739 .bpc = 8,
740 .size = {
741 .width = 409,
742 .height = 230,
743 },
744 .delay = {
745 .prepare = 50,
746 .enable = 200,
747 .disable = 110,
748 .unprepare = 1000,
749 },
750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
751};
752
753static const struct display_timing auo_p320hvn03_timings = {
754 .pixelclock = { 106000000, 148500000, 164000000 },
755 .hactive = { 1920, 1920, 1920 },
756 .hfront_porch = { 25, 50, 130 },
757 .hback_porch = { 25, 50, 130 },
758 .hsync_len = { 20, 40, 105 },
759 .vactive = { 1080, 1080, 1080 },
760 .vfront_porch = { 8, 17, 150 },
761 .vback_porch = { 8, 17, 150 },
762 .vsync_len = { 4, 11, 100 },
763};
764
765static const struct panel_desc auo_p320hvn03 = {
766 .timings = &auo_p320hvn03_timings,
767 .num_timings = 1,
768 .bpc = 8,
769 .size = {
770 .width = 698,
771 .height = 393,
772 },
773 .delay = {
774 .prepare = 1,
775 .enable = 450,
776 .unprepare = 500,
777 },
778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
779};
780
781static const struct drm_display_mode auo_t215hvn01_mode = {
782 .clock = 148800,
783 .hdisplay = 1920,
784 .hsync_start = 1920 + 88,
785 .hsync_end = 1920 + 88 + 44,
786 .htotal = 1920 + 88 + 44 + 148,
787 .vdisplay = 1080,
788 .vsync_start = 1080 + 4,
789 .vsync_end = 1080 + 4 + 5,
790 .vtotal = 1080 + 4 + 5 + 36,
791 .vrefresh = 60,
792};
793
794static const struct panel_desc auo_t215hvn01 = {
795 .modes = &auo_t215hvn01_mode,
796 .num_modes = 1,
797 .bpc = 8,
798 .size = {
799 .width = 430,
800 .height = 270,
801 },
802 .delay = {
803 .disable = 5,
804 .unprepare = 1000,
805 }
806};
807
808static const struct drm_display_mode avic_tm070ddh03_mode = {
809 .clock = 51200,
810 .hdisplay = 1024,
811 .hsync_start = 1024 + 160,
812 .hsync_end = 1024 + 160 + 4,
813 .htotal = 1024 + 160 + 4 + 156,
814 .vdisplay = 600,
815 .vsync_start = 600 + 17,
816 .vsync_end = 600 + 17 + 1,
817 .vtotal = 600 + 17 + 1 + 17,
818 .vrefresh = 60,
819};
820
821static const struct panel_desc avic_tm070ddh03 = {
822 .modes = &avic_tm070ddh03_mode,
823 .num_modes = 1,
824 .bpc = 8,
825 .size = {
826 .width = 154,
827 .height = 90,
828 },
829 .delay = {
830 .prepare = 20,
831 .enable = 200,
832 .disable = 200,
833 },
834};
835
836static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
837 .clock = 30000,
838 .hdisplay = 800,
839 .hsync_start = 800 + 40,
840 .hsync_end = 800 + 40 + 48,
841 .htotal = 800 + 40 + 48 + 40,
842 .vdisplay = 480,
843 .vsync_start = 480 + 13,
844 .vsync_end = 480 + 13 + 3,
845 .vtotal = 480 + 13 + 3 + 29,
846};
847
848static const struct panel_desc bananapi_s070wv20_ct16 = {
849 .modes = &bananapi_s070wv20_ct16_mode,
850 .num_modes = 1,
851 .bpc = 6,
852 .size = {
853 .width = 154,
854 .height = 86,
855 },
856};
857
858static const struct drm_display_mode boe_hv070wsa_mode = {
859 .clock = 42105,
860 .hdisplay = 1024,
861 .hsync_start = 1024 + 30,
862 .hsync_end = 1024 + 30 + 30,
863 .htotal = 1024 + 30 + 30 + 30,
864 .vdisplay = 600,
865 .vsync_start = 600 + 10,
866 .vsync_end = 600 + 10 + 10,
867 .vtotal = 600 + 10 + 10 + 10,
868 .vrefresh = 60,
869};
870
871static const struct panel_desc boe_hv070wsa = {
872 .modes = &boe_hv070wsa_mode,
873 .num_modes = 1,
874 .size = {
875 .width = 154,
876 .height = 90,
877 },
878};
879
880static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
881 {
882 .clock = 71900,
883 .hdisplay = 1280,
884 .hsync_start = 1280 + 48,
885 .hsync_end = 1280 + 48 + 32,
886 .htotal = 1280 + 48 + 32 + 80,
887 .vdisplay = 800,
888 .vsync_start = 800 + 3,
889 .vsync_end = 800 + 3 + 5,
890 .vtotal = 800 + 3 + 5 + 24,
891 .vrefresh = 60,
892 },
893 {
894 .clock = 57500,
895 .hdisplay = 1280,
896 .hsync_start = 1280 + 48,
897 .hsync_end = 1280 + 48 + 32,
898 .htotal = 1280 + 48 + 32 + 80,
899 .vdisplay = 800,
900 .vsync_start = 800 + 3,
901 .vsync_end = 800 + 3 + 5,
902 .vtotal = 800 + 3 + 5 + 24,
903 .vrefresh = 48,
904 },
905};
906
907static const struct panel_desc boe_nv101wxmn51 = {
908 .modes = boe_nv101wxmn51_modes,
909 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
910 .bpc = 8,
911 .size = {
912 .width = 217,
913 .height = 136,
914 },
915 .delay = {
916 .prepare = 210,
917 .enable = 50,
918 .unprepare = 160,
919 },
920};
921
922static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
923 .clock = 9000,
924 .hdisplay = 480,
925 .hsync_start = 480 + 5,
926 .hsync_end = 480 + 5 + 5,
927 .htotal = 480 + 5 + 5 + 40,
928 .vdisplay = 272,
929 .vsync_start = 272 + 8,
930 .vsync_end = 272 + 8 + 8,
931 .vtotal = 272 + 8 + 8 + 8,
932 .vrefresh = 60,
933 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
934};
935
936static const struct panel_desc cdtech_s043wq26h_ct7 = {
937 .modes = &cdtech_s043wq26h_ct7_mode,
938 .num_modes = 1,
939 .bpc = 8,
940 .size = {
941 .width = 95,
942 .height = 54,
943 },
944 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
945};
946
947static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
948 .clock = 35000,
949 .hdisplay = 800,
950 .hsync_start = 800 + 40,
951 .hsync_end = 800 + 40 + 40,
952 .htotal = 800 + 40 + 40 + 48,
953 .vdisplay = 480,
954 .vsync_start = 480 + 29,
955 .vsync_end = 480 + 29 + 13,
956 .vtotal = 480 + 29 + 13 + 3,
957 .vrefresh = 60,
958 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
959};
960
961static const struct panel_desc cdtech_s070wv95_ct16 = {
962 .modes = &cdtech_s070wv95_ct16_mode,
963 .num_modes = 1,
964 .bpc = 8,
965 .size = {
966 .width = 154,
967 .height = 85,
968 },
969};
970
971static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
972 .clock = 66770,
973 .hdisplay = 800,
974 .hsync_start = 800 + 49,
975 .hsync_end = 800 + 49 + 33,
976 .htotal = 800 + 49 + 33 + 17,
977 .vdisplay = 1280,
978 .vsync_start = 1280 + 1,
979 .vsync_end = 1280 + 1 + 7,
980 .vtotal = 1280 + 1 + 7 + 15,
981 .vrefresh = 60,
982 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
983};
984
985static const struct panel_desc chunghwa_claa070wp03xg = {
986 .modes = &chunghwa_claa070wp03xg_mode,
987 .num_modes = 1,
988 .bpc = 6,
989 .size = {
990 .width = 94,
991 .height = 150,
992 },
993};
994
995static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
996 .clock = 72070,
997 .hdisplay = 1366,
998 .hsync_start = 1366 + 58,
999 .hsync_end = 1366 + 58 + 58,
1000 .htotal = 1366 + 58 + 58 + 58,
1001 .vdisplay = 768,
1002 .vsync_start = 768 + 4,
1003 .vsync_end = 768 + 4 + 4,
1004 .vtotal = 768 + 4 + 4 + 4,
1005 .vrefresh = 60,
1006};
1007
1008static const struct panel_desc chunghwa_claa101wa01a = {
1009 .modes = &chunghwa_claa101wa01a_mode,
1010 .num_modes = 1,
1011 .bpc = 6,
1012 .size = {
1013 .width = 220,
1014 .height = 120,
1015 },
1016};
1017
1018static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1019 .clock = 69300,
1020 .hdisplay = 1366,
1021 .hsync_start = 1366 + 48,
1022 .hsync_end = 1366 + 48 + 32,
1023 .htotal = 1366 + 48 + 32 + 20,
1024 .vdisplay = 768,
1025 .vsync_start = 768 + 16,
1026 .vsync_end = 768 + 16 + 8,
1027 .vtotal = 768 + 16 + 8 + 16,
1028 .vrefresh = 60,
1029};
1030
1031static const struct panel_desc chunghwa_claa101wb01 = {
1032 .modes = &chunghwa_claa101wb01_mode,
1033 .num_modes = 1,
1034 .bpc = 6,
1035 .size = {
1036 .width = 223,
1037 .height = 125,
1038 },
1039};
1040
1041static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1042 .clock = 33260,
1043 .hdisplay = 800,
1044 .hsync_start = 800 + 40,
1045 .hsync_end = 800 + 40 + 128,
1046 .htotal = 800 + 40 + 128 + 88,
1047 .vdisplay = 480,
1048 .vsync_start = 480 + 10,
1049 .vsync_end = 480 + 10 + 2,
1050 .vtotal = 480 + 10 + 2 + 33,
1051 .vrefresh = 60,
1052 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1053};
1054
1055static const struct panel_desc dataimage_scf0700c48ggu18 = {
1056 .modes = &dataimage_scf0700c48ggu18_mode,
1057 .num_modes = 1,
1058 .bpc = 8,
1059 .size = {
1060 .width = 152,
1061 .height = 91,
1062 },
1063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1064 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1065};
1066
1067static const struct display_timing dlc_dlc0700yzg_1_timing = {
1068 .pixelclock = { 45000000, 51200000, 57000000 },
1069 .hactive = { 1024, 1024, 1024 },
1070 .hfront_porch = { 100, 106, 113 },
1071 .hback_porch = { 100, 106, 113 },
1072 .hsync_len = { 100, 108, 114 },
1073 .vactive = { 600, 600, 600 },
1074 .vfront_porch = { 8, 11, 15 },
1075 .vback_porch = { 8, 11, 15 },
1076 .vsync_len = { 9, 13, 15 },
1077 .flags = DISPLAY_FLAGS_DE_HIGH,
1078};
1079
1080static const struct panel_desc dlc_dlc0700yzg_1 = {
1081 .timings = &dlc_dlc0700yzg_1_timing,
1082 .num_timings = 1,
1083 .bpc = 6,
1084 .size = {
1085 .width = 154,
1086 .height = 86,
1087 },
1088 .delay = {
1089 .prepare = 30,
1090 .enable = 200,
1091 .disable = 200,
1092 },
1093 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1094};
1095
1096static const struct display_timing dlc_dlc1010gig_timing = {
1097 .pixelclock = { 68900000, 71100000, 73400000 },
1098 .hactive = { 1280, 1280, 1280 },
1099 .hfront_porch = { 43, 53, 63 },
1100 .hback_porch = { 43, 53, 63 },
1101 .hsync_len = { 44, 54, 64 },
1102 .vactive = { 800, 800, 800 },
1103 .vfront_porch = { 5, 8, 11 },
1104 .vback_porch = { 5, 8, 11 },
1105 .vsync_len = { 5, 7, 11 },
1106 .flags = DISPLAY_FLAGS_DE_HIGH,
1107};
1108
1109static const struct panel_desc dlc_dlc1010gig = {
1110 .timings = &dlc_dlc1010gig_timing,
1111 .num_timings = 1,
1112 .bpc = 8,
1113 .size = {
1114 .width = 216,
1115 .height = 135,
1116 },
1117 .delay = {
1118 .prepare = 60,
1119 .enable = 150,
1120 .disable = 100,
1121 .unprepare = 60,
1122 },
1123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1124};
1125
1126static const struct drm_display_mode edt_et035012dm6_mode = {
1127 .clock = 6500,
1128 .hdisplay = 320,
1129 .hsync_start = 320 + 20,
1130 .hsync_end = 320 + 20 + 30,
1131 .htotal = 320 + 20 + 68,
1132 .vdisplay = 240,
1133 .vsync_start = 240 + 4,
1134 .vsync_end = 240 + 4 + 4,
1135 .vtotal = 240 + 4 + 4 + 14,
1136 .vrefresh = 60,
1137 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1138};
1139
1140static const struct panel_desc edt_et035012dm6 = {
1141 .modes = &edt_et035012dm6_mode,
1142 .num_modes = 1,
1143 .bpc = 8,
1144 .size = {
1145 .width = 70,
1146 .height = 52,
1147 },
1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1149 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1150};
1151
1152static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1153 .clock = 9000,
1154 .hdisplay = 480,
1155 .hsync_start = 480 + 2,
1156 .hsync_end = 480 + 2 + 41,
1157 .htotal = 480 + 2 + 41 + 2,
1158 .vdisplay = 272,
1159 .vsync_start = 272 + 2,
1160 .vsync_end = 272 + 2 + 10,
1161 .vtotal = 272 + 2 + 10 + 2,
1162 .vrefresh = 60,
1163 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1164};
1165
1166static const struct panel_desc edt_etm0430g0dh6 = {
1167 .modes = &edt_etm0430g0dh6_mode,
1168 .num_modes = 1,
1169 .bpc = 6,
1170 .size = {
1171 .width = 95,
1172 .height = 54,
1173 },
1174};
1175
1176static const struct drm_display_mode edt_et057090dhu_mode = {
1177 .clock = 25175,
1178 .hdisplay = 640,
1179 .hsync_start = 640 + 16,
1180 .hsync_end = 640 + 16 + 30,
1181 .htotal = 640 + 16 + 30 + 114,
1182 .vdisplay = 480,
1183 .vsync_start = 480 + 10,
1184 .vsync_end = 480 + 10 + 3,
1185 .vtotal = 480 + 10 + 3 + 32,
1186 .vrefresh = 60,
1187 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1188};
1189
1190static const struct panel_desc edt_et057090dhu = {
1191 .modes = &edt_et057090dhu_mode,
1192 .num_modes = 1,
1193 .bpc = 6,
1194 .size = {
1195 .width = 115,
1196 .height = 86,
1197 },
1198 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1199 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1200};
1201
1202static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1203 .clock = 33260,
1204 .hdisplay = 800,
1205 .hsync_start = 800 + 40,
1206 .hsync_end = 800 + 40 + 128,
1207 .htotal = 800 + 40 + 128 + 88,
1208 .vdisplay = 480,
1209 .vsync_start = 480 + 10,
1210 .vsync_end = 480 + 10 + 2,
1211 .vtotal = 480 + 10 + 2 + 33,
1212 .vrefresh = 60,
1213 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1214};
1215
1216static const struct panel_desc edt_etm0700g0dh6 = {
1217 .modes = &edt_etm0700g0dh6_mode,
1218 .num_modes = 1,
1219 .bpc = 6,
1220 .size = {
1221 .width = 152,
1222 .height = 91,
1223 },
1224 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1225 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1226};
1227
1228static const struct panel_desc edt_etm0700g0bdh6 = {
1229 .modes = &edt_etm0700g0dh6_mode,
1230 .num_modes = 1,
1231 .bpc = 6,
1232 .size = {
1233 .width = 152,
1234 .height = 91,
1235 },
1236 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1237 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1238};
1239
1240static const struct display_timing evervision_vgg804821_timing = {
1241 .pixelclock = { 27600000, 33300000, 50000000 },
1242 .hactive = { 800, 800, 800 },
1243 .hfront_porch = { 40, 66, 70 },
1244 .hback_porch = { 40, 67, 70 },
1245 .hsync_len = { 40, 67, 70 },
1246 .vactive = { 480, 480, 480 },
1247 .vfront_porch = { 6, 10, 10 },
1248 .vback_porch = { 7, 11, 11 },
1249 .vsync_len = { 7, 11, 11 },
1250 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1251 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1252 DISPLAY_FLAGS_SYNC_NEGEDGE,
1253};
1254
1255static const struct panel_desc evervision_vgg804821 = {
1256 .timings = &evervision_vgg804821_timing,
1257 .num_timings = 1,
1258 .bpc = 8,
1259 .size = {
1260 .width = 108,
1261 .height = 64,
1262 },
1263 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1264 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1265};
1266
1267static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1268 .clock = 32260,
1269 .hdisplay = 800,
1270 .hsync_start = 800 + 168,
1271 .hsync_end = 800 + 168 + 64,
1272 .htotal = 800 + 168 + 64 + 88,
1273 .vdisplay = 480,
1274 .vsync_start = 480 + 37,
1275 .vsync_end = 480 + 37 + 2,
1276 .vtotal = 480 + 37 + 2 + 8,
1277 .vrefresh = 60,
1278};
1279
1280static const struct panel_desc foxlink_fl500wvr00_a0t = {
1281 .modes = &foxlink_fl500wvr00_a0t_mode,
1282 .num_modes = 1,
1283 .bpc = 8,
1284 .size = {
1285 .width = 108,
1286 .height = 65,
1287 },
1288 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1289};
1290
1291static const struct drm_display_mode friendlyarm_hd702e_mode = {
1292 .clock = 67185,
1293 .hdisplay = 800,
1294 .hsync_start = 800 + 20,
1295 .hsync_end = 800 + 20 + 24,
1296 .htotal = 800 + 20 + 24 + 20,
1297 .vdisplay = 1280,
1298 .vsync_start = 1280 + 4,
1299 .vsync_end = 1280 + 4 + 8,
1300 .vtotal = 1280 + 4 + 8 + 4,
1301 .vrefresh = 60,
1302 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1303};
1304
1305static const struct panel_desc friendlyarm_hd702e = {
1306 .modes = &friendlyarm_hd702e_mode,
1307 .num_modes = 1,
1308 .size = {
1309 .width = 94,
1310 .height = 151,
1311 },
1312};
1313
1314static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1315 .clock = 9000,
1316 .hdisplay = 480,
1317 .hsync_start = 480 + 5,
1318 .hsync_end = 480 + 5 + 1,
1319 .htotal = 480 + 5 + 1 + 40,
1320 .vdisplay = 272,
1321 .vsync_start = 272 + 8,
1322 .vsync_end = 272 + 8 + 1,
1323 .vtotal = 272 + 8 + 1 + 8,
1324 .vrefresh = 60,
1325};
1326
1327static const struct panel_desc giantplus_gpg482739qs5 = {
1328 .modes = &giantplus_gpg482739qs5_mode,
1329 .num_modes = 1,
1330 .bpc = 8,
1331 .size = {
1332 .width = 95,
1333 .height = 54,
1334 },
1335 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1336};
1337
1338static const struct display_timing hannstar_hsd070pww1_timing = {
1339 .pixelclock = { 64300000, 71100000, 82000000 },
1340 .hactive = { 1280, 1280, 1280 },
1341 .hfront_porch = { 1, 1, 10 },
1342 .hback_porch = { 1, 1, 10 },
1343
1344
1345
1346
1347
1348 .hsync_len = { 58, 158, 661 },
1349 .vactive = { 800, 800, 800 },
1350 .vfront_porch = { 1, 1, 10 },
1351 .vback_porch = { 1, 1, 10 },
1352 .vsync_len = { 1, 21, 203 },
1353 .flags = DISPLAY_FLAGS_DE_HIGH,
1354};
1355
1356static const struct panel_desc hannstar_hsd070pww1 = {
1357 .timings = &hannstar_hsd070pww1_timing,
1358 .num_timings = 1,
1359 .bpc = 6,
1360 .size = {
1361 .width = 151,
1362 .height = 94,
1363 },
1364 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1365};
1366
1367static const struct display_timing hannstar_hsd100pxn1_timing = {
1368 .pixelclock = { 55000000, 65000000, 75000000 },
1369 .hactive = { 1024, 1024, 1024 },
1370 .hfront_porch = { 40, 40, 40 },
1371 .hback_porch = { 220, 220, 220 },
1372 .hsync_len = { 20, 60, 100 },
1373 .vactive = { 768, 768, 768 },
1374 .vfront_porch = { 7, 7, 7 },
1375 .vback_porch = { 21, 21, 21 },
1376 .vsync_len = { 10, 10, 10 },
1377 .flags = DISPLAY_FLAGS_DE_HIGH,
1378};
1379
1380static const struct panel_desc hannstar_hsd100pxn1 = {
1381 .timings = &hannstar_hsd100pxn1_timing,
1382 .num_timings = 1,
1383 .bpc = 6,
1384 .size = {
1385 .width = 203,
1386 .height = 152,
1387 },
1388 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1389};
1390
1391static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1392 .clock = 33333,
1393 .hdisplay = 800,
1394 .hsync_start = 800 + 85,
1395 .hsync_end = 800 + 85 + 86,
1396 .htotal = 800 + 85 + 86 + 85,
1397 .vdisplay = 480,
1398 .vsync_start = 480 + 16,
1399 .vsync_end = 480 + 16 + 13,
1400 .vtotal = 480 + 16 + 13 + 16,
1401 .vrefresh = 60,
1402};
1403
1404static const struct panel_desc hitachi_tx23d38vm0caa = {
1405 .modes = &hitachi_tx23d38vm0caa_mode,
1406 .num_modes = 1,
1407 .bpc = 6,
1408 .size = {
1409 .width = 195,
1410 .height = 117,
1411 },
1412 .delay = {
1413 .enable = 160,
1414 .disable = 160,
1415 },
1416};
1417
1418static const struct drm_display_mode innolux_at043tn24_mode = {
1419 .clock = 9000,
1420 .hdisplay = 480,
1421 .hsync_start = 480 + 2,
1422 .hsync_end = 480 + 2 + 41,
1423 .htotal = 480 + 2 + 41 + 2,
1424 .vdisplay = 272,
1425 .vsync_start = 272 + 2,
1426 .vsync_end = 272 + 2 + 10,
1427 .vtotal = 272 + 2 + 10 + 2,
1428 .vrefresh = 60,
1429 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1430};
1431
1432static const struct panel_desc innolux_at043tn24 = {
1433 .modes = &innolux_at043tn24_mode,
1434 .num_modes = 1,
1435 .bpc = 8,
1436 .size = {
1437 .width = 95,
1438 .height = 54,
1439 },
1440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1442};
1443
1444static const struct drm_display_mode innolux_at070tn92_mode = {
1445 .clock = 33333,
1446 .hdisplay = 800,
1447 .hsync_start = 800 + 210,
1448 .hsync_end = 800 + 210 + 20,
1449 .htotal = 800 + 210 + 20 + 46,
1450 .vdisplay = 480,
1451 .vsync_start = 480 + 22,
1452 .vsync_end = 480 + 22 + 10,
1453 .vtotal = 480 + 22 + 23 + 10,
1454 .vrefresh = 60,
1455};
1456
1457static const struct panel_desc innolux_at070tn92 = {
1458 .modes = &innolux_at070tn92_mode,
1459 .num_modes = 1,
1460 .size = {
1461 .width = 154,
1462 .height = 86,
1463 },
1464 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1465};
1466
1467static const struct display_timing innolux_g070y2_l01_timing = {
1468 .pixelclock = { 28000000, 29500000, 32000000 },
1469 .hactive = { 800, 800, 800 },
1470 .hfront_porch = { 61, 91, 141 },
1471 .hback_porch = { 60, 90, 140 },
1472 .hsync_len = { 12, 12, 12 },
1473 .vactive = { 480, 480, 480 },
1474 .vfront_porch = { 4, 9, 30 },
1475 .vback_porch = { 4, 8, 28 },
1476 .vsync_len = { 2, 2, 2 },
1477 .flags = DISPLAY_FLAGS_DE_HIGH,
1478};
1479
1480static const struct panel_desc innolux_g070y2_l01 = {
1481 .timings = &innolux_g070y2_l01_timing,
1482 .num_timings = 1,
1483 .bpc = 6,
1484 .size = {
1485 .width = 152,
1486 .height = 91,
1487 },
1488 .delay = {
1489 .prepare = 10,
1490 .enable = 100,
1491 .disable = 100,
1492 .unprepare = 800,
1493 },
1494 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1495};
1496
1497static const struct display_timing innolux_g101ice_l01_timing = {
1498 .pixelclock = { 60400000, 71100000, 74700000 },
1499 .hactive = { 1280, 1280, 1280 },
1500 .hfront_porch = { 41, 80, 100 },
1501 .hback_porch = { 40, 79, 99 },
1502 .hsync_len = { 1, 1, 1 },
1503 .vactive = { 800, 800, 800 },
1504 .vfront_porch = { 5, 11, 14 },
1505 .vback_porch = { 4, 11, 14 },
1506 .vsync_len = { 1, 1, 1 },
1507 .flags = DISPLAY_FLAGS_DE_HIGH,
1508};
1509
1510static const struct panel_desc innolux_g101ice_l01 = {
1511 .timings = &innolux_g101ice_l01_timing,
1512 .num_timings = 1,
1513 .bpc = 8,
1514 .size = {
1515 .width = 217,
1516 .height = 135,
1517 },
1518 .delay = {
1519 .enable = 200,
1520 .disable = 200,
1521 },
1522 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1523};
1524
1525static const struct display_timing innolux_g121i1_l01_timing = {
1526 .pixelclock = { 67450000, 71000000, 74550000 },
1527 .hactive = { 1280, 1280, 1280 },
1528 .hfront_porch = { 40, 80, 160 },
1529 .hback_porch = { 39, 79, 159 },
1530 .hsync_len = { 1, 1, 1 },
1531 .vactive = { 800, 800, 800 },
1532 .vfront_porch = { 5, 11, 100 },
1533 .vback_porch = { 4, 11, 99 },
1534 .vsync_len = { 1, 1, 1 },
1535};
1536
1537static const struct panel_desc innolux_g121i1_l01 = {
1538 .timings = &innolux_g121i1_l01_timing,
1539 .num_timings = 1,
1540 .bpc = 6,
1541 .size = {
1542 .width = 261,
1543 .height = 163,
1544 },
1545 .delay = {
1546 .enable = 200,
1547 .disable = 20,
1548 },
1549 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1550};
1551
1552static const struct drm_display_mode innolux_g121x1_l03_mode = {
1553 .clock = 65000,
1554 .hdisplay = 1024,
1555 .hsync_start = 1024 + 0,
1556 .hsync_end = 1024 + 1,
1557 .htotal = 1024 + 0 + 1 + 320,
1558 .vdisplay = 768,
1559 .vsync_start = 768 + 38,
1560 .vsync_end = 768 + 38 + 1,
1561 .vtotal = 768 + 38 + 1 + 0,
1562 .vrefresh = 60,
1563 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1564};
1565
1566static const struct panel_desc innolux_g121x1_l03 = {
1567 .modes = &innolux_g121x1_l03_mode,
1568 .num_modes = 1,
1569 .bpc = 6,
1570 .size = {
1571 .width = 246,
1572 .height = 185,
1573 },
1574 .delay = {
1575 .enable = 200,
1576 .unprepare = 200,
1577 .disable = 400,
1578 },
1579};
1580
1581static const struct drm_display_mode innolux_n116bge_mode = {
1582 .clock = 76420,
1583 .hdisplay = 1366,
1584 .hsync_start = 1366 + 136,
1585 .hsync_end = 1366 + 136 + 30,
1586 .htotal = 1366 + 136 + 30 + 60,
1587 .vdisplay = 768,
1588 .vsync_start = 768 + 8,
1589 .vsync_end = 768 + 8 + 12,
1590 .vtotal = 768 + 8 + 12 + 12,
1591 .vrefresh = 60,
1592 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1593};
1594
1595static const struct panel_desc innolux_n116bge = {
1596 .modes = &innolux_n116bge_mode,
1597 .num_modes = 1,
1598 .bpc = 6,
1599 .size = {
1600 .width = 256,
1601 .height = 144,
1602 },
1603};
1604
1605static const struct drm_display_mode innolux_n156bge_l21_mode = {
1606 .clock = 69300,
1607 .hdisplay = 1366,
1608 .hsync_start = 1366 + 16,
1609 .hsync_end = 1366 + 16 + 34,
1610 .htotal = 1366 + 16 + 34 + 50,
1611 .vdisplay = 768,
1612 .vsync_start = 768 + 2,
1613 .vsync_end = 768 + 2 + 6,
1614 .vtotal = 768 + 2 + 6 + 12,
1615 .vrefresh = 60,
1616};
1617
1618static const struct panel_desc innolux_n156bge_l21 = {
1619 .modes = &innolux_n156bge_l21_mode,
1620 .num_modes = 1,
1621 .bpc = 6,
1622 .size = {
1623 .width = 344,
1624 .height = 193,
1625 },
1626};
1627
1628static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1629 .clock = 206016,
1630 .hdisplay = 2160,
1631 .hsync_start = 2160 + 48,
1632 .hsync_end = 2160 + 48 + 32,
1633 .htotal = 2160 + 48 + 32 + 80,
1634 .vdisplay = 1440,
1635 .vsync_start = 1440 + 3,
1636 .vsync_end = 1440 + 3 + 10,
1637 .vtotal = 1440 + 3 + 10 + 27,
1638 .vrefresh = 60,
1639 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1640};
1641
1642static const struct panel_desc innolux_p120zdg_bf1 = {
1643 .modes = &innolux_p120zdg_bf1_mode,
1644 .num_modes = 1,
1645 .bpc = 8,
1646 .size = {
1647 .width = 254,
1648 .height = 169,
1649 },
1650 .delay = {
1651 .hpd_absent_delay = 200,
1652 .unprepare = 500,
1653 },
1654};
1655
1656static const struct drm_display_mode innolux_zj070na_01p_mode = {
1657 .clock = 51501,
1658 .hdisplay = 1024,
1659 .hsync_start = 1024 + 128,
1660 .hsync_end = 1024 + 128 + 64,
1661 .htotal = 1024 + 128 + 64 + 128,
1662 .vdisplay = 600,
1663 .vsync_start = 600 + 16,
1664 .vsync_end = 600 + 16 + 4,
1665 .vtotal = 600 + 16 + 4 + 16,
1666 .vrefresh = 60,
1667};
1668
1669static const struct panel_desc innolux_zj070na_01p = {
1670 .modes = &innolux_zj070na_01p_mode,
1671 .num_modes = 1,
1672 .bpc = 6,
1673 .size = {
1674 .width = 154,
1675 .height = 90,
1676 },
1677};
1678
1679static const struct display_timing koe_tx14d24vm1bpa_timing = {
1680 .pixelclock = { 5580000, 5850000, 6200000 },
1681 .hactive = { 320, 320, 320 },
1682 .hfront_porch = { 30, 30, 30 },
1683 .hback_porch = { 30, 30, 30 },
1684 .hsync_len = { 1, 5, 17 },
1685 .vactive = { 240, 240, 240 },
1686 .vfront_porch = { 6, 6, 6 },
1687 .vback_porch = { 5, 5, 5 },
1688 .vsync_len = { 1, 2, 11 },
1689 .flags = DISPLAY_FLAGS_DE_HIGH,
1690};
1691
1692static const struct panel_desc koe_tx14d24vm1bpa = {
1693 .timings = &koe_tx14d24vm1bpa_timing,
1694 .num_timings = 1,
1695 .bpc = 6,
1696 .size = {
1697 .width = 115,
1698 .height = 86,
1699 },
1700};
1701
1702static const struct display_timing koe_tx31d200vm0baa_timing = {
1703 .pixelclock = { 39600000, 43200000, 48000000 },
1704 .hactive = { 1280, 1280, 1280 },
1705 .hfront_porch = { 16, 36, 56 },
1706 .hback_porch = { 16, 36, 56 },
1707 .hsync_len = { 8, 8, 8 },
1708 .vactive = { 480, 480, 480 },
1709 .vfront_porch = { 6, 21, 33 },
1710 .vback_porch = { 6, 21, 33 },
1711 .vsync_len = { 8, 8, 8 },
1712 .flags = DISPLAY_FLAGS_DE_HIGH,
1713};
1714
1715static const struct panel_desc koe_tx31d200vm0baa = {
1716 .timings = &koe_tx31d200vm0baa_timing,
1717 .num_timings = 1,
1718 .bpc = 6,
1719 .size = {
1720 .width = 292,
1721 .height = 109,
1722 },
1723 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1724};
1725
1726static const struct display_timing kyo_tcg121xglp_timing = {
1727 .pixelclock = { 52000000, 65000000, 71000000 },
1728 .hactive = { 1024, 1024, 1024 },
1729 .hfront_porch = { 2, 2, 2 },
1730 .hback_porch = { 2, 2, 2 },
1731 .hsync_len = { 86, 124, 244 },
1732 .vactive = { 768, 768, 768 },
1733 .vfront_porch = { 2, 2, 2 },
1734 .vback_porch = { 2, 2, 2 },
1735 .vsync_len = { 6, 34, 73 },
1736 .flags = DISPLAY_FLAGS_DE_HIGH,
1737};
1738
1739static const struct panel_desc kyo_tcg121xglp = {
1740 .timings = &kyo_tcg121xglp_timing,
1741 .num_timings = 1,
1742 .bpc = 8,
1743 .size = {
1744 .width = 246,
1745 .height = 184,
1746 },
1747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1748};
1749
1750static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1751 .clock = 7000,
1752 .hdisplay = 320,
1753 .hsync_start = 320 + 20,
1754 .hsync_end = 320 + 20 + 30,
1755 .htotal = 320 + 20 + 30 + 38,
1756 .vdisplay = 240,
1757 .vsync_start = 240 + 4,
1758 .vsync_end = 240 + 4 + 3,
1759 .vtotal = 240 + 4 + 3 + 15,
1760 .vrefresh = 60,
1761};
1762
1763static const struct panel_desc lemaker_bl035_rgb_002 = {
1764 .modes = &lemaker_bl035_rgb_002_mode,
1765 .num_modes = 1,
1766 .size = {
1767 .width = 70,
1768 .height = 52,
1769 },
1770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1771 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1772};
1773
1774static const struct drm_display_mode lg_lb070wv8_mode = {
1775 .clock = 33246,
1776 .hdisplay = 800,
1777 .hsync_start = 800 + 88,
1778 .hsync_end = 800 + 88 + 80,
1779 .htotal = 800 + 88 + 80 + 88,
1780 .vdisplay = 480,
1781 .vsync_start = 480 + 10,
1782 .vsync_end = 480 + 10 + 25,
1783 .vtotal = 480 + 10 + 25 + 10,
1784 .vrefresh = 60,
1785};
1786
1787static const struct panel_desc lg_lb070wv8 = {
1788 .modes = &lg_lb070wv8_mode,
1789 .num_modes = 1,
1790 .bpc = 16,
1791 .size = {
1792 .width = 151,
1793 .height = 91,
1794 },
1795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1796};
1797
1798static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1799 .clock = 200000,
1800 .hdisplay = 1536,
1801 .hsync_start = 1536 + 12,
1802 .hsync_end = 1536 + 12 + 16,
1803 .htotal = 1536 + 12 + 16 + 48,
1804 .vdisplay = 2048,
1805 .vsync_start = 2048 + 8,
1806 .vsync_end = 2048 + 8 + 4,
1807 .vtotal = 2048 + 8 + 4 + 8,
1808 .vrefresh = 60,
1809 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1810};
1811
1812static const struct panel_desc lg_lp079qx1_sp0v = {
1813 .modes = &lg_lp079qx1_sp0v_mode,
1814 .num_modes = 1,
1815 .size = {
1816 .width = 129,
1817 .height = 171,
1818 },
1819};
1820
1821static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1822 .clock = 205210,
1823 .hdisplay = 2048,
1824 .hsync_start = 2048 + 150,
1825 .hsync_end = 2048 + 150 + 5,
1826 .htotal = 2048 + 150 + 5 + 5,
1827 .vdisplay = 1536,
1828 .vsync_start = 1536 + 3,
1829 .vsync_end = 1536 + 3 + 1,
1830 .vtotal = 1536 + 3 + 1 + 9,
1831 .vrefresh = 60,
1832};
1833
1834static const struct panel_desc lg_lp097qx1_spa1 = {
1835 .modes = &lg_lp097qx1_spa1_mode,
1836 .num_modes = 1,
1837 .size = {
1838 .width = 208,
1839 .height = 147,
1840 },
1841};
1842
1843static const struct drm_display_mode lg_lp120up1_mode = {
1844 .clock = 162300,
1845 .hdisplay = 1920,
1846 .hsync_start = 1920 + 40,
1847 .hsync_end = 1920 + 40 + 40,
1848 .htotal = 1920 + 40 + 40+ 80,
1849 .vdisplay = 1280,
1850 .vsync_start = 1280 + 4,
1851 .vsync_end = 1280 + 4 + 4,
1852 .vtotal = 1280 + 4 + 4 + 12,
1853 .vrefresh = 60,
1854};
1855
1856static const struct panel_desc lg_lp120up1 = {
1857 .modes = &lg_lp120up1_mode,
1858 .num_modes = 1,
1859 .bpc = 8,
1860 .size = {
1861 .width = 267,
1862 .height = 183,
1863 },
1864};
1865
1866static const struct drm_display_mode lg_lp129qe_mode = {
1867 .clock = 285250,
1868 .hdisplay = 2560,
1869 .hsync_start = 2560 + 48,
1870 .hsync_end = 2560 + 48 + 32,
1871 .htotal = 2560 + 48 + 32 + 80,
1872 .vdisplay = 1700,
1873 .vsync_start = 1700 + 3,
1874 .vsync_end = 1700 + 3 + 10,
1875 .vtotal = 1700 + 3 + 10 + 36,
1876 .vrefresh = 60,
1877};
1878
1879static const struct panel_desc lg_lp129qe = {
1880 .modes = &lg_lp129qe_mode,
1881 .num_modes = 1,
1882 .bpc = 8,
1883 .size = {
1884 .width = 272,
1885 .height = 181,
1886 },
1887};
1888
1889static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1890 .clock = 30400,
1891 .hdisplay = 800,
1892 .hsync_start = 800 + 0,
1893 .hsync_end = 800 + 1,
1894 .htotal = 800 + 0 + 1 + 160,
1895 .vdisplay = 480,
1896 .vsync_start = 480 + 0,
1897 .vsync_end = 480 + 48 + 1,
1898 .vtotal = 480 + 48 + 1 + 0,
1899 .vrefresh = 60,
1900 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1901};
1902
1903static const struct panel_desc mitsubishi_aa070mc01 = {
1904 .modes = &mitsubishi_aa070mc01_mode,
1905 .num_modes = 1,
1906 .bpc = 8,
1907 .size = {
1908 .width = 152,
1909 .height = 91,
1910 },
1911
1912 .delay = {
1913 .enable = 200,
1914 .unprepare = 200,
1915 .disable = 400,
1916 },
1917 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1918 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1919};
1920
1921static const struct display_timing nec_nl12880bc20_05_timing = {
1922 .pixelclock = { 67000000, 71000000, 75000000 },
1923 .hactive = { 1280, 1280, 1280 },
1924 .hfront_porch = { 2, 30, 30 },
1925 .hback_porch = { 6, 100, 100 },
1926 .hsync_len = { 2, 30, 30 },
1927 .vactive = { 800, 800, 800 },
1928 .vfront_porch = { 5, 5, 5 },
1929 .vback_porch = { 11, 11, 11 },
1930 .vsync_len = { 7, 7, 7 },
1931};
1932
1933static const struct panel_desc nec_nl12880bc20_05 = {
1934 .timings = &nec_nl12880bc20_05_timing,
1935 .num_timings = 1,
1936 .bpc = 8,
1937 .size = {
1938 .width = 261,
1939 .height = 163,
1940 },
1941 .delay = {
1942 .enable = 50,
1943 .disable = 50,
1944 },
1945 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1946};
1947
1948static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1949 .clock = 10870,
1950 .hdisplay = 480,
1951 .hsync_start = 480 + 2,
1952 .hsync_end = 480 + 2 + 41,
1953 .htotal = 480 + 2 + 41 + 2,
1954 .vdisplay = 272,
1955 .vsync_start = 272 + 2,
1956 .vsync_end = 272 + 2 + 4,
1957 .vtotal = 272 + 2 + 4 + 2,
1958 .vrefresh = 74,
1959 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1960};
1961
1962static const struct panel_desc nec_nl4827hc19_05b = {
1963 .modes = &nec_nl4827hc19_05b_mode,
1964 .num_modes = 1,
1965 .bpc = 8,
1966 .size = {
1967 .width = 95,
1968 .height = 54,
1969 },
1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1971 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1972};
1973
1974static const struct drm_display_mode netron_dy_e231732_mode = {
1975 .clock = 66000,
1976 .hdisplay = 1024,
1977 .hsync_start = 1024 + 160,
1978 .hsync_end = 1024 + 160 + 70,
1979 .htotal = 1024 + 160 + 70 + 90,
1980 .vdisplay = 600,
1981 .vsync_start = 600 + 127,
1982 .vsync_end = 600 + 127 + 20,
1983 .vtotal = 600 + 127 + 20 + 3,
1984 .vrefresh = 60,
1985};
1986
1987static const struct panel_desc netron_dy_e231732 = {
1988 .modes = &netron_dy_e231732_mode,
1989 .num_modes = 1,
1990 .size = {
1991 .width = 154,
1992 .height = 87,
1993 },
1994 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1995};
1996
1997static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1998 .clock = 9000,
1999 .hdisplay = 480,
2000 .hsync_start = 480 + 2,
2001 .hsync_end = 480 + 2 + 41,
2002 .htotal = 480 + 2 + 41 + 2,
2003 .vdisplay = 272,
2004 .vsync_start = 272 + 2,
2005 .vsync_end = 272 + 2 + 10,
2006 .vtotal = 272 + 2 + 10 + 2,
2007 .vrefresh = 60,
2008 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2009};
2010
2011static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2012 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2013 .num_modes = 1,
2014 .bpc = 8,
2015 .size = {
2016 .width = 95,
2017 .height = 54,
2018 },
2019 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2021 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2022};
2023
2024static const struct display_timing nlt_nl192108ac18_02d_timing = {
2025 .pixelclock = { 130000000, 148350000, 163000000 },
2026 .hactive = { 1920, 1920, 1920 },
2027 .hfront_porch = { 80, 100, 100 },
2028 .hback_porch = { 100, 120, 120 },
2029 .hsync_len = { 50, 60, 60 },
2030 .vactive = { 1080, 1080, 1080 },
2031 .vfront_porch = { 12, 30, 30 },
2032 .vback_porch = { 4, 10, 10 },
2033 .vsync_len = { 4, 5, 5 },
2034};
2035
2036static const struct panel_desc nlt_nl192108ac18_02d = {
2037 .timings = &nlt_nl192108ac18_02d_timing,
2038 .num_timings = 1,
2039 .bpc = 8,
2040 .size = {
2041 .width = 344,
2042 .height = 194,
2043 },
2044 .delay = {
2045 .unprepare = 500,
2046 },
2047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2048};
2049
2050static const struct drm_display_mode nvd_9128_mode = {
2051 .clock = 29500,
2052 .hdisplay = 800,
2053 .hsync_start = 800 + 130,
2054 .hsync_end = 800 + 130 + 98,
2055 .htotal = 800 + 0 + 130 + 98,
2056 .vdisplay = 480,
2057 .vsync_start = 480 + 10,
2058 .vsync_end = 480 + 10 + 50,
2059 .vtotal = 480 + 0 + 10 + 50,
2060};
2061
2062static const struct panel_desc nvd_9128 = {
2063 .modes = &nvd_9128_mode,
2064 .num_modes = 1,
2065 .bpc = 8,
2066 .size = {
2067 .width = 156,
2068 .height = 88,
2069 },
2070 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2071};
2072
2073static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2074 .pixelclock = { 30000000, 30000000, 40000000 },
2075 .hactive = { 800, 800, 800 },
2076 .hfront_porch = { 40, 40, 40 },
2077 .hback_porch = { 40, 40, 40 },
2078 .hsync_len = { 1, 48, 48 },
2079 .vactive = { 480, 480, 480 },
2080 .vfront_porch = { 13, 13, 13 },
2081 .vback_porch = { 29, 29, 29 },
2082 .vsync_len = { 3, 3, 3 },
2083 .flags = DISPLAY_FLAGS_DE_HIGH,
2084};
2085
2086static const struct panel_desc okaya_rs800480t_7x0gp = {
2087 .timings = &okaya_rs800480t_7x0gp_timing,
2088 .num_timings = 1,
2089 .bpc = 6,
2090 .size = {
2091 .width = 154,
2092 .height = 87,
2093 },
2094 .delay = {
2095 .prepare = 41,
2096 .enable = 50,
2097 .unprepare = 41,
2098 .disable = 50,
2099 },
2100 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2101};
2102
2103static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2104 .clock = 9000,
2105 .hdisplay = 480,
2106 .hsync_start = 480 + 5,
2107 .hsync_end = 480 + 5 + 30,
2108 .htotal = 480 + 5 + 30 + 10,
2109 .vdisplay = 272,
2110 .vsync_start = 272 + 8,
2111 .vsync_end = 272 + 8 + 5,
2112 .vtotal = 272 + 8 + 5 + 3,
2113 .vrefresh = 60,
2114};
2115
2116static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2117 .modes = &olimex_lcd_olinuxino_43ts_mode,
2118 .num_modes = 1,
2119 .size = {
2120 .width = 95,
2121 .height = 54,
2122 },
2123 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2124};
2125
2126
2127
2128
2129
2130
2131static const struct drm_display_mode ontat_yx700wv03_mode = {
2132 .clock = 29500,
2133 .hdisplay = 800,
2134 .hsync_start = 824,
2135 .hsync_end = 896,
2136 .htotal = 992,
2137 .vdisplay = 480,
2138 .vsync_start = 483,
2139 .vsync_end = 493,
2140 .vtotal = 500,
2141 .vrefresh = 60,
2142 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2143};
2144
2145
2146
2147
2148
2149static const struct panel_desc ontat_yx700wv03 = {
2150 .modes = &ontat_yx700wv03_mode,
2151 .num_modes = 1,
2152 .bpc = 8,
2153 .size = {
2154 .width = 154,
2155 .height = 83,
2156 },
2157 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2158};
2159
2160static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2161 .clock = 25000,
2162 .hdisplay = 480,
2163 .hsync_start = 480 + 10,
2164 .hsync_end = 480 + 10 + 10,
2165 .htotal = 480 + 10 + 10 + 15,
2166 .vdisplay = 800,
2167 .vsync_start = 800 + 3,
2168 .vsync_end = 800 + 3 + 3,
2169 .vtotal = 800 + 3 + 3 + 3,
2170 .vrefresh = 60,
2171};
2172
2173static const struct panel_desc ortustech_com43h4m85ulc = {
2174 .modes = &ortustech_com43h4m85ulc_mode,
2175 .num_modes = 1,
2176 .bpc = 8,
2177 .size = {
2178 .width = 56,
2179 .height = 93,
2180 },
2181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2183};
2184
2185static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2186 .clock = 33000,
2187 .hdisplay = 800,
2188 .hsync_start = 800 + 210,
2189 .hsync_end = 800 + 210 + 30,
2190 .htotal = 800 + 210 + 30 + 16,
2191 .vdisplay = 480,
2192 .vsync_start = 480 + 22,
2193 .vsync_end = 480 + 22 + 13,
2194 .vtotal = 480 + 22 + 13 + 10,
2195 .vrefresh = 60,
2196 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2197};
2198
2199static const struct panel_desc osddisplays_osd070t1718_19ts = {
2200 .modes = &osddisplays_osd070t1718_19ts_mode,
2201 .num_modes = 1,
2202 .bpc = 8,
2203 .size = {
2204 .width = 152,
2205 .height = 91,
2206 },
2207 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2209};
2210
2211static const struct drm_display_mode pda_91_00156_a0_mode = {
2212 .clock = 33300,
2213 .hdisplay = 800,
2214 .hsync_start = 800 + 1,
2215 .hsync_end = 800 + 1 + 64,
2216 .htotal = 800 + 1 + 64 + 64,
2217 .vdisplay = 480,
2218 .vsync_start = 480 + 1,
2219 .vsync_end = 480 + 1 + 23,
2220 .vtotal = 480 + 1 + 23 + 22,
2221 .vrefresh = 60,
2222};
2223
2224static const struct panel_desc pda_91_00156_a0 = {
2225 .modes = &pda_91_00156_a0_mode,
2226 .num_modes = 1,
2227 .size = {
2228 .width = 152,
2229 .height = 91,
2230 },
2231 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2232};
2233
2234
2235static const struct drm_display_mode qd43003c0_40_mode = {
2236 .clock = 9000,
2237 .hdisplay = 480,
2238 .hsync_start = 480 + 8,
2239 .hsync_end = 480 + 8 + 4,
2240 .htotal = 480 + 8 + 4 + 39,
2241 .vdisplay = 272,
2242 .vsync_start = 272 + 4,
2243 .vsync_end = 272 + 4 + 10,
2244 .vtotal = 272 + 4 + 10 + 2,
2245 .vrefresh = 60,
2246};
2247
2248static const struct panel_desc qd43003c0_40 = {
2249 .modes = &qd43003c0_40_mode,
2250 .num_modes = 1,
2251 .bpc = 8,
2252 .size = {
2253 .width = 95,
2254 .height = 53,
2255 },
2256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2257};
2258
2259static const struct display_timing rocktech_rk070er9427_timing = {
2260 .pixelclock = { 26400000, 33300000, 46800000 },
2261 .hactive = { 800, 800, 800 },
2262 .hfront_porch = { 16, 210, 354 },
2263 .hback_porch = { 46, 46, 46 },
2264 .hsync_len = { 1, 1, 1 },
2265 .vactive = { 480, 480, 480 },
2266 .vfront_porch = { 7, 22, 147 },
2267 .vback_porch = { 23, 23, 23 },
2268 .vsync_len = { 1, 1, 1 },
2269 .flags = DISPLAY_FLAGS_DE_HIGH,
2270};
2271
2272static const struct panel_desc rocktech_rk070er9427 = {
2273 .timings = &rocktech_rk070er9427_timing,
2274 .num_timings = 1,
2275 .bpc = 6,
2276 .size = {
2277 .width = 154,
2278 .height = 86,
2279 },
2280 .delay = {
2281 .prepare = 41,
2282 .enable = 50,
2283 .unprepare = 41,
2284 .disable = 50,
2285 },
2286 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2287};
2288
2289static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2290 .clock = 271560,
2291 .hdisplay = 2560,
2292 .hsync_start = 2560 + 48,
2293 .hsync_end = 2560 + 48 + 32,
2294 .htotal = 2560 + 48 + 32 + 80,
2295 .vdisplay = 1600,
2296 .vsync_start = 1600 + 2,
2297 .vsync_end = 1600 + 2 + 5,
2298 .vtotal = 1600 + 2 + 5 + 57,
2299 .vrefresh = 60,
2300};
2301
2302static const struct panel_desc samsung_lsn122dl01_c01 = {
2303 .modes = &samsung_lsn122dl01_c01_mode,
2304 .num_modes = 1,
2305 .size = {
2306 .width = 263,
2307 .height = 164,
2308 },
2309};
2310
2311static const struct drm_display_mode samsung_ltn101nt05_mode = {
2312 .clock = 54030,
2313 .hdisplay = 1024,
2314 .hsync_start = 1024 + 24,
2315 .hsync_end = 1024 + 24 + 136,
2316 .htotal = 1024 + 24 + 136 + 160,
2317 .vdisplay = 600,
2318 .vsync_start = 600 + 3,
2319 .vsync_end = 600 + 3 + 6,
2320 .vtotal = 600 + 3 + 6 + 61,
2321 .vrefresh = 60,
2322};
2323
2324static const struct panel_desc samsung_ltn101nt05 = {
2325 .modes = &samsung_ltn101nt05_mode,
2326 .num_modes = 1,
2327 .bpc = 6,
2328 .size = {
2329 .width = 223,
2330 .height = 125,
2331 },
2332};
2333
2334static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2335 .clock = 76300,
2336 .hdisplay = 1366,
2337 .hsync_start = 1366 + 64,
2338 .hsync_end = 1366 + 64 + 48,
2339 .htotal = 1366 + 64 + 48 + 128,
2340 .vdisplay = 768,
2341 .vsync_start = 768 + 2,
2342 .vsync_end = 768 + 2 + 5,
2343 .vtotal = 768 + 2 + 5 + 17,
2344 .vrefresh = 60,
2345};
2346
2347static const struct panel_desc samsung_ltn140at29_301 = {
2348 .modes = &samsung_ltn140at29_301_mode,
2349 .num_modes = 1,
2350 .bpc = 6,
2351 .size = {
2352 .width = 320,
2353 .height = 187,
2354 },
2355};
2356
2357static const struct drm_display_mode sharp_lq035q7db03_mode = {
2358 .clock = 5500,
2359 .hdisplay = 240,
2360 .hsync_start = 240 + 16,
2361 .hsync_end = 240 + 16 + 7,
2362 .htotal = 240 + 16 + 7 + 5,
2363 .vdisplay = 320,
2364 .vsync_start = 320 + 9,
2365 .vsync_end = 320 + 9 + 1,
2366 .vtotal = 320 + 9 + 1 + 7,
2367 .vrefresh = 60,
2368};
2369
2370static const struct panel_desc sharp_lq035q7db03 = {
2371 .modes = &sharp_lq035q7db03_mode,
2372 .num_modes = 1,
2373 .bpc = 6,
2374 .size = {
2375 .width = 54,
2376 .height = 72,
2377 },
2378 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2379};
2380
2381static const struct display_timing sharp_lq101k1ly04_timing = {
2382 .pixelclock = { 60000000, 65000000, 80000000 },
2383 .hactive = { 1280, 1280, 1280 },
2384 .hfront_porch = { 20, 20, 20 },
2385 .hback_porch = { 20, 20, 20 },
2386 .hsync_len = { 10, 10, 10 },
2387 .vactive = { 800, 800, 800 },
2388 .vfront_porch = { 4, 4, 4 },
2389 .vback_porch = { 4, 4, 4 },
2390 .vsync_len = { 4, 4, 4 },
2391 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2392};
2393
2394static const struct panel_desc sharp_lq101k1ly04 = {
2395 .timings = &sharp_lq101k1ly04_timing,
2396 .num_timings = 1,
2397 .bpc = 8,
2398 .size = {
2399 .width = 217,
2400 .height = 136,
2401 },
2402 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2403};
2404
2405static const struct display_timing sharp_lq123p1jx31_timing = {
2406 .pixelclock = { 252750000, 252750000, 266604720 },
2407 .hactive = { 2400, 2400, 2400 },
2408 .hfront_porch = { 48, 48, 48 },
2409 .hback_porch = { 80, 80, 84 },
2410 .hsync_len = { 32, 32, 32 },
2411 .vactive = { 1600, 1600, 1600 },
2412 .vfront_porch = { 3, 3, 3 },
2413 .vback_porch = { 33, 33, 120 },
2414 .vsync_len = { 10, 10, 10 },
2415 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2416};
2417
2418static const struct panel_desc sharp_lq123p1jx31 = {
2419 .timings = &sharp_lq123p1jx31_timing,
2420 .num_timings = 1,
2421 .bpc = 8,
2422 .size = {
2423 .width = 259,
2424 .height = 173,
2425 },
2426 .delay = {
2427 .prepare = 110,
2428 .enable = 50,
2429 .unprepare = 550,
2430 },
2431};
2432
2433static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2434 .clock = 71100,
2435 .hdisplay = 1024,
2436 .hsync_start = 1024 + 168,
2437 .hsync_end = 1024 + 168 + 64,
2438 .htotal = 1024 + 168 + 64 + 88,
2439 .vdisplay = 768,
2440 .vsync_start = 768 + 37,
2441 .vsync_end = 768 + 37 + 2,
2442 .vtotal = 768 + 37 + 2 + 8,
2443 .vrefresh = 60,
2444};
2445
2446static const struct panel_desc sharp_lq150x1lg11 = {
2447 .modes = &sharp_lq150x1lg11_mode,
2448 .num_modes = 1,
2449 .bpc = 6,
2450 .size = {
2451 .width = 304,
2452 .height = 228,
2453 },
2454 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2455};
2456
2457static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2458 .clock = 33300,
2459 .hdisplay = 800,
2460 .hsync_start = 800 + 1,
2461 .hsync_end = 800 + 1 + 64,
2462 .htotal = 800 + 1 + 64 + 64,
2463 .vdisplay = 480,
2464 .vsync_start = 480 + 1,
2465 .vsync_end = 480 + 1 + 23,
2466 .vtotal = 480 + 1 + 23 + 22,
2467 .vrefresh = 60,
2468};
2469
2470static const struct panel_desc shelly_sca07010_bfn_lnn = {
2471 .modes = &shelly_sca07010_bfn_lnn_mode,
2472 .num_modes = 1,
2473 .size = {
2474 .width = 152,
2475 .height = 91,
2476 },
2477 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2478};
2479
2480static const struct drm_display_mode starry_kr122ea0sra_mode = {
2481 .clock = 147000,
2482 .hdisplay = 1920,
2483 .hsync_start = 1920 + 16,
2484 .hsync_end = 1920 + 16 + 16,
2485 .htotal = 1920 + 16 + 16 + 32,
2486 .vdisplay = 1200,
2487 .vsync_start = 1200 + 15,
2488 .vsync_end = 1200 + 15 + 2,
2489 .vtotal = 1200 + 15 + 2 + 18,
2490 .vrefresh = 60,
2491 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2492};
2493
2494static const struct panel_desc starry_kr122ea0sra = {
2495 .modes = &starry_kr122ea0sra_mode,
2496 .num_modes = 1,
2497 .size = {
2498 .width = 263,
2499 .height = 164,
2500 },
2501 .delay = {
2502 .prepare = 10 + 200,
2503 .enable = 50,
2504 .unprepare = 10 + 500,
2505 },
2506};
2507
2508static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2509 .clock = 30000,
2510 .hdisplay = 800,
2511 .hsync_start = 800 + 39,
2512 .hsync_end = 800 + 39 + 47,
2513 .htotal = 800 + 39 + 47 + 39,
2514 .vdisplay = 480,
2515 .vsync_start = 480 + 13,
2516 .vsync_end = 480 + 13 + 2,
2517 .vtotal = 480 + 13 + 2 + 29,
2518 .vrefresh = 62,
2519};
2520
2521static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2522 .modes = &tfc_s9700rtwv43tr_01b_mode,
2523 .num_modes = 1,
2524 .bpc = 8,
2525 .size = {
2526 .width = 155,
2527 .height = 90,
2528 },
2529 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2530 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2531};
2532
2533static const struct display_timing tianma_tm070jdhg30_timing = {
2534 .pixelclock = { 62600000, 68200000, 78100000 },
2535 .hactive = { 1280, 1280, 1280 },
2536 .hfront_porch = { 15, 64, 159 },
2537 .hback_porch = { 5, 5, 5 },
2538 .hsync_len = { 1, 1, 256 },
2539 .vactive = { 800, 800, 800 },
2540 .vfront_porch = { 3, 40, 99 },
2541 .vback_porch = { 2, 2, 2 },
2542 .vsync_len = { 1, 1, 128 },
2543 .flags = DISPLAY_FLAGS_DE_HIGH,
2544};
2545
2546static const struct panel_desc tianma_tm070jdhg30 = {
2547 .timings = &tianma_tm070jdhg30_timing,
2548 .num_timings = 1,
2549 .bpc = 8,
2550 .size = {
2551 .width = 151,
2552 .height = 95,
2553 },
2554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2555};
2556
2557static const struct display_timing tianma_tm070rvhg71_timing = {
2558 .pixelclock = { 27700000, 29200000, 39600000 },
2559 .hactive = { 800, 800, 800 },
2560 .hfront_porch = { 12, 40, 212 },
2561 .hback_porch = { 88, 88, 88 },
2562 .hsync_len = { 1, 1, 40 },
2563 .vactive = { 480, 480, 480 },
2564 .vfront_porch = { 1, 13, 88 },
2565 .vback_porch = { 32, 32, 32 },
2566 .vsync_len = { 1, 1, 3 },
2567 .flags = DISPLAY_FLAGS_DE_HIGH,
2568};
2569
2570static const struct panel_desc tianma_tm070rvhg71 = {
2571 .timings = &tianma_tm070rvhg71_timing,
2572 .num_timings = 1,
2573 .bpc = 8,
2574 .size = {
2575 .width = 154,
2576 .height = 86,
2577 },
2578 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2579};
2580
2581static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2582 .clock = 79500,
2583 .hdisplay = 1280,
2584 .hsync_start = 1280 + 192,
2585 .hsync_end = 1280 + 192 + 128,
2586 .htotal = 1280 + 192 + 128 + 64,
2587 .vdisplay = 768,
2588 .vsync_start = 768 + 20,
2589 .vsync_end = 768 + 20 + 7,
2590 .vtotal = 768 + 20 + 7 + 3,
2591 .vrefresh = 60,
2592};
2593
2594static const struct panel_desc toshiba_lt089ac29000 = {
2595 .modes = &toshiba_lt089ac29000_mode,
2596 .num_modes = 1,
2597 .size = {
2598 .width = 194,
2599 .height = 116,
2600 },
2601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2602 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2603};
2604
2605static const struct drm_display_mode tpk_f07a_0102_mode = {
2606 .clock = 33260,
2607 .hdisplay = 800,
2608 .hsync_start = 800 + 40,
2609 .hsync_end = 800 + 40 + 128,
2610 .htotal = 800 + 40 + 128 + 88,
2611 .vdisplay = 480,
2612 .vsync_start = 480 + 10,
2613 .vsync_end = 480 + 10 + 2,
2614 .vtotal = 480 + 10 + 2 + 33,
2615 .vrefresh = 60,
2616};
2617
2618static const struct panel_desc tpk_f07a_0102 = {
2619 .modes = &tpk_f07a_0102_mode,
2620 .num_modes = 1,
2621 .size = {
2622 .width = 152,
2623 .height = 91,
2624 },
2625 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2626};
2627
2628static const struct drm_display_mode tpk_f10a_0102_mode = {
2629 .clock = 45000,
2630 .hdisplay = 1024,
2631 .hsync_start = 1024 + 176,
2632 .hsync_end = 1024 + 176 + 5,
2633 .htotal = 1024 + 176 + 5 + 88,
2634 .vdisplay = 600,
2635 .vsync_start = 600 + 20,
2636 .vsync_end = 600 + 20 + 5,
2637 .vtotal = 600 + 20 + 5 + 25,
2638 .vrefresh = 60,
2639};
2640
2641static const struct panel_desc tpk_f10a_0102 = {
2642 .modes = &tpk_f10a_0102_mode,
2643 .num_modes = 1,
2644 .size = {
2645 .width = 223,
2646 .height = 125,
2647 },
2648};
2649
2650static const struct display_timing urt_umsh_8596md_timing = {
2651 .pixelclock = { 33260000, 33260000, 33260000 },
2652 .hactive = { 800, 800, 800 },
2653 .hfront_porch = { 41, 41, 41 },
2654 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2655 .hsync_len = { 71, 128, 128 },
2656 .vactive = { 480, 480, 480 },
2657 .vfront_porch = { 10, 10, 10 },
2658 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2659 .vsync_len = { 2, 2, 2 },
2660 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2661 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2662};
2663
2664static const struct panel_desc urt_umsh_8596md_lvds = {
2665 .timings = &urt_umsh_8596md_timing,
2666 .num_timings = 1,
2667 .bpc = 6,
2668 .size = {
2669 .width = 152,
2670 .height = 91,
2671 },
2672 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2673};
2674
2675static const struct panel_desc urt_umsh_8596md_parallel = {
2676 .timings = &urt_umsh_8596md_timing,
2677 .num_timings = 1,
2678 .bpc = 6,
2679 .size = {
2680 .width = 152,
2681 .height = 91,
2682 },
2683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2684};
2685
2686static const struct drm_display_mode vl050_8048nt_c01_mode = {
2687 .clock = 33333,
2688 .hdisplay = 800,
2689 .hsync_start = 800 + 210,
2690 .hsync_end = 800 + 210 + 20,
2691 .htotal = 800 + 210 + 20 + 46,
2692 .vdisplay = 480,
2693 .vsync_start = 480 + 22,
2694 .vsync_end = 480 + 22 + 10,
2695 .vtotal = 480 + 22 + 10 + 23,
2696 .vrefresh = 60,
2697 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2698};
2699
2700static const struct panel_desc vl050_8048nt_c01 = {
2701 .modes = &vl050_8048nt_c01_mode,
2702 .num_modes = 1,
2703 .bpc = 8,
2704 .size = {
2705 .width = 120,
2706 .height = 76,
2707 },
2708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2709 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2710};
2711
2712static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2713 .clock = 6410,
2714 .hdisplay = 320,
2715 .hsync_start = 320 + 20,
2716 .hsync_end = 320 + 20 + 30,
2717 .htotal = 320 + 20 + 30 + 38,
2718 .vdisplay = 240,
2719 .vsync_start = 240 + 4,
2720 .vsync_end = 240 + 4 + 3,
2721 .vtotal = 240 + 4 + 3 + 15,
2722 .vrefresh = 60,
2723 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2724};
2725
2726static const struct panel_desc winstar_wf35ltiacd = {
2727 .modes = &winstar_wf35ltiacd_mode,
2728 .num_modes = 1,
2729 .bpc = 8,
2730 .size = {
2731 .width = 70,
2732 .height = 53,
2733 },
2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2735};
2736
2737static const struct drm_display_mode arm_rtsm_mode[] = {
2738 {
2739 .clock = 65000,
2740 .hdisplay = 1024,
2741 .hsync_start = 1024 + 24,
2742 .hsync_end = 1024 + 24 + 136,
2743 .htotal = 1024 + 24 + 136 + 160,
2744 .vdisplay = 768,
2745 .vsync_start = 768 + 3,
2746 .vsync_end = 768 + 3 + 6,
2747 .vtotal = 768 + 3 + 6 + 29,
2748 .vrefresh = 60,
2749 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2750 },
2751};
2752
2753static const struct panel_desc arm_rtsm = {
2754 .modes = arm_rtsm_mode,
2755 .num_modes = 1,
2756 .bpc = 8,
2757 .size = {
2758 .width = 400,
2759 .height = 300,
2760 },
2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2762};
2763
2764static const struct of_device_id platform_of_match[] = {
2765 {
2766 .compatible = "ampire,am-480272h3tmqw-t01h",
2767 .data = &ire_am_480272h3tmqw_t01h,
2768 }, {
2769 .compatible = "ampire,am800480r3tmqwa1h",
2770 .data = &ire_am800480r3tmqwa1h,
2771 }, {
2772 .compatible = "arm,rtsm-display",
2773 .data = &arm_rtsm,
2774 }, {
2775 .compatible = "armadeus,st0700-adapt",
2776 .data = &armadeus_st0700_adapt,
2777 }, {
2778 .compatible = "auo,b101aw03",
2779 .data = &auo_b101aw03,
2780 }, {
2781 .compatible = "auo,b101ean01",
2782 .data = &auo_b101ean01,
2783 }, {
2784 .compatible = "auo,b101xtn01",
2785 .data = &auo_b101xtn01,
2786 }, {
2787 .compatible = "auo,b116xw03",
2788 .data = &auo_b116xw03,
2789 }, {
2790 .compatible = "auo,b133htn01",
2791 .data = &auo_b133htn01,
2792 }, {
2793 .compatible = "auo,b133xtn01",
2794 .data = &auo_b133xtn01,
2795 }, {
2796 .compatible = "auo,g070vvn01",
2797 .data = &auo_g070vvn01,
2798 }, {
2799 .compatible = "auo,g101evn010",
2800 .data = &auo_g101evn010,
2801 }, {
2802 .compatible = "auo,g104sn02",
2803 .data = &auo_g104sn02,
2804 }, {
2805 .compatible = "auo,g133han01",
2806 .data = &auo_g133han01,
2807 }, {
2808 .compatible = "auo,g185han01",
2809 .data = &auo_g185han01,
2810 }, {
2811 .compatible = "auo,p320hvn03",
2812 .data = &auo_p320hvn03,
2813 }, {
2814 .compatible = "auo,t215hvn01",
2815 .data = &auo_t215hvn01,
2816 }, {
2817 .compatible = "avic,tm070ddh03",
2818 .data = &avic_tm070ddh03,
2819 }, {
2820 .compatible = "bananapi,s070wv20-ct16",
2821 .data = &bananapi_s070wv20_ct16,
2822 }, {
2823 .compatible = "boe,hv070wsa-100",
2824 .data = &boe_hv070wsa
2825 }, {
2826 .compatible = "boe,nv101wxmn51",
2827 .data = &boe_nv101wxmn51,
2828 }, {
2829 .compatible = "cdtech,s043wq26h-ct7",
2830 .data = &cdtech_s043wq26h_ct7,
2831 }, {
2832 .compatible = "cdtech,s070wv95-ct16",
2833 .data = &cdtech_s070wv95_ct16,
2834 }, {
2835 .compatible = "chunghwa,claa070wp03xg",
2836 .data = &chunghwa_claa070wp03xg,
2837 }, {
2838 .compatible = "chunghwa,claa101wa01a",
2839 .data = &chunghwa_claa101wa01a
2840 }, {
2841 .compatible = "chunghwa,claa101wb01",
2842 .data = &chunghwa_claa101wb01
2843 }, {
2844 .compatible = "dataimage,scf0700c48ggu18",
2845 .data = &dataimage_scf0700c48ggu18,
2846 }, {
2847 .compatible = "dlc,dlc0700yzg-1",
2848 .data = &dlc_dlc0700yzg_1,
2849 }, {
2850 .compatible = "dlc,dlc1010gig",
2851 .data = &dlc_dlc1010gig,
2852 }, {
2853 .compatible = "edt,et035012dm6",
2854 .data = &edt_et035012dm6,
2855 }, {
2856 .compatible = "edt,etm0430g0dh6",
2857 .data = &edt_etm0430g0dh6,
2858 }, {
2859 .compatible = "edt,et057090dhu",
2860 .data = &edt_et057090dhu,
2861 }, {
2862 .compatible = "edt,et070080dh6",
2863 .data = &edt_etm0700g0dh6,
2864 }, {
2865 .compatible = "edt,etm0700g0dh6",
2866 .data = &edt_etm0700g0dh6,
2867 }, {
2868 .compatible = "edt,etm0700g0bdh6",
2869 .data = &edt_etm0700g0bdh6,
2870 }, {
2871 .compatible = "edt,etm0700g0edh6",
2872 .data = &edt_etm0700g0bdh6,
2873 }, {
2874 .compatible = "evervision,vgg804821",
2875 .data = &evervision_vgg804821,
2876 }, {
2877 .compatible = "foxlink,fl500wvr00-a0t",
2878 .data = &foxlink_fl500wvr00_a0t,
2879 }, {
2880 .compatible = "friendlyarm,hd702e",
2881 .data = &friendlyarm_hd702e,
2882 }, {
2883 .compatible = "giantplus,gpg482739qs5",
2884 .data = &giantplus_gpg482739qs5
2885 }, {
2886 .compatible = "hannstar,hsd070pww1",
2887 .data = &hannstar_hsd070pww1,
2888 }, {
2889 .compatible = "hannstar,hsd100pxn1",
2890 .data = &hannstar_hsd100pxn1,
2891 }, {
2892 .compatible = "hit,tx23d38vm0caa",
2893 .data = &hitachi_tx23d38vm0caa
2894 }, {
2895 .compatible = "innolux,at043tn24",
2896 .data = &innolux_at043tn24,
2897 }, {
2898 .compatible = "innolux,at070tn92",
2899 .data = &innolux_at070tn92,
2900 }, {
2901 .compatible = "innolux,g070y2-l01",
2902 .data = &innolux_g070y2_l01,
2903 }, {
2904 .compatible = "innolux,g101ice-l01",
2905 .data = &innolux_g101ice_l01
2906 }, {
2907 .compatible = "innolux,g121i1-l01",
2908 .data = &innolux_g121i1_l01
2909 }, {
2910 .compatible = "innolux,g121x1-l03",
2911 .data = &innolux_g121x1_l03,
2912 }, {
2913 .compatible = "innolux,n116bge",
2914 .data = &innolux_n116bge,
2915 }, {
2916 .compatible = "innolux,n156bge-l21",
2917 .data = &innolux_n156bge_l21,
2918 }, {
2919 .compatible = "innolux,p120zdg-bf1",
2920 .data = &innolux_p120zdg_bf1,
2921 }, {
2922 .compatible = "innolux,zj070na-01p",
2923 .data = &innolux_zj070na_01p,
2924 }, {
2925 .compatible = "koe,tx14d24vm1bpa",
2926 .data = &koe_tx14d24vm1bpa,
2927 }, {
2928 .compatible = "koe,tx31d200vm0baa",
2929 .data = &koe_tx31d200vm0baa,
2930 }, {
2931 .compatible = "kyo,tcg121xglp",
2932 .data = &kyo_tcg121xglp,
2933 }, {
2934 .compatible = "lemaker,bl035-rgb-002",
2935 .data = &lemaker_bl035_rgb_002,
2936 }, {
2937 .compatible = "lg,lb070wv8",
2938 .data = &lg_lb070wv8,
2939 }, {
2940 .compatible = "lg,lp079qx1-sp0v",
2941 .data = &lg_lp079qx1_sp0v,
2942 }, {
2943 .compatible = "lg,lp097qx1-spa1",
2944 .data = &lg_lp097qx1_spa1,
2945 }, {
2946 .compatible = "lg,lp120up1",
2947 .data = &lg_lp120up1,
2948 }, {
2949 .compatible = "lg,lp129qe",
2950 .data = &lg_lp129qe,
2951 }, {
2952 .compatible = "mitsubishi,aa070mc01-ca1",
2953 .data = &mitsubishi_aa070mc01,
2954 }, {
2955 .compatible = "nec,nl12880bc20-05",
2956 .data = &nec_nl12880bc20_05,
2957 }, {
2958 .compatible = "nec,nl4827hc19-05b",
2959 .data = &nec_nl4827hc19_05b,
2960 }, {
2961 .compatible = "netron-dy,e231732",
2962 .data = &netron_dy_e231732,
2963 }, {
2964 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2965 .data = &newhaven_nhd_43_480272ef_atxl,
2966 }, {
2967 .compatible = "nlt,nl192108ac18-02d",
2968 .data = &nlt_nl192108ac18_02d,
2969 }, {
2970 .compatible = "nvd,9128",
2971 .data = &nvd_9128,
2972 }, {
2973 .compatible = "okaya,rs800480t-7x0gp",
2974 .data = &okaya_rs800480t_7x0gp,
2975 }, {
2976 .compatible = "olimex,lcd-olinuxino-43-ts",
2977 .data = &olimex_lcd_olinuxino_43ts,
2978 }, {
2979 .compatible = "ontat,yx700wv03",
2980 .data = &ontat_yx700wv03,
2981 }, {
2982 .compatible = "ortustech,com43h4m85ulc",
2983 .data = &ortustech_com43h4m85ulc,
2984 }, {
2985 .compatible = "osddisplays,osd070t1718-19ts",
2986 .data = &osddisplays_osd070t1718_19ts,
2987 }, {
2988 .compatible = "pda,91-00156-a0",
2989 .data = &pda_91_00156_a0,
2990 }, {
2991 .compatible = "qiaodian,qd43003c0-40",
2992 .data = &qd43003c0_40,
2993 }, {
2994 .compatible = "rocktech,rk070er9427",
2995 .data = &rocktech_rk070er9427,
2996 }, {
2997 .compatible = "samsung,lsn122dl01-c01",
2998 .data = &samsung_lsn122dl01_c01,
2999 }, {
3000 .compatible = "samsung,ltn101nt05",
3001 .data = &samsung_ltn101nt05,
3002 }, {
3003 .compatible = "samsung,ltn140at29-301",
3004 .data = &samsung_ltn140at29_301,
3005 }, {
3006 .compatible = "sharp,lq035q7db03",
3007 .data = &sharp_lq035q7db03,
3008 }, {
3009 .compatible = "sharp,lq101k1ly04",
3010 .data = &sharp_lq101k1ly04,
3011 }, {
3012 .compatible = "sharp,lq123p1jx31",
3013 .data = &sharp_lq123p1jx31,
3014 }, {
3015 .compatible = "sharp,lq150x1lg11",
3016 .data = &sharp_lq150x1lg11,
3017 }, {
3018 .compatible = "shelly,sca07010-bfn-lnn",
3019 .data = &shelly_sca07010_bfn_lnn,
3020 }, {
3021 .compatible = "starry,kr122ea0sra",
3022 .data = &starry_kr122ea0sra,
3023 }, {
3024 .compatible = "tfc,s9700rtwv43tr-01b",
3025 .data = &tfc_s9700rtwv43tr_01b,
3026 }, {
3027 .compatible = "tianma,tm070jdhg30",
3028 .data = &tianma_tm070jdhg30,
3029 }, {
3030 .compatible = "tianma,tm070rvhg71",
3031 .data = &tianma_tm070rvhg71,
3032 }, {
3033 .compatible = "toshiba,lt089ac29000",
3034 .data = &toshiba_lt089ac29000,
3035 }, {
3036 .compatible = "tpk,f07a-0102",
3037 .data = &tpk_f07a_0102,
3038 }, {
3039 .compatible = "tpk,f10a-0102",
3040 .data = &tpk_f10a_0102,
3041 }, {
3042 .compatible = "urt,umsh-8596md-t",
3043 .data = &urt_umsh_8596md_parallel,
3044 }, {
3045 .compatible = "urt,umsh-8596md-1t",
3046 .data = &urt_umsh_8596md_parallel,
3047 }, {
3048 .compatible = "urt,umsh-8596md-7t",
3049 .data = &urt_umsh_8596md_parallel,
3050 }, {
3051 .compatible = "urt,umsh-8596md-11t",
3052 .data = &urt_umsh_8596md_lvds,
3053 }, {
3054 .compatible = "urt,umsh-8596md-19t",
3055 .data = &urt_umsh_8596md_lvds,
3056 }, {
3057 .compatible = "urt,umsh-8596md-20t",
3058 .data = &urt_umsh_8596md_parallel,
3059 }, {
3060 .compatible = "vxt,vl050-8048nt-c01",
3061 .data = &vl050_8048nt_c01,
3062 }, {
3063 .compatible = "winstar,wf35ltiacd",
3064 .data = &winstar_wf35ltiacd,
3065 }, {
3066
3067 }
3068};
3069MODULE_DEVICE_TABLE(of, platform_of_match);
3070
3071static int panel_simple_platform_probe(struct platform_device *pdev)
3072{
3073 const struct of_device_id *id;
3074
3075 id = of_match_node(platform_of_match, pdev->dev.of_node);
3076 if (!id)
3077 return -ENODEV;
3078
3079 return panel_simple_probe(&pdev->dev, id->data);
3080}
3081
3082static int panel_simple_platform_remove(struct platform_device *pdev)
3083{
3084 return panel_simple_remove(&pdev->dev);
3085}
3086
3087static void panel_simple_platform_shutdown(struct platform_device *pdev)
3088{
3089 panel_simple_shutdown(&pdev->dev);
3090}
3091
3092static struct platform_driver panel_simple_platform_driver = {
3093 .driver = {
3094 .name = "panel-simple",
3095 .of_match_table = platform_of_match,
3096 },
3097 .probe = panel_simple_platform_probe,
3098 .remove = panel_simple_platform_remove,
3099 .shutdown = panel_simple_platform_shutdown,
3100};
3101
3102struct panel_desc_dsi {
3103 struct panel_desc desc;
3104
3105 unsigned long flags;
3106 enum mipi_dsi_pixel_format format;
3107 unsigned int lanes;
3108};
3109
3110static const struct drm_display_mode auo_b080uan01_mode = {
3111 .clock = 154500,
3112 .hdisplay = 1200,
3113 .hsync_start = 1200 + 62,
3114 .hsync_end = 1200 + 62 + 4,
3115 .htotal = 1200 + 62 + 4 + 62,
3116 .vdisplay = 1920,
3117 .vsync_start = 1920 + 9,
3118 .vsync_end = 1920 + 9 + 2,
3119 .vtotal = 1920 + 9 + 2 + 8,
3120 .vrefresh = 60,
3121};
3122
3123static const struct panel_desc_dsi auo_b080uan01 = {
3124 .desc = {
3125 .modes = &auo_b080uan01_mode,
3126 .num_modes = 1,
3127 .bpc = 8,
3128 .size = {
3129 .width = 108,
3130 .height = 272,
3131 },
3132 },
3133 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3134 .format = MIPI_DSI_FMT_RGB888,
3135 .lanes = 4,
3136};
3137
3138static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3139 .clock = 160000,
3140 .hdisplay = 1200,
3141 .hsync_start = 1200 + 120,
3142 .hsync_end = 1200 + 120 + 20,
3143 .htotal = 1200 + 120 + 20 + 21,
3144 .vdisplay = 1920,
3145 .vsync_start = 1920 + 21,
3146 .vsync_end = 1920 + 21 + 3,
3147 .vtotal = 1920 + 21 + 3 + 18,
3148 .vrefresh = 60,
3149 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3150};
3151
3152static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3153 .desc = {
3154 .modes = &boe_tv080wum_nl0_mode,
3155 .num_modes = 1,
3156 .size = {
3157 .width = 107,
3158 .height = 172,
3159 },
3160 },
3161 .flags = MIPI_DSI_MODE_VIDEO |
3162 MIPI_DSI_MODE_VIDEO_BURST |
3163 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3164 .format = MIPI_DSI_FMT_RGB888,
3165 .lanes = 4,
3166};
3167
3168static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3169 .clock = 71000,
3170 .hdisplay = 800,
3171 .hsync_start = 800 + 32,
3172 .hsync_end = 800 + 32 + 1,
3173 .htotal = 800 + 32 + 1 + 57,
3174 .vdisplay = 1280,
3175 .vsync_start = 1280 + 28,
3176 .vsync_end = 1280 + 28 + 1,
3177 .vtotal = 1280 + 28 + 1 + 14,
3178 .vrefresh = 60,
3179};
3180
3181static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3182 .desc = {
3183 .modes = &lg_ld070wx3_sl01_mode,
3184 .num_modes = 1,
3185 .bpc = 8,
3186 .size = {
3187 .width = 94,
3188 .height = 151,
3189 },
3190 },
3191 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3192 .format = MIPI_DSI_FMT_RGB888,
3193 .lanes = 4,
3194};
3195
3196static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3197 .clock = 67000,
3198 .hdisplay = 720,
3199 .hsync_start = 720 + 12,
3200 .hsync_end = 720 + 12 + 4,
3201 .htotal = 720 + 12 + 4 + 112,
3202 .vdisplay = 1280,
3203 .vsync_start = 1280 + 8,
3204 .vsync_end = 1280 + 8 + 4,
3205 .vtotal = 1280 + 8 + 4 + 12,
3206 .vrefresh = 60,
3207};
3208
3209static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3210 .desc = {
3211 .modes = &lg_lh500wx1_sd03_mode,
3212 .num_modes = 1,
3213 .bpc = 8,
3214 .size = {
3215 .width = 62,
3216 .height = 110,
3217 },
3218 },
3219 .flags = MIPI_DSI_MODE_VIDEO,
3220 .format = MIPI_DSI_FMT_RGB888,
3221 .lanes = 4,
3222};
3223
3224static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3225 .clock = 157200,
3226 .hdisplay = 1920,
3227 .hsync_start = 1920 + 154,
3228 .hsync_end = 1920 + 154 + 16,
3229 .htotal = 1920 + 154 + 16 + 32,
3230 .vdisplay = 1200,
3231 .vsync_start = 1200 + 17,
3232 .vsync_end = 1200 + 17 + 2,
3233 .vtotal = 1200 + 17 + 2 + 16,
3234 .vrefresh = 60,
3235};
3236
3237static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3238 .desc = {
3239 .modes = &panasonic_vvx10f004b00_mode,
3240 .num_modes = 1,
3241 .bpc = 8,
3242 .size = {
3243 .width = 217,
3244 .height = 136,
3245 },
3246 },
3247 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3248 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3249 .format = MIPI_DSI_FMT_RGB888,
3250 .lanes = 4,
3251};
3252
3253static const struct drm_display_mode lg_acx467akm_7_mode = {
3254 .clock = 150000,
3255 .hdisplay = 1080,
3256 .hsync_start = 1080 + 2,
3257 .hsync_end = 1080 + 2 + 2,
3258 .htotal = 1080 + 2 + 2 + 2,
3259 .vdisplay = 1920,
3260 .vsync_start = 1920 + 2,
3261 .vsync_end = 1920 + 2 + 2,
3262 .vtotal = 1920 + 2 + 2 + 2,
3263 .vrefresh = 60,
3264};
3265
3266static const struct panel_desc_dsi lg_acx467akm_7 = {
3267 .desc = {
3268 .modes = &lg_acx467akm_7_mode,
3269 .num_modes = 1,
3270 .bpc = 8,
3271 .size = {
3272 .width = 62,
3273 .height = 110,
3274 },
3275 },
3276 .flags = 0,
3277 .format = MIPI_DSI_FMT_RGB888,
3278 .lanes = 4,
3279};
3280
3281static const struct drm_display_mode osd101t2045_53ts_mode = {
3282 .clock = 154500,
3283 .hdisplay = 1920,
3284 .hsync_start = 1920 + 112,
3285 .hsync_end = 1920 + 112 + 16,
3286 .htotal = 1920 + 112 + 16 + 32,
3287 .vdisplay = 1200,
3288 .vsync_start = 1200 + 16,
3289 .vsync_end = 1200 + 16 + 2,
3290 .vtotal = 1200 + 16 + 2 + 16,
3291 .vrefresh = 60,
3292 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3293};
3294
3295static const struct panel_desc_dsi osd101t2045_53ts = {
3296 .desc = {
3297 .modes = &osd101t2045_53ts_mode,
3298 .num_modes = 1,
3299 .bpc = 8,
3300 .size = {
3301 .width = 217,
3302 .height = 136,
3303 },
3304 },
3305 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3306 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3307 MIPI_DSI_MODE_EOT_PACKET,
3308 .format = MIPI_DSI_FMT_RGB888,
3309 .lanes = 4,
3310};
3311
3312static const struct of_device_id dsi_of_match[] = {
3313 {
3314 .compatible = "auo,b080uan01",
3315 .data = &auo_b080uan01
3316 }, {
3317 .compatible = "boe,tv080wum-nl0",
3318 .data = &boe_tv080wum_nl0
3319 }, {
3320 .compatible = "lg,ld070wx3-sl01",
3321 .data = &lg_ld070wx3_sl01
3322 }, {
3323 .compatible = "lg,lh500wx1-sd03",
3324 .data = &lg_lh500wx1_sd03
3325 }, {
3326 .compatible = "panasonic,vvx10f004b00",
3327 .data = &panasonic_vvx10f004b00
3328 }, {
3329 .compatible = "lg,acx467akm-7",
3330 .data = &lg_acx467akm_7
3331 }, {
3332 .compatible = "osddisplays,osd101t2045-53ts",
3333 .data = &osd101t2045_53ts
3334 }, {
3335
3336 }
3337};
3338MODULE_DEVICE_TABLE(of, dsi_of_match);
3339
3340static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3341{
3342 const struct panel_desc_dsi *desc;
3343 const struct of_device_id *id;
3344 int err;
3345
3346 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3347 if (!id)
3348 return -ENODEV;
3349
3350 desc = id->data;
3351
3352 err = panel_simple_probe(&dsi->dev, &desc->desc);
3353 if (err < 0)
3354 return err;
3355
3356 dsi->mode_flags = desc->flags;
3357 dsi->format = desc->format;
3358 dsi->lanes = desc->lanes;
3359
3360 err = mipi_dsi_attach(dsi);
3361 if (err) {
3362 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3363
3364 drm_panel_remove(&panel->base);
3365 }
3366
3367 return err;
3368}
3369
3370static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3371{
3372 int err;
3373
3374 err = mipi_dsi_detach(dsi);
3375 if (err < 0)
3376 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3377
3378 return panel_simple_remove(&dsi->dev);
3379}
3380
3381static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3382{
3383 panel_simple_shutdown(&dsi->dev);
3384}
3385
3386static struct mipi_dsi_driver panel_simple_dsi_driver = {
3387 .driver = {
3388 .name = "panel-simple-dsi",
3389 .of_match_table = dsi_of_match,
3390 },
3391 .probe = panel_simple_dsi_probe,
3392 .remove = panel_simple_dsi_remove,
3393 .shutdown = panel_simple_dsi_shutdown,
3394};
3395
3396static int __init panel_simple_init(void)
3397{
3398 int err;
3399
3400 err = platform_driver_register(&panel_simple_platform_driver);
3401 if (err < 0)
3402 return err;
3403
3404 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3405 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3406 if (err < 0)
3407 return err;
3408 }
3409
3410 return 0;
3411}
3412module_init(panel_simple_init);
3413
3414static void __exit panel_simple_exit(void)
3415{
3416 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3417 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3418
3419 platform_driver_unregister(&panel_simple_platform_driver);
3420}
3421module_exit(panel_simple_exit);
3422
3423MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3424MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3425MODULE_LICENSE("GPL and additional rights");
3426